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修订版13373 (tree)
时间2020-02-20 18:38:16
作者gdisirio

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更改概述

差异

--- trunk/demos/STM32/NIL-STM32L476-DISCOVERY/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/NIL-STM32L476-DISCOVERY/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/halconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/halconf.h (revision 13373)
@@ -44,7 +44,7 @@
4444 * @brief Enables the ADC subsystem.
4545 */
4646 #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
47-#define HAL_USE_ADC TRUE
47+#define HAL_USE_ADC FALSE
4848 #endif
4949
5050 /**
--- trunk/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/mcuconf.h (revision 13373)
@@ -50,7 +50,7 @@
5050 #define STM32_PLLSRC STM32_PLLSRC_HSI16
5151 #define STM32_PLLM_VALUE 2
5252 #define STM32_PLLN_VALUE 16
53-#define STM32_PLLP_VALUE 4
53+#define STM32_PLLP_VALUE 2
5454 #define STM32_PLLQ_VALUE 4
5555 #define STM32_PLLR_VALUE 2
5656 #define STM32_HPRE STM32_HPRE_DIV1
@@ -108,7 +108,7 @@
108108 #define STM32_ADC_ADC1_DMA_PRIORITY 2
109109 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
110110 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
111-#define STM32_ADC_PRESCALER_VALUE 1
111+#define STM32_ADC_PRESCALER_VALUE 2
112112
113113 /*
114114 * DAC driver system settings.
--- trunk/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h (revision 13373)
@@ -134,6 +134,7 @@
134134 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
135135 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
136136 #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
137+#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
137138
138139 /*
139140 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h (revision 13373)
@@ -155,6 +155,8 @@
155155 #define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
156156 #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
157157 #define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
158+#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
159+#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
158160
159161 /*
160162 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L432KC-NUCLEO32/cfg/mcuconf.h (revision 13373)
@@ -125,6 +125,7 @@
125125 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
126126 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
127127 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
128+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
128129
129130 /*
130131 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L452RE-NUCLEO64-P/cfg/mcuconf.h (revision 13373)
@@ -130,6 +130,7 @@
130130 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
131131 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
132132 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
133+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
133134
134135 /*
135136 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L476-DISCOVERY/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_DYNAMIC/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_DYNAMIC/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_STATIC/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L476-DISCOVERY-SB_HOST_STATIC/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L476RG-NUCLEO64/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L476RG-NUCLEO64/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L496ZG-NUCLEO144/cfg/mcuconf.h (revision 13373)
@@ -152,6 +152,7 @@
152152 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
153153 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
154154 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
155+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
155156
156157 /*
157158 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h (revision 13372)
+++ trunk/demos/STM32/RT-STM32L4R9-DISCOVERY/cfg/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c (revision 13372)
+++ trunk/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c (revision 13373)
@@ -58,6 +58,23 @@
5858 /*===========================================================================*/
5959
6060 /**
61+ * @brief ADC voltage regulator enable.
62+ *
63+ * @param[in] adc pointer to the ADC registers block
64+ */
65+NOINLINE static void adc_lld_vreg_on(ADC_TypeDef *adc) {
66+ volatile uint32_t loop;
67+
68+ osalDbgAssert(adc->CR == 0, "invalid register state");
69+
70+ adc->CR = ADC_CR_ADVREGEN;
71+ loop = (STM32_HCLK >> 20) << 4;
72+ do {
73+ loop--;
74+ } while (loop > 0);
75+}
76+
77+/**
6178 * @brief Stops an ongoing conversion, if any.
6279 *
6380 * @param[in] adc pointer to the ADC registers block
@@ -167,11 +184,13 @@
167184 ADC->CCR = 0;
168185 #endif
169186
170- osalDbgAssert(ADC1->CR == 0, "invalid register state");
187+ /* Regulator enabled and stabilized before calibration.*/
188+ adc_lld_vreg_on(ADC1);
189+
171190 ADC1->CR |= ADC_CR_ADCAL;
172- osalDbgAssert(ADC1->CR != 0, "invalid register state");
173191 while (ADC1->CR & ADC_CR_ADCAL)
174192 ;
193+ ADC1->CR = 0;
175194 rccDisableADC1();
176195 }
177196
@@ -206,6 +225,9 @@
206225 }
207226 #endif /* STM32_ADC_USE_ADC1 */
208227
228+ /* Regulator enabled and stabilized before calibration.*/
229+ adc_lld_vreg_on(ADC1);
230+
209231 /* ADC initial setup, starting the analog part here in order to reduce
210232 the latency when starting a conversion.*/
211233 adcp->adc->CR = ADC_CR_ADEN;
@@ -244,6 +266,9 @@
244266 ;
245267 }
246268
269+ /* Regulator and anything else off.*/
270+ adcp->adc->CR = 0;
271+
247272 #if STM32_ADC_USE_ADC1
248273 if (&ADCD1 == adcp)
249274 rccDisableADC1();
--- trunk/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h (revision 13372)
+++ trunk/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h (revision 13373)
@@ -161,7 +161,7 @@
161161 * default, @p STM32_ADC_CKMODE_ADCCLK).
162162 */
163163 #if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__)
164-#define STM32_ADC_PRESCALER_VALUE 1
164+#define STM32_ADC_PRESCALER_VALUE 2
165165 #endif
166166 #endif
167167
@@ -188,6 +188,10 @@
188188 #error "STM32_HAS_ADC1 not defined in registry"
189189 #endif
190190
191+#if !defined(STM32_ADC_SUPPORTS_PRESCALER)
192+#error "STM32_ADC_SUPPORTS_PRESCALER not defined in registry"
193+#endif
194+
191195 #if (STM32_ADC_USE_ADC1 && !defined(STM32_ADC1_HANDLER))
192196 #error "STM32_ADC1_HANDLER not defined in registry"
193197 #endif
@@ -246,9 +250,7 @@
246250
247251 /* ADC clock source checks.*/
248252 #if STM32_ADC_SUPPORTS_PRESCALER == TRUE
249-#if STM32_ADC_PRESCALER_VALUE == 1
250-#define STM32_ADC_PRESC 0U
251-#elif STM32_ADC_PRESCALER_VALUE == 2
253+#if STM32_ADC_PRESCALER_VALUE == 2
252254 #define STM32_ADC_PRESC 1U
253255 #elif STM32_ADC_PRESCALER_VALUE == 4
254256 #define STM32_ADC_PRESC 2U
--- trunk/os/hal/ports/STM32/STM32G0xx/hal_lld.h (revision 13372)
+++ trunk/os/hal/ports/STM32/STM32G0xx/hal_lld.h (revision 13373)
@@ -264,7 +264,7 @@
264264 #define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U)
265265
266266 #define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */
267-#define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */
267+#define STM32_ADCSEL_SYSCLK (0U << 30U) /**< ADC source is SYSCLK. */
268268 #define STM32_ADCSEL_PLLPCLK (1U << 30U) /**< ADC source is PLLPCLK. */
269269 #define STM32_ADCSEL_HSI16 (2U << 30U) /**< ADC source is HSI16. */
270270 /** @} */
@@ -402,7 +402,7 @@
402402 * @note The allowed values are 2..32.
403403 */
404404 #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
405-#define STM32_PLLP_VALUE 4
405+#define STM32_PLLP_VALUE 2
406406 #endif
407407
408408 /**
@@ -1463,8 +1463,8 @@
14631463 /**
14641464 * @brief ADC clock frequency.
14651465 */
1466-#if (STM32_ADCSEL == STM32_ADCSEL_NOCLK) || defined(__DOXYGEN__)
1467-#define STM32_ADCCLK 0
1466+#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
1467+#define STM32_ADCCLK STM32_SYSCLK
14681468 #elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
14691469 #define STM32_ADCCLK STM32_PLL_P_CLKOUT
14701470 #elif STM32_ADCSEL == STM32_ADCSEL_HSI16
--- trunk/os/hal/ports/STM32/STM32G4xx/hal_lld.h (revision 13372)
+++ trunk/os/hal/ports/STM32/STM32G4xx/hal_lld.h (revision 13373)
@@ -51,13 +51,13 @@
5151 */
5252 #if defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || \
5353 defined(__DOXYGEN__)
54-#define PLATFORM_NAME "STM32G04 Access Line"
54+#define PLATFORM_NAME "STM32G4 Access Line"
5555
5656 #elif defined(STM32G473xx)
57-#define PLATFORM_NAME "STM32G0 Performance Line"
57+#define PLATFORM_NAME "STM32G4 Performance Line"
5858
5959 #elif defined(STM32G483xx)
60-#define PLATFORM_NAME "STM32G0 Performance Line with Crypto"
60+#define PLATFORM_NAME "STM32G4 Performance Line with Crypto"
6161
6262 #elif defined(STM32G474xx)
6363 #define PLATFORM_NAME "STM32G4 Hi-resolution Line"
--- trunk/testex/STM32/STM32L4xx/SPI-L3GD20/cfg/mcuconf.h (revision 13372)
+++ trunk/testex/STM32/STM32L4xx/SPI-L3GD20/cfg/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/STM32L4xx/CAN/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/STM32L4xx/CAN/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/STM32L4xx/IRQ_STORM/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/ADC/cfg/stm32g071rb_nucleo64/mcuconf.h (revision 13373)
@@ -50,7 +50,7 @@
5050 #define STM32_PLLSRC STM32_PLLSRC_HSI16
5151 #define STM32_PLLM_VALUE 2
5252 #define STM32_PLLN_VALUE 16
53-#define STM32_PLLP_VALUE 4
53+#define STM32_PLLP_VALUE 2
5454 #define STM32_PLLQ_VALUE 4
5555 #define STM32_PLLR_VALUE 2
5656 #define STM32_HPRE STM32_HPRE_DIV1
@@ -108,7 +108,7 @@
108108 #define STM32_ADC_ADC1_DMA_PRIORITY 2
109109 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
110110 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
111-#define STM32_ADC_PRESCALER_VALUE 1
111+#define STM32_ADC_PRESCALER_VALUE 2
112112
113113 /*
114114 * DAC driver system settings.
--- trunk/testhal/STM32/multi/ADC/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/ADC/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/ADC/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/DAC/cfg/stm32g474re_nucleo64/mcuconf.h (revision 13373)
@@ -155,6 +155,8 @@
155155 #define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
156156 #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
157157 #define STM32_ADC_ADC345_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
158+#define STM32_ADC_ADC12_PRESC ADC_CCR_PRESC_DIV2
159+#define STM32_ADC_ADC345_PRESC ADC_CCR_PRESC_DIV2
158160
159161 /*
160162 * CAN driver system settings.
--- trunk/testhal/STM32/multi/DAC/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/DAC/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/DAC/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/EFL-MFS/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/EFL-MFS/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/PAL/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/RTC/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/RTC/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/RTC/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/SDMMC-FATFS/cfg/stm32l4r9ai_discovery/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/SPI/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/SPI/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/SPI/cfg/stm32l4r9_discovery/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/TRNG/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/TRNG/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/TRNG/cfg/stm32l4r5zi_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/USB_CDC/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
--- trunk/testhal/STM32/multi/WSPI-MFS/cfg/stm32l476_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/WSPI-MFS/cfg/stm32l476_discovery/mcuconf.h (revision 13373)
@@ -149,6 +149,7 @@
149149 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
150150 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
151151 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
152+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
152153
153154 /*
154155 * CAN driver system settings.
--- trunk/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h (revision 13372)
+++ trunk/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h (revision 13373)
@@ -157,6 +157,7 @@
157157 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
158158 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
159159 #define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
160+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
160161
161162 /*
162163 * CAN driver system settings.
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