| 修订版 | 14625 (tree) |
|---|---|
| 时间 | 2021-07-26 18:31:10 |
| 作者 | vrepetenko |
Fixed warnings with STATIC_INLINE, modified target core checks.
trunk/os/hal/ports/STM32/STM32WLxx/hal_lld.c (diff)
trunk/os/hal/ports/STM32/STM32WLxx/hal_lld.h (diff) trunk/os/hal/ports/STM32/STM32WLxx/stm32_registry.h (diff)| @@ -202,13 +202,12 @@ | ||
| 202 | 202 | /* Driver local functions. */ |
| 203 | 203 | /*===========================================================================*/ |
| 204 | 204 | |
| 205 | -#if (STM32_NO_INIT == FALSE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) || defined(__DOXYGEN__) | |
| 206 | 205 | /** |
| 207 | 206 | * @brief Safe setting of flash ACR register. |
| 208 | 207 | * |
| 209 | 208 | * @param[in] acr value for the ACR register |
| 210 | 209 | */ |
| 211 | -static void flash_set_acr(uint32_t acr) { | |
| 210 | +__STATIC_INLINE void flash_set_acr(uint32_t acr) { | |
| 212 | 211 | |
| 213 | 212 | FLASH->ACR = acr; |
| 214 | 213 | while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) { |
| @@ -215,14 +214,12 @@ | ||
| 215 | 214 | /* Waiting for flash wait states setup.*/ |
| 216 | 215 | } |
| 217 | 216 | } |
| 218 | -#endif /* (STM32_NO_INIT == TRUE || defined(HAL_LLD_USE_CLOCK_MANAGEMENT)) */ | |
| 219 | 217 | |
| 220 | -#if (STM32_NO_INIT == FALSE) || defined(__DOXYGEN__) | |
| 221 | 218 | /** |
| 222 | 219 | * @brief Configures the PWR unit. |
| 223 | 220 | * @note CR1, CR2 and CR5 are not initialized inside this function. |
| 224 | 221 | */ |
| 225 | -static void hal_lld_set_static_pwr(void) { | |
| 222 | +__STATIC_INLINE void hal_lld_set_static_pwr(void) { | |
| 226 | 223 | |
| 227 | 224 | /* Static PWR configurations.*/ |
| 228 | 225 | PWR->CR3 = STM32_PWR_CR3; |
| @@ -240,7 +237,7 @@ | ||
| 240 | 237 | /** |
| 241 | 238 | * @brief Initializes static muxes and dividers. |
| 242 | 239 | */ |
| 243 | -static void hal_lld_set_static_clocks(void) { | |
| 240 | +__STATIC_INLINE void hal_lld_set_static_clocks(void) { | |
| 244 | 241 | |
| 245 | 242 | uint32_t ccipr; |
| 246 | 243 |
| @@ -258,7 +255,6 @@ | ||
| 258 | 255 | |
| 259 | 256 | RCC->CCIPR = ccipr; |
| 260 | 257 | } |
| 261 | -#endif /* (STM32_NO_INIT == FALSE) */ | |
| 262 | 258 | |
| 263 | 259 | #if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__) |
| 264 | 260 | static bool hal_lld_check_pll(const system_limits_t *slp, |
| @@ -368,14 +368,6 @@ | ||
| 368 | 368 | #endif |
| 369 | 369 | |
| 370 | 370 | /** |
| 371 | - * @brief Target code for this HAL configuration. | |
| 372 | - * @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+. | |
| 373 | - */ | |
| 374 | -#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__) | |
| 375 | -#define STM32_TARGET_CORE 1 | |
| 376 | -#endif | |
| 377 | - | |
| 378 | -/** | |
| 379 | 371 | * @brief Enables the dynamic clock handling. |
| 380 | 372 | */ |
| 381 | 373 | #if !defined(STM32_CLOCK_DYNAMIC) || defined(__DOXYGEN__) |
| @@ -734,12 +726,11 @@ | ||
| 734 | 726 | #error "Using a wrong mcuconf.h file, STM32WLxx_MCUCONF not defined" |
| 735 | 727 | #endif |
| 736 | 728 | |
| 737 | -/** | |
| 738 | - * @brief Target core for this HAL configuration. | |
| 739 | - * @note Core 1 is the Cortex-M4, core 2 is the Cortex-M0+. | |
| 729 | +/* | |
| 730 | + * Target core checks. | |
| 740 | 731 | */ |
| 741 | -#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__) | |
| 742 | -#define STM32_TARGET_CORE 1 | |
| 732 | +#if !defined(STM32_TARGET_CORE) | |
| 733 | +#error "STM32_TARGET_CORE not defined in mcuconf.h" | |
| 743 | 734 | #endif |
| 744 | 735 | |
| 745 | 736 | #if (STM32_TARGET_CORE == 2) && (STM32_HAS_M0 == FALSE) |
| @@ -748,7 +739,7 @@ | ||
| 748 | 739 | |
| 749 | 740 | #if (defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 1)) || \ |
| 750 | 741 | (!defined(CORE_CM0PLUS) && (STM32_TARGET_CORE == 2)) |
| 751 | -#error "wrong target core specified" | |
| 742 | +#error "wrong target core specified in mcuconf.h" | |
| 752 | 743 | #endif |
| 753 | 744 | |
| 754 | 745 | /* |
| @@ -200,7 +200,7 @@ | ||
| 200 | 200 | #define STM32_RTC_TAMP_STAMP_EXTI 19 |
| 201 | 201 | #define STM32_RTC_WKUP_EXTI 20 |
| 202 | 202 | |
| 203 | -#if STM32_TARGET_CORE == 1 | |
| 203 | +#if !defined(CORE_CM0PLUS) | |
| 204 | 204 | |
| 205 | 205 | #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 |
| 206 | 206 | #define STM32_RTC_WKUP_HANDLER Vector4C |
| @@ -221,7 +221,7 @@ | ||
| 221 | 221 | #define STM32_RTC_IRQ_ENABLE() \ |
| 222 | 222 | nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY) |
| 223 | 223 | |
| 224 | -#endif /* STM32_TARGET_CORE == 1 */ | |
| 224 | +#endif /* !defined(CORE_CM0PLUS) */ | |
| 225 | 225 | |
| 226 | 226 | /* Enabling RTC-related EXTI lines.*/ |
| 227 | 227 | #define STM32_RTC_ENABLE_ALL_EXTI() do { \ |
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