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修订版15835 (tree)
时间2022-11-14 17:48:56
作者gdisirio

Log Message

Tentative SPIv3 fix.

更改概述

差异

--- trunk/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c (revision 15834)
+++ trunk/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c (revision 15835)
@@ -88,22 +88,22 @@
8888 spip->spi->CFG2 = (spip->config->cfg2 | SPI_CFG2_MASTER | SPI_CFG2_SSOE) &
8989 ~SPI_CFG2_COMM_Msk;
9090 }
91+ spip->spi->CR1 = SPI_CR1_MASRX | SPI_CR1_SPE;
9192 }
9293
93-static void spi_lld_start_transfer(SPIDriver *spip) {
94- uint32_t cr1;
94+static void spi_lld_resume(SPIDriver *spip) {
9595
96- cr1 = spip->spi->CR1;
97- spip->spi->CR1 = cr1 | SPI_CR1_SPE;
98-
9996 if (!spip->config->slave) {
100- spip->spi->CR1 = cr1 | SPI_CR1_SPE | SPI_CR1_CSTART;
97+ spip->spi->CR1 |= SPI_CR1_CSTART;
10198 }
10299 }
103100
104-static void spi_lld_wait_complete(SPIDriver *spip) {
101+static void spi_lld_suspend(SPIDriver *spip) {
105102
106- while ((spip->spi->CR1 & SPI_CR1_CSTART) != 0) {
103+ if (!spip->config->slave) {
104+ spip->spi->CR1 |= SPI_CR1_CSUSP;
105+ while ((spip->spi->CR1 & SPI_CR1_CSTART) != 0U) {
106+ }
107107 }
108108 spip->spi->IFCR = 0xFFFFFFFF;
109109 }
@@ -229,9 +229,8 @@
229229 #endif
230230
231231 /* Stopping SPI.*/
232- spip->spi->CR1 |= SPI_CR1_CSUSP;
233- spi_lld_wait_complete(spip);
234- spip->spi->CR1 &= ~SPI_CR1_SPE;
232+ spi_lld_suspend(spip);
233+// spip->spi->CR1 &= ~SPI_CR1_SPE;
235234
236235 return HAL_RET_SUCCESS;
237236 }
@@ -1072,8 +1071,6 @@
10721071
10731072 osalDbgAssert(n < 65536, "unsupported DMA transfer size");
10741073
1075- spi_lld_wait_complete(spip);
1076-
10771074 #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
10781075 if (spip->is_bdma)
10791076 #endif
@@ -1109,7 +1106,7 @@
11091106 }
11101107 #endif
11111108
1112- spi_lld_start_transfer(spip);
1109+ spi_lld_resume(spip);
11131110
11141111 return HAL_RET_SUCCESS;
11151112 }
@@ -1170,7 +1167,7 @@
11701167 }
11711168 #endif
11721169
1173- spi_lld_start_transfer(spip);
1170+ spi_lld_resume(spip);
11741171
11751172 return HAL_RET_SUCCESS;
11761173 }
@@ -1228,7 +1225,7 @@
12281225 }
12291226 #endif
12301227
1231- spi_lld_start_transfer(spip);
1228+ spi_lld_resume(spip);
12321229
12331230 return HAL_RET_SUCCESS;
12341231 }
@@ -1286,7 +1283,7 @@
12861283 }
12871284 #endif
12881285
1289- spi_lld_start_transfer(spip);
1286+ spi_lld_resume(spip);
12901287
12911288 return HAL_RET_SUCCESS;
12921289 }
@@ -1347,7 +1344,7 @@
13471344 uint32_t dsize = (spip->spi->CFG1 & SPI_CFG1_DSIZE_Msk) + 1U;
13481345 uint32_t rxframe;
13491346
1350- spi_lld_start_transfer(spip);
1347+ spi_lld_resume(spip);
13511348
13521349 /* wait for room in TX FIFO.*/
13531350 while ((spip->spi->SR & SPI_SR_TXP) == 0U)
@@ -1381,9 +1378,8 @@
13811378 rxframe = spip->spi->RXDR;
13821379 }
13831380
1384- spip->spi->CR1 |= SPI_CR1_CSUSP;
1385- spi_lld_wait_complete(spip);
1386- spip->spi->CR1 &= ~SPI_CR1_SPE;
1381+ spi_lld_suspend(spip);
1382+// spip->spi->CR1 &= ~SPI_CR1_SPE;
13871383
13881384 return rxframe;
13891385 }
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