Tentative SPIv3 fix.
| @@ -88,22 +88,22 @@ | ||
| 88 | 88 | spip->spi->CFG2 = (spip->config->cfg2 | SPI_CFG2_MASTER | SPI_CFG2_SSOE) & |
| 89 | 89 | ~SPI_CFG2_COMM_Msk; |
| 90 | 90 | } |
| 91 | + spip->spi->CR1 = SPI_CR1_MASRX | SPI_CR1_SPE; | |
| 91 | 92 | } |
| 92 | 93 | |
| 93 | -static void spi_lld_start_transfer(SPIDriver *spip) { | |
| 94 | - uint32_t cr1; | |
| 94 | +static void spi_lld_resume(SPIDriver *spip) { | |
| 95 | 95 | |
| 96 | - cr1 = spip->spi->CR1; | |
| 97 | - spip->spi->CR1 = cr1 | SPI_CR1_SPE; | |
| 98 | - | |
| 99 | 96 | if (!spip->config->slave) { |
| 100 | - spip->spi->CR1 = cr1 | SPI_CR1_SPE | SPI_CR1_CSTART; | |
| 97 | + spip->spi->CR1 |= SPI_CR1_CSTART; | |
| 101 | 98 | } |
| 102 | 99 | } |
| 103 | 100 | |
| 104 | -static void spi_lld_wait_complete(SPIDriver *spip) { | |
| 101 | +static void spi_lld_suspend(SPIDriver *spip) { | |
| 105 | 102 | |
| 106 | - while ((spip->spi->CR1 & SPI_CR1_CSTART) != 0) { | |
| 103 | + if (!spip->config->slave) { | |
| 104 | + spip->spi->CR1 |= SPI_CR1_CSUSP; | |
| 105 | + while ((spip->spi->CR1 & SPI_CR1_CSTART) != 0U) { | |
| 106 | + } | |
| 107 | 107 | } |
| 108 | 108 | spip->spi->IFCR = 0xFFFFFFFF; |
| 109 | 109 | } |
| @@ -229,9 +229,8 @@ | ||
| 229 | 229 | #endif |
| 230 | 230 | |
| 231 | 231 | /* Stopping SPI.*/ |
| 232 | - spip->spi->CR1 |= SPI_CR1_CSUSP; | |
| 233 | - spi_lld_wait_complete(spip); | |
| 234 | - spip->spi->CR1 &= ~SPI_CR1_SPE; | |
| 232 | + spi_lld_suspend(spip); | |
| 233 | +// spip->spi->CR1 &= ~SPI_CR1_SPE; | |
| 235 | 234 | |
| 236 | 235 | return HAL_RET_SUCCESS; |
| 237 | 236 | } |
| @@ -1072,8 +1071,6 @@ | ||
| 1072 | 1071 | |
| 1073 | 1072 | osalDbgAssert(n < 65536, "unsupported DMA transfer size"); |
| 1074 | 1073 | |
| 1075 | - spi_lld_wait_complete(spip); | |
| 1076 | - | |
| 1077 | 1074 | #if defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED) |
| 1078 | 1075 | if (spip->is_bdma) |
| 1079 | 1076 | #endif |
| @@ -1109,7 +1106,7 @@ | ||
| 1109 | 1106 | } |
| 1110 | 1107 | #endif |
| 1111 | 1108 | |
| 1112 | - spi_lld_start_transfer(spip); | |
| 1109 | + spi_lld_resume(spip); | |
| 1113 | 1110 | |
| 1114 | 1111 | return HAL_RET_SUCCESS; |
| 1115 | 1112 | } |
| @@ -1170,7 +1167,7 @@ | ||
| 1170 | 1167 | } |
| 1171 | 1168 | #endif |
| 1172 | 1169 | |
| 1173 | - spi_lld_start_transfer(spip); | |
| 1170 | + spi_lld_resume(spip); | |
| 1174 | 1171 | |
| 1175 | 1172 | return HAL_RET_SUCCESS; |
| 1176 | 1173 | } |
| @@ -1228,7 +1225,7 @@ | ||
| 1228 | 1225 | } |
| 1229 | 1226 | #endif |
| 1230 | 1227 | |
| 1231 | - spi_lld_start_transfer(spip); | |
| 1228 | + spi_lld_resume(spip); | |
| 1232 | 1229 | |
| 1233 | 1230 | return HAL_RET_SUCCESS; |
| 1234 | 1231 | } |
| @@ -1286,7 +1283,7 @@ | ||
| 1286 | 1283 | } |
| 1287 | 1284 | #endif |
| 1288 | 1285 | |
| 1289 | - spi_lld_start_transfer(spip); | |
| 1286 | + spi_lld_resume(spip); | |
| 1290 | 1287 | |
| 1291 | 1288 | return HAL_RET_SUCCESS; |
| 1292 | 1289 | } |
| @@ -1347,7 +1344,7 @@ | ||
| 1347 | 1344 | uint32_t dsize = (spip->spi->CFG1 & SPI_CFG1_DSIZE_Msk) + 1U; |
| 1348 | 1345 | uint32_t rxframe; |
| 1349 | 1346 | |
| 1350 | - spi_lld_start_transfer(spip); | |
| 1347 | + spi_lld_resume(spip); | |
| 1351 | 1348 | |
| 1352 | 1349 | /* wait for room in TX FIFO.*/ |
| 1353 | 1350 | while ((spip->spi->SR & SPI_SR_TXP) == 0U) |
| @@ -1381,9 +1378,8 @@ | ||
| 1381 | 1378 | rxframe = spip->spi->RXDR; |
| 1382 | 1379 | } |
| 1383 | 1380 | |
| 1384 | - spip->spi->CR1 |= SPI_CR1_CSUSP; | |
| 1385 | - spi_lld_wait_complete(spip); | |
| 1386 | - spip->spi->CR1 &= ~SPI_CR1_SPE; | |
| 1381 | + spi_lld_suspend(spip); | |
| 1382 | +// spip->spi->CR1 &= ~SPI_CR1_SPE; | |
| 1387 | 1383 | |
| 1388 | 1384 | return rxframe; |
| 1389 | 1385 | } |
ChibiOS
gdisirio
trunk/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c