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修订版	15842 (tree)
时间	2022-11-20 17:51:07
作者	gdisirio

Log Message

Fixed bug #1241.

更改概述

modified: branches/stable_20.3.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (diff)
modified: branches/stable_20.3.x/readme.txt (diff)
modified: branches/stable_21.11.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (diff)
modified: branches/stable_21.11.x/readme.txt (diff)
modified: trunk/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (diff)
modified: trunk/readme.txt (diff)

差异

--- branches/stable_20.3.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15841)

+++ branches/stable_20.3.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15842)

		@@ -1,1153 +1,1154 @@
1		-/*
2		- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3		-
4		- Licensed under the Apache License, Version 2.0 (the "License");
5		- you may not use this file except in compliance with the License.
6		- You may obtain a copy of the License at
7		-
8		- http://www.apache.org/licenses/LICENSE-2.0
9		-
10		- Unless required by applicable law or agreed to in writing, software
11		- distributed under the License is distributed on an "AS IS" BASIS,
12		- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13		- See the License for the specific language governing permissions and
14		- limitations under the License.
15		-*/
16		-
17		-/**
18		- * @file TIMv1/hal_gpt_lld.c
19		- * @brief STM32 GPT subsystem low level driver source.
20		- *
21		- * @addtogroup GPT
22		- * @{
23		- */
24		-
25		-#include "hal.h"
26		-
27		-#if HAL_USE_GPT \|\| defined(__DOXYGEN__)
28		-
29		-/===========================================================================/
30		-/* Driver local definitions. */
31		-/===========================================================================/
32		-
33		-/===========================================================================/
34		-/* Driver exported variables. */
35		-/===========================================================================/
36		-
37		-/**
38		- * @brief GPTD1 driver identifier.
39		- * @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
40		- */
41		-#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
42		-GPTDriver GPTD1;
43		-#endif
44		-
45		-/**
46		- * @brief GPTD2 driver identifier.
47		- * @note The driver GPTD2 allocates the timer TIM2 when enabled.
48		- */
49		-#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
50		-GPTDriver GPTD2;
51		-#endif
52		-
53		-/**
54		- * @brief GPTD3 driver identifier.
55		- * @note The driver GPTD3 allocates the timer TIM3 when enabled.
56		- */
57		-#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
58		-GPTDriver GPTD3;
59		-#endif
60		-
61		-/**
62		- * @brief GPTD4 driver identifier.
63		- * @note The driver GPTD4 allocates the timer TIM4 when enabled.
64		- */
65		-#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
66		-GPTDriver GPTD4;
67		-#endif
68		-
69		-/**
70		- * @brief GPTD5 driver identifier.
71		- * @note The driver GPTD5 allocates the timer TIM5 when enabled.
72		- */
73		-#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
74		-GPTDriver GPTD5;
75		-#endif
76		-
77		-/**
78		- * @brief GPTD6 driver identifier.
79		- * @note The driver GPTD6 allocates the timer TIM6 when enabled.
80		- */
81		-#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
82		-GPTDriver GPTD6;
83		-#endif
84		-
85		-/**
86		- * @brief GPTD7 driver identifier.
87		- * @note The driver GPTD7 allocates the timer TIM7 when enabled.
88		- */
89		-#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
90		-GPTDriver GPTD7;
91		-#endif
92		-
93		-/**
94		- * @brief GPTD8 driver identifier.
95		- * @note The driver GPTD8 allocates the timer TIM8 when enabled.
96		- */
97		-#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
98		-GPTDriver GPTD8;
99		-#endif
100		-
101		-/**
102		- * @brief GPTD9 driver identifier.
103		- * @note The driver GPTD9 allocates the timer TIM9 when enabled.
104		- */
105		-#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
106		-GPTDriver GPTD9;
107		-#endif
108		-
109		-/**
110		- * @brief GPTD10 driver identifier.
111		- * @note The driver GPTD10 allocates the timer TIM10 when enabled.
112		- */
113		-#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
114		-GPTDriver GPTD10;
115		-#endif
116		-
117		-/**
118		- * @brief GPTD11 driver identifier.
119		- * @note The driver GPTD11 allocates the timer TIM11 when enabled.
120		- */
121		-#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
122		-GPTDriver GPTD11;
123		-#endif
124		-
125		-/**
126		- * @brief GPTD12 driver identifier.
127		- * @note The driver GPTD12 allocates the timer TIM12 when enabled.
128		- */
129		-#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
130		-GPTDriver GPTD12;
131		-#endif
132		-
133		-/**
134		- * @brief GPTD13 driver identifier.
135		- * @note The driver GPTD13 allocates the timer TIM13 when enabled.
136		- */
137		-#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
138		-GPTDriver GPTD13;
139		-#endif
140		-
141		-/**
142		- * @brief GPTD14 driver identifier.
143		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
144		- */
145		-#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
146		-GPTDriver GPTD14;
147		-#endif
148		-
149		-/**
150		- * @brief GPTD15 driver identifier.
151		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
152		- */
153		-#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
154		-GPTDriver GPTD15;
155		-#endif
156		-
157		-/**
158		- * @brief GPTD16 driver identifier.
159		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
160		- */
161		-#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
162		-GPTDriver GPTD16;
163		-#endif
164		-
165		-/**
166		- * @brief GPTD17 driver identifier.
167		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
168		- */
169		-#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
170		-GPTDriver GPTD17;
171		-#endif
172		-
173		-/**
174		- * @brief GPTD21 driver identifier.
175		- * @note The driver GPTD21 allocates the timer TIM21 when enabled.
176		- */
177		-#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
178		-GPTDriver GPTD21;
179		-#endif
180		-
181		-/**
182		- * @brief GPTD22 driver identifier.
183		- * @note The driver GPTD22 allocates the timer TIM22 when enabled.
184		- */
185		-#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
186		-GPTDriver GPTD22;
187		-#endif
188		-
189		-/===========================================================================/
190		-/* Driver local variables and types. */
191		-/===========================================================================/
192		-
193		-/===========================================================================/
194		-/* Driver local functions. */
195		-/===========================================================================/
196		-
197		-/===========================================================================/
198		-/* Driver interrupt handlers. */
199		-/===========================================================================/
200		-
201		-#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
202		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
203		-#if !defined(STM32_TIM1_UP_HANDLER)
204		-#error "STM32_TIM1_UP_HANDLER not defined"
205		-#endif
206		-/**
207		- * @brief TIM1 interrupt handler.
208		- *
209		- * @isr
210		- */
211		-OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
212		-
213		- OSAL_IRQ_PROLOGUE();
214		-
215		- gpt_lld_serve_interrupt(&GPTD1);
216		-
217		- OSAL_IRQ_EPILOGUE();
218		-}
219		-#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
220		-#endif /* STM32_GPT_USE_TIM1 */
221		-
222		-#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
223		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
224		-#if !defined(STM32_TIM2_HANDLER)
225		-#error "STM32_TIM2_HANDLER not defined"
226		-#endif
227		-/**
228		- * @brief TIM2 interrupt handler.
229		- *
230		- * @isr
231		- */
232		-OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
233		-
234		- OSAL_IRQ_PROLOGUE();
235		-
236		- gpt_lld_serve_interrupt(&GPTD2);
237		-
238		- OSAL_IRQ_EPILOGUE();
239		-}
240		-#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
241		-#endif /* STM32_GPT_USE_TIM2 */
242		-
243		-#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
244		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
245		-#if !defined(STM32_TIM3_HANDLER)
246		-#error "STM32_TIM3_HANDLER not defined"
247		-#endif
248		-/**
249		- * @brief TIM3 interrupt handler.
250		- *
251		- * @isr
252		- */
253		-OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
254		-
255		- OSAL_IRQ_PROLOGUE();
256		-
257		- gpt_lld_serve_interrupt(&GPTD3);
258		-
259		- OSAL_IRQ_EPILOGUE();
260		-}
261		-#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
262		-#endif /* STM32_GPT_USE_TIM3 */
263		-
264		-#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
265		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
266		-#if !defined(STM32_TIM4_HANDLER)
267		-#error "STM32_TIM4_HANDLER not defined"
268		-#endif
269		-/**
270		- * @brief TIM4 interrupt handler.
271		- *
272		- * @isr
273		- */
274		-OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
275		-
276		- OSAL_IRQ_PROLOGUE();
277		-
278		- gpt_lld_serve_interrupt(&GPTD4);
279		-
280		- OSAL_IRQ_EPILOGUE();
281		-}
282		-#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
283		-#endif /* STM32_GPT_USE_TIM4 */
284		-
285		-#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
286		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
287		-#if !defined(STM32_TIM5_HANDLER)
288		-#error "STM32_TIM5_HANDLER not defined"
289		-#endif
290		-/**
291		- * @brief TIM5 interrupt handler.
292		- *
293		- * @isr
294		- */
295		-OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
296		-
297		- OSAL_IRQ_PROLOGUE();
298		-
299		- gpt_lld_serve_interrupt(&GPTD5);
300		-
301		- OSAL_IRQ_EPILOGUE();
302		-}
303		-#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
304		-#endif /* STM32_GPT_USE_TIM5 */
305		-
306		-#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
307		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
308		-#if !defined(STM32_TIM6_HANDLER)
309		-#error "STM32_TIM6_HANDLER not defined"
310		-#endif
311		-/**
312		- * @brief TIM6 interrupt handler.
313		- *
314		- * @isr
315		- */
316		-OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
317		-
318		- OSAL_IRQ_PROLOGUE();
319		-
320		- gpt_lld_serve_interrupt(&GPTD6);
321		-
322		- OSAL_IRQ_EPILOGUE();
323		-}
324		-#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
325		-#endif /* STM32_GPT_USE_TIM6 */
326		-
327		-#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
328		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
329		-#if !defined(STM32_TIM7_HANDLER)
330		-#error "STM32_TIM7_HANDLER not defined"
331		-#endif
332		-/**
333		- * @brief TIM7 interrupt handler.
334		- *
335		- * @isr
336		- */
337		-OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
338		-
339		- OSAL_IRQ_PROLOGUE();
340		-
341		- gpt_lld_serve_interrupt(&GPTD7);
342		-
343		- OSAL_IRQ_EPILOGUE();
344		-}
345		-#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
346		-#endif /* STM32_GPT_USE_TIM7 */
347		-
348		-#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
349		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
350		-#if !defined(STM32_TIM8_UP_HANDLER)
351		-#error "STM32_TIM8_UP_HANDLER not defined"
352		-#endif
353		-/**
354		- * @brief TIM8 interrupt handler.
355		- *
356		- * @isr
357		- */
358		-OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
359		-
360		- OSAL_IRQ_PROLOGUE();
361		-
362		- gpt_lld_serve_interrupt(&GPTD8);
363		-
364		- OSAL_IRQ_EPILOGUE();
365		-}
366		-#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
367		-#endif /* STM32_GPT_USE_TIM8 */
368		-
369		-#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
370		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
371		-#error "TIM9 ISR not defined by platform"
372		-#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
373		-#endif /* STM32_GPT_USE_TIM9 */
374		-
375		-#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
376		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
377		-#error "TIM10 ISR not defined by platform"
378		-#endif /* !defined(STM32_TIM10_SUPPRESS_ISR) */
379		-#endif /* STM32_GPT_USE_TIM10 */
380		-
381		-#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
382		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
383		-#error "TIM11 ISR not defined by platform"
384		-#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
385		-#endif /* STM32_GPT_USE_TIM11 */
386		-
387		-#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
388		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
389		-#error "TIM12 ISR not defined by platform"
390		-#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
391		-#endif /* STM32_GPT_USE_TIM12 */
392		-
393		-#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
394		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
395		-#error "TIM13 ISR not defined by platform"
396		-#endif /* !defined(STM32_TIM13_SUPPRESS_ISR) */
397		-#endif /* STM32_GPT_USE_TIM13 */
398		-
399		-#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
400		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
401		-#error "TIM14 ISR not defined by platform"
402		-#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
403		-#endif /* STM32_GPT_USE_TIM14 */
404		-
405		-#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
406		-#if !defined(STM32_TIM15_SUPPRESS_ISR)
407		-#error "TIM15 ISR not defined by platform"
408		-#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */
409		-#endif /* STM32_GPT_USE_TIM15 */
410		-
411		-#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
412		-#if !defined(STM32_TIM16_SUPPRESS_ISR)
413		-#error "TIM16 ISR not defined by platform"
414		-#endif /* !defined(STM32_TIM16_SUPPRESS_ISR) */
415		-#endif /* STM32_GPT_USE_TIM16 */
416		-
417		-#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
418		-#if !defined(STM32_TIM17_SUPPRESS_ISR)
419		-#error "TIM17 ISR not defined by platform"
420		-#endif /* !defined(STM32_TIM17_SUPPRESS_ISR) */
421		-#endif /* STM32_GPT_USE_TIM17 */
422		-
423		-#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
424		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
425		-#if !defined(STM32_TIM21_HANDLER)
426		-#error "STM32_TIM21_HANDLER not defined"
427		-#endif
428		-/**
429		- * @brief TIM21 interrupt handler.
430		- *
431		- * @isr
432		- */
433		-OSAL_IRQ_HANDLER(STM32_TIM21_HANDLER) {
434		-
435		- OSAL_IRQ_PROLOGUE();
436		-
437		- gpt_lld_serve_interrupt(&GPTD21);
438		-
439		- OSAL_IRQ_EPILOGUE();
440		-}
441		-#endif /* !defined(STM32_TIM21_SUPPRESS_ISR) */
442		-#endif /* STM32_GPT_USE_TIM21 */
443		-
444		-#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
445		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
446		-#if !defined(STM32_TIM22_HANDLER)
447		-#error "STM32_TIM22_HANDLER not defined"
448		-#endif
449		-/**
450		- * @brief TIM22 interrupt handler.
451		- *
452		- * @isr
453		- */
454		-OSAL_IRQ_HANDLER(STM32_TIM22_HANDLER) {
455		-
456		- OSAL_IRQ_PROLOGUE();
457		-
458		- gpt_lld_serve_interrupt(&GPTD22);
459		-
460		- OSAL_IRQ_EPILOGUE();
461		-}
462		-#endif /* !defined(STM32_TIM22_SUPPRESS_ISR) */
463		-#endif /* STM32_GPT_USE_TIM22 */
464		-
465		-/===========================================================================/
466		-/* Driver exported functions. */
467		-/===========================================================================/
468		-
469		-/**
470		- * @brief Low level GPT driver initialization.
471		- *
472		- * @notapi
473		- */
474		-void gpt_lld_init(void) {
475		-
476		-#if STM32_GPT_USE_TIM1
477		- /* Driver initialization.*/
478		- GPTD1.tim = STM32_TIM1;
479		- gptObjectInit(&GPTD1);
480		-#endif
481		-
482		-#if STM32_GPT_USE_TIM2
483		- /* Driver initialization.*/
484		- GPTD2.tim = STM32_TIM2;
485		- gptObjectInit(&GPTD2);
486		-#endif
487		-
488		-#if STM32_GPT_USE_TIM3
489		- /* Driver initialization.*/
490		- GPTD3.tim = STM32_TIM3;
491		- gptObjectInit(&GPTD3);
492		-#endif
493		-
494		-#if STM32_GPT_USE_TIM4
495		- /* Driver initialization.*/
496		- GPTD4.tim = STM32_TIM4;
497		- gptObjectInit(&GPTD4);
498		-#endif
499		-
500		-#if STM32_GPT_USE_TIM5
501		- /* Driver initialization.*/
502		- GPTD5.tim = STM32_TIM5;
503		- gptObjectInit(&GPTD5);
504		-#endif
505		-
506		-#if STM32_GPT_USE_TIM6
507		- /* Driver initialization.*/
508		- GPTD6.tim = STM32_TIM6;
509		- gptObjectInit(&GPTD6);
510		-#endif
511		-
512		-#if STM32_GPT_USE_TIM7
513		- /* Driver initialization.*/
514		- GPTD7.tim = STM32_TIM7;
515		- gptObjectInit(&GPTD7);
516		-#endif
517		-
518		-#if STM32_GPT_USE_TIM8
519		- /* Driver initialization.*/
520		- GPTD8.tim = STM32_TIM8;
521		- gptObjectInit(&GPTD8);
522		-#endif
523		-
524		-#if STM32_GPT_USE_TIM9
525		- /* Driver initialization.*/
526		- GPTD9.tim = STM32_TIM9;
527		- gptObjectInit(&GPTD9);
528		-#endif
529		-
530		-#if STM32_GPT_USE_TIM10
531		- /* Driver initialization.*/
532		- GPTD10.tim = STM32_TIM10;
533		- gptObjectInit(&GPTD10);
534		-#endif
535		-
536		-#if STM32_GPT_USE_TIM11
537		- /* Driver initialization.*/
538		- GPTD11.tim = STM32_TIM11;
539		- gptObjectInit(&GPTD11);
540		-#endif
541		-
542		-#if STM32_GPT_USE_TIM12
543		- /* Driver initialization.*/
544		- GPTD12.tim = STM32_TIM12;
545		- gptObjectInit(&GPTD12);
546		-#endif
547		-
548		-#if STM32_GPT_USE_TIM13
549		- /* Driver initialization.*/
550		- GPTD13.tim = STM32_TIM13;
551		- gptObjectInit(&GPTD13);
552		-#endif
553		-
554		-#if STM32_GPT_USE_TIM14
555		- /* Driver initialization.*/
556		- GPTD14.tim = STM32_TIM14;
557		- gptObjectInit(&GPTD14);
558		-#endif
559		-
560		-#if STM32_GPT_USE_TIM15
561		- /* Driver initialization.*/
562		- GPTD15.tim = STM32_TIM15;
563		- gptObjectInit(&GPTD15);
564		-#endif
565		-
566		-#if STM32_GPT_USE_TIM16
567		- /* Driver initialization.*/
568		- GPTD16.tim = STM32_TIM16;
569		- gptObjectInit(&GPTD16);
570		-#endif
571		-
572		-#if STM32_GPT_USE_TIM17
573		- /* Driver initialization.*/
574		- GPTD17.tim = STM32_TIM17;
575		- gptObjectInit(&GPTD17);
576		-#endif
577		-
578		-#if STM32_GPT_USE_TIM21
579		- /* Driver initialization.*/
580		- GPTD21.tim = STM32_TIM21;
581		- gptObjectInit(&GPTD21);
582		-#endif
583		-
584		-#if STM32_GPT_USE_TIM22
585		- /* Driver initialization.*/
586		- GPTD22.tim = STM32_TIM22;
587		- gptObjectInit(&GPTD22);
588		-#endif
589		-}
590		-
591		-/**
592		- * @brief Configures and activates the GPT peripheral.
593		- *
594		- * @param[in] gptp pointer to the @p GPTDriver object
595		- *
596		- * @notapi
597		- */
598		-void gpt_lld_start(GPTDriver *gptp) {
599		- uint16_t psc;
600		-
601		- if (gptp->state == GPT_STOP) {
602		- /* Clock activation.*/
603		-#if STM32_GPT_USE_TIM1
604		- if (&GPTD1 == gptp) {
605		- rccEnableTIM1(true);
606		- rccResetTIM1();
607		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
608		- nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
609		-#endif
610		-#if defined(STM32_TIM1CLK)
611		- gptp->clock = STM32_TIM1CLK;
612		-#else
613		- gptp->clock = STM32_TIMCLK2;
614		-#endif
615		- }
616		-#endif
617		-
618		-#if STM32_GPT_USE_TIM2
619		- if (&GPTD2 == gptp) {
620		- rccEnableTIM2(true);
621		- rccResetTIM2();
622		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
623		- nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
624		-#endif
625		-#if defined(STM32_TIM2CLK)
626		- gptp->clock = STM32_TIM2CLK;
627		-#else
628		- gptp->clock = STM32_TIMCLK1;
629		-#endif
630		- }
631		-#endif
632		-
633		-#if STM32_GPT_USE_TIM3
634		- if (&GPTD3 == gptp) {
635		- rccEnableTIM3(true);
636		- rccResetTIM3();
637		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
638		- nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
639		-#endif
640		-#if defined(STM32_TIM3CLK)
641		- gptp->clock = STM32_TIM3CLK;
642		-#else
643		- gptp->clock = STM32_TIMCLK1;
644		-#endif
645		- }
646		-#endif
647		-
648		-#if STM32_GPT_USE_TIM4
649		- if (&GPTD4 == gptp) {
650		- rccEnableTIM4(true);
651		- rccResetTIM4();
652		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
653		- nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
654		-#endif
655		-#if defined(STM32_TIM4CLK)
656		- gptp->clock = STM32_TIM4CLK;
657		-#else
658		- gptp->clock = STM32_TIMCLK1;
659		-#endif
660		- }
661		-#endif
662		-
663		-#if STM32_GPT_USE_TIM5
664		- if (&GPTD5 == gptp) {
665		- rccEnableTIM5(true);
666		- rccResetTIM5();
667		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
668		- nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
669		-#endif
670		-#if defined(STM32_TIM5CLK)
671		- gptp->clock = STM32_TIM5CLK;
672		-#else
673		- gptp->clock = STM32_TIMCLK1;
674		-#endif
675		- }
676		-#endif
677		-
678		-#if STM32_GPT_USE_TIM6
679		- if (&GPTD6 == gptp) {
680		- rccEnableTIM6(true);
681		- rccResetTIM6();
682		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
683		- nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
684		-#endif
685		-#if defined(STM32_TIM6CLK)
686		- gptp->clock = STM32_TIM6CLK;
687		-#else
688		- gptp->clock = STM32_TIMCLK1;
689		-#endif
690		- }
691		-#endif
692		-
693		-#if STM32_GPT_USE_TIM7
694		- if (&GPTD7 == gptp) {
695		- rccEnableTIM7(true);
696		- rccResetTIM7();
697		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
698		- nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
699		-#endif
700		-#if defined(STM32_TIM7CLK)
701		- gptp->clock = STM32_TIM7CLK;
702		-#else
703		- gptp->clock = STM32_TIMCLK1;
704		-#endif
705		- }
706		-#endif
707		-
708		-#if STM32_GPT_USE_TIM8
709		- if (&GPTD8 == gptp) {
710		- rccEnableTIM8(true);
711		- rccResetTIM8();
712		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
713		- nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
714		-#endif
715		-#if defined(STM32_TIM8CLK)
716		- gptp->clock = STM32_TIM8CLK;
717		-#else
718		- gptp->clock = STM32_TIMCLK2;
719		-#endif
720		- }
721		-#endif
722		-
723		-#if STM32_GPT_USE_TIM9
724		- if (&GPTD9 == gptp) {
725		- rccEnableTIM9(true);
726		- rccResetTIM9();
727		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
728		- nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
729		-#endif
730		-#if defined(STM32_TIM9CLK)
731		- gptp->clock = STM32_TIM9CLK;
732		-#else
733		- gptp->clock = STM32_TIMCLK2;
734		-#endif
735		- }
736		-#endif
737		-
738		-#if STM32_GPT_USE_TIM10
739		- if (&GPTD10 == gptp) {
740		- rccEnableTIM10(true);
741		- rccResetTIM10();
742		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
743		- nvicEnableVector(STM32_TIM10_NUMBER, STM32_GPT_TIM10_IRQ_PRIORITY);
744		-#endif
745		-#if defined(STM32_TIM10CLK)
746		- gptp->clock = STM32_TIM10CLK;
747		-#else
748		- gptp->clock = STM32_TIMCLK2;
749		-#endif
750		- }
751		-#endif
752		-
753		-#if STM32_GPT_USE_TIM11
754		- if (&GPTD11 == gptp) {
755		- rccEnableTIM11(true);
756		- rccResetTIM11();
757		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
758		- nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
759		-#endif
760		-#if defined(STM32_TIM11CLK)
761		- gptp->clock = STM32_TIM11CLK;
762		-#else
763		- gptp->clock = STM32_TIMCLK2;
764		-#endif
765		- }
766		-#endif
767		-
768		-#if STM32_GPT_USE_TIM12
769		- if (&GPTD12 == gptp) {
770		- rccEnableTIM12(true);
771		- rccResetTIM12();
772		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
773		- nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
774		-#endif
775		-#if defined(STM32_TIM12CLK)
776		- gptp->clock = STM32_TIM12CLK;
777		-#else
778		- gptp->clock = STM32_TIMCLK1;
779		-#endif
780		- }
781		-#endif
782		-
783		-#if STM32_GPT_USE_TIM13
784		- if (&GPTD13 == gptp) {
785		- rccEnableTIM13(true);
786		- rccResetTIM13();
787		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
788		- nvicEnableVector(STM32_TIM13_NUMBER, STM32_GPT_TIM13_IRQ_PRIORITY);
789		-#endif
790		-#if defined(STM32_TIM13CLK)
791		- gptp->clock = STM32_TIM13CLK;
792		-#else
793		- gptp->clock = STM32_TIMCLK1;
794		-#endif
795		- }
796		-#endif
797		-
798		-#if STM32_GPT_USE_TIM14
799		- if (&GPTD14 == gptp) {
800		- rccEnableTIM14(true);
801		- rccResetTIM14();
802		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
803		- nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
804		-#endif
805		-#if defined(STM32_TIM14CLK)
806		- gptp->clock = STM32_TIM14CLK;
807		-#else
808		- gptp->clock = STM32_TIMCLK1;
809		-#endif
810		- }
811		-#endif
812		-
813		-#if STM32_GPT_USE_TIM15
814		- if (&GPTD15 == gptp) {
815		- rccEnableTIM15(true);
816		- rccResetTIM15();
817		-#if defined(STM32_TIM15CLK)
818		- gptp->clock = STM32_TIM15CLK;
819		-#else
820		- gptp->clock = STM32_TIMCLK2;
821		-#endif
822		- }
823		-#endif
824		-
825		-#if STM32_GPT_USE_TIM16
826		- if (&GPTD16 == gptp) {
827		- rccEnableTIM16(true);
828		- rccResetTIM16();
829		-#if defined(STM32_TIM16CLK)
830		- gptp->clock = STM32_TIM16CLK;
831		-#else
832		- gptp->clock = STM32_TIMCLK2;
833		-#endif
834		- }
835		-#endif
836		-
837		-#if STM32_GPT_USE_TIM17
838		- if (&GPTD17 == gptp) {
839		- rccEnableTIM17(true);
840		- rccResetTIM17();
841		-#if defined(STM32_TIM17CLK)
842		- gptp->clock = STM32_TIM17CLK;
843		-#else
844		- gptp->clock = STM32_TIMCLK2;
845		-#endif
846		- }
847		-#endif
848		-
849		-#if STM32_GPT_USE_TIM21
850		- if (&GPTD21 == gptp) {
851		- rccEnableTIM21(true);
852		- rccResetTIM21();
853		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
854		- nvicEnableVector(STM32_TIM21_NUMBER, STM32_GPT_TIM21_IRQ_PRIORITY);
855		-#endif
856		-#if defined(STM32_TIM21CLK)
857		- gptp->clock = STM32_TIM21CLK;
858		-#else
859		- gptp->clock = STM32_TIMCLK1;
860		-#endif
861		- }
862		-#endif
863		-
864		-#if STM32_GPT_USE_TIM22
865		- if (&GPTD22 == gptp) {
866		- rccEnableTIM22(true);
867		- rccResetTIM22();
868		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
869		- nvicEnableVector(STM32_TIM22_NUMBER, STM32_GPT_TIM22_IRQ_PRIORITY);
870		-#endif
871		-#if defined(STM32_TIM22CLK)
872		- gptp->clock = STM32_TIM22CLK;
873		-#else
874		- gptp->clock = STM32_TIMCLK1;
875		-#endif
876		- }
877		-#endif
878		- }
879		-
880		- /* Prescaler value calculation.*/
881		- psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
882		- osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
883		- "invalid frequency");
884		-
885		- /* Timer configuration.*/
886		- gptp->tim->CR1 = 0; /* Initially stopped. */
887		- gptp->tim->CR2 = gptp->config->cr2;
888		- gptp->tim->PSC = psc; /* Prescaler value. */
889		- gptp->tim->SR = 0; /* Clear pending IRQs. */
890		- gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
891		- ~STM32_TIM_DIER_IRQ_MASK;
892		-}
893		-
894		-/**
895		- * @brief Deactivates the GPT peripheral.
896		- *
897		- * @param[in] gptp pointer to the @p GPTDriver object
898		- *
899		- * @notapi
900		- */
901		-void gpt_lld_stop(GPTDriver *gptp) {
902		-
903		- if (gptp->state == GPT_READY) {
904		- gptp->tim->CR1 = 0; /* Timer disabled. */
905		- gptp->tim->DIER = 0; /* All IRQs disabled. */
906		- gptp->tim->SR = 0; /* Clear pending IRQs. */
907		-
908		-#if STM32_GPT_USE_TIM1
909		- if (&GPTD1 == gptp) {
910		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
911		- nvicDisableVector(STM32_TIM1_UP_NUMBER);
912		-#endif
913		- rccDisableTIM1();
914		- }
915		-#endif
916		-
917		-#if STM32_GPT_USE_TIM2
918		- if (&GPTD2 == gptp) {
919		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
920		- nvicDisableVector(STM32_TIM2_NUMBER);
921		-#endif
922		- rccDisableTIM2();
923		- }
924		-#endif
925		-
926		-#if STM32_GPT_USE_TIM3
927		- if (&GPTD3 == gptp) {
928		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
929		- nvicDisableVector(STM32_TIM3_NUMBER);
930		-#endif
931		- rccDisableTIM3();
932		- }
933		-#endif
934		-
935		-#if STM32_GPT_USE_TIM4
936		- if (&GPTD4 == gptp) {
937		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
938		- nvicDisableVector(STM32_TIM4_NUMBER);
939		-#endif
940		- rccDisableTIM4();
941		- }
942		-#endif
943		-
944		-#if STM32_GPT_USE_TIM5
945		- if (&GPTD5 == gptp) {
946		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
947		- nvicDisableVector(STM32_TIM5_NUMBER);
948		-#endif
949		- rccDisableTIM5();
950		- }
951		-#endif
952		-
953		-#if STM32_GPT_USE_TIM6
954		- if (&GPTD6 == gptp) {
955		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
956		- nvicDisableVector(STM32_TIM6_NUMBER);
957		-#endif
958		- rccDisableTIM6();
959		- }
960		-#endif
961		-
962		-#if STM32_GPT_USE_TIM7
963		- if (&GPTD7 == gptp) {
964		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
965		- nvicDisableVector(STM32_TIM7_NUMBER);
966		-#endif
967		- rccDisableTIM7();
968		- }
969		-#endif
970		-
971		-#if STM32_GPT_USE_TIM8
972		- if (&GPTD8 == gptp) {
973		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
974		- nvicDisableVector(STM32_TIM8_UP_NUMBER);
975		-#endif
976		- rccDisableTIM8();
977		- }
978		-#endif
979		-
980		-#if STM32_GPT_USE_TIM9
981		- if (&GPTD9 == gptp) {
982		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
983		- nvicDisableVector(STM32_TIM9_NUMBER);
984		-#endif
985		- rccDisableTIM9();
986		- }
987		-#endif
988		-
989		-#if STM32_GPT_USE_TIM10
990		- if (&GPTD10 == gptp) {
991		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
992		- nvicDisableVector(STM32_TIM10_NUMBER);
993		-#endif
994		- rccDisableTIM10();
995		- }
996		-#endif
997		-
998		-#if STM32_GPT_USE_TIM11
999		- if (&GPTD11 == gptp) {
1000		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
1001		- nvicDisableVector(STM32_TIM11_NUMBER);
1002		-#endif
1003		- rccDisableTIM11();
1004		- }
1005		-#endif
1006		-
1007		-#if STM32_GPT_USE_TIM12
1008		- if (&GPTD12 == gptp) {
1009		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
1010		- nvicDisableVector(STM32_TIM12_NUMBER);
1011		-#endif
1012		- rccDisableTIM12();
1013		- }
1014		-#endif
1015		-
1016		-#if STM32_GPT_USE_TIM13
1017		- if (&GPTD13 == gptp) {
1018		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
1019		- nvicDisableVector(STM32_TIM13_NUMBER);
1020		-#endif
1021		- rccDisableTIM13();
1022		- }
1023		-#endif
1024		-
1025		-#if STM32_GPT_USE_TIM14
1026		- if (&GPTD14 == gptp) {
1027		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
1028		- nvicDisableVector(STM32_TIM14_NUMBER);
1029		-#endif
1030		- rccDisableTIM14();
1031		- }
1032		-#endif
1033		-
1034		-#if STM32_GPT_USE_TIM15
1035		- if (&GPTD15 == gptp) {
1036		- rccDisableTIM15();
1037		- }
1038		-#endif
1039		-
1040		-#if STM32_GPT_USE_TIM16
1041		- if (&GPTD16 == gptp) {
1042		- rccDisableTIM16();
1043		- }
1044		-#endif
1045		-
1046		-#if STM32_GPT_USE_TIM17
1047		- if (&GPTD17 == gptp) {
1048		- rccDisableTIM17();
1049		- }
1050		-#endif
1051		-
1052		-#if STM32_GPT_USE_TIM21
1053		- if (&GPTD21 == gptp) {
1054		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
1055		- nvicDisableVector(STM32_TIM21_NUMBER);
1056		-#endif
1057		- rccDisableTIM21();
1058		- }
1059		-#endif
1060		-
1061		-#if STM32_GPT_USE_TIM22
1062		- if (&GPTD22 == gptp) {
1063		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
1064		- nvicDisableVector(STM32_TIM22_NUMBER);
1065		-#endif
1066		- rccDisableTIM22();
1067		- }
1068		-#endif
1069		- }
1070		-}
1071		-
1072		-/**
1073		- * @brief Starts the timer in continuous mode.
1074		- *
1075		- * @param[in] gptp pointer to the @p GPTDriver object
1076		- * @param[in] interval period in ticks
1077		- *
1078		- * @notapi
1079		- */
1080		-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
1081		-
1082		- gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1083		- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1084		- gptp->tim->CNT = 0; /* Reset counter. */
1085		-
1086		- /* NOTE: After generating the UG event it takes several clock cycles before
1087		- SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
1088		- before the clearing of SR, to give it some time.*/
1089		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1090		- if (NULL != gptp->config->callback)
1091		- gptp->tim->DIER \|= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
1092		- gptp->tim->CR1 = STM32_TIM_CR1_ARPE \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
1093		-}
1094		-
1095		-/**
1096		- * @brief Stops the timer.
1097		- *
1098		- * @param[in] gptp pointer to the @p GPTDriver object
1099		- *
1100		- * @notapi
1101		- */
1102		-void gpt_lld_stop_timer(GPTDriver *gptp) {
1103		-
1104		- gptp->tim->CR1 = 0; /* Initially stopped. */
1105		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1106		-
1107		- /* All interrupts disabled.*/
1108		- gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
1109		-}
1110		-
1111		-/**
1112		- * @brief Starts the timer in one shot mode and waits for completion.
1113		- * @details This function specifically polls the timer waiting for completion
1114		- * in order to not have extra delays caused by interrupt servicing,
1115		- * this function is only recommended for short delays.
1116		- *
1117		- * @param[in] gptp pointer to the @p GPTDriver object
1118		- * @param[in] interval time interval in ticks
1119		- *
1120		- * @notapi
1121		- */
1122		-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
1123		-
1124		- gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1125		- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1126		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1127		- gptp->tim->CR1 = STM32_TIM_CR1_OPM \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
1128		- while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
1129		- ;
1130		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1131		-}
1132		-
1133		-/**
1134		- * @brief Shared IRQ handler.
1135		- *
1136		- * @param[in] gptp pointer to a @p GPTDriver object
1137		- *
1138		- * @notapi
1139		- */
1140		-void gpt_lld_serve_interrupt(GPTDriver *gptp) {
1141		- uint32_t sr;
1142		-
1143		- sr = gptp->tim->SR;
1144		- sr &= gptp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
1145		- gptp->tim->SR = ~sr;
1146		- if ((sr & STM32_TIM_SR_UIF) != 0) {
1147		- _gpt_isr_invoke_cb(gptp);
1148		- }
1149		-}
1150		-
1151		-#endif /* HAL_USE_GPT */
1152		-
1153		-/** @} */
	1	+/*
	2	+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
	3	+
	4	+ Licensed under the Apache License, Version 2.0 (the "License");
	5	+ you may not use this file except in compliance with the License.
	6	+ You may obtain a copy of the License at
	7	+
	8	+ http://www.apache.org/licenses/LICENSE-2.0
	9	+
	10	+ Unless required by applicable law or agreed to in writing, software
	11	+ distributed under the License is distributed on an "AS IS" BASIS,
	12	+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	+ See the License for the specific language governing permissions and
	14	+ limitations under the License.
	15	+*/
	16	+
	17	+/**
	18	+ * @file TIMv1/hal_gpt_lld.c
	19	+ * @brief STM32 GPT subsystem low level driver source.
	20	+ *
	21	+ * @addtogroup GPT
	22	+ * @{
	23	+ */
	24	+
	25	+#include "hal.h"
	26	+
	27	+#if HAL_USE_GPT \|\| defined(__DOXYGEN__)
	28	+
	29	+/===========================================================================/
	30	+/* Driver local definitions. */
	31	+/===========================================================================/
	32	+
	33	+/===========================================================================/
	34	+/* Driver exported variables. */
	35	+/===========================================================================/
	36	+
	37	+/**
	38	+ * @brief GPTD1 driver identifier.
	39	+ * @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
	40	+ */
	41	+#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
	42	+GPTDriver GPTD1;
	43	+#endif
	44	+
	45	+/**
	46	+ * @brief GPTD2 driver identifier.
	47	+ * @note The driver GPTD2 allocates the timer TIM2 when enabled.
	48	+ */
	49	+#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
	50	+GPTDriver GPTD2;
	51	+#endif
	52	+
	53	+/**
	54	+ * @brief GPTD3 driver identifier.
	55	+ * @note The driver GPTD3 allocates the timer TIM3 when enabled.
	56	+ */
	57	+#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
	58	+GPTDriver GPTD3;
	59	+#endif
	60	+
	61	+/**
	62	+ * @brief GPTD4 driver identifier.
	63	+ * @note The driver GPTD4 allocates the timer TIM4 when enabled.
	64	+ */
	65	+#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
	66	+GPTDriver GPTD4;
	67	+#endif
	68	+
	69	+/**
	70	+ * @brief GPTD5 driver identifier.
	71	+ * @note The driver GPTD5 allocates the timer TIM5 when enabled.
	72	+ */
	73	+#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
	74	+GPTDriver GPTD5;
	75	+#endif
	76	+
	77	+/**
	78	+ * @brief GPTD6 driver identifier.
	79	+ * @note The driver GPTD6 allocates the timer TIM6 when enabled.
	80	+ */
	81	+#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
	82	+GPTDriver GPTD6;
	83	+#endif
	84	+
	85	+/**
	86	+ * @brief GPTD7 driver identifier.
	87	+ * @note The driver GPTD7 allocates the timer TIM7 when enabled.
	88	+ */
	89	+#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
	90	+GPTDriver GPTD7;
	91	+#endif
	92	+
	93	+/**
	94	+ * @brief GPTD8 driver identifier.
	95	+ * @note The driver GPTD8 allocates the timer TIM8 when enabled.
	96	+ */
	97	+#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
	98	+GPTDriver GPTD8;
	99	+#endif
	100	+
	101	+/**
	102	+ * @brief GPTD9 driver identifier.
	103	+ * @note The driver GPTD9 allocates the timer TIM9 when enabled.
	104	+ */
	105	+#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
	106	+GPTDriver GPTD9;
	107	+#endif
	108	+
	109	+/**
	110	+ * @brief GPTD10 driver identifier.
	111	+ * @note The driver GPTD10 allocates the timer TIM10 when enabled.
	112	+ */
	113	+#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
	114	+GPTDriver GPTD10;
	115	+#endif
	116	+
	117	+/**
	118	+ * @brief GPTD11 driver identifier.
	119	+ * @note The driver GPTD11 allocates the timer TIM11 when enabled.
	120	+ */
	121	+#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
	122	+GPTDriver GPTD11;
	123	+#endif
	124	+
	125	+/**
	126	+ * @brief GPTD12 driver identifier.
	127	+ * @note The driver GPTD12 allocates the timer TIM12 when enabled.
	128	+ */
	129	+#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
	130	+GPTDriver GPTD12;
	131	+#endif
	132	+
	133	+/**
	134	+ * @brief GPTD13 driver identifier.
	135	+ * @note The driver GPTD13 allocates the timer TIM13 when enabled.
	136	+ */
	137	+#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
	138	+GPTDriver GPTD13;
	139	+#endif
	140	+
	141	+/**
	142	+ * @brief GPTD14 driver identifier.
	143	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	144	+ */
	145	+#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
	146	+GPTDriver GPTD14;
	147	+#endif
	148	+
	149	+/**
	150	+ * @brief GPTD15 driver identifier.
	151	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	152	+ */
	153	+#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
	154	+GPTDriver GPTD15;
	155	+#endif
	156	+
	157	+/**
	158	+ * @brief GPTD16 driver identifier.
	159	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	160	+ */
	161	+#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
	162	+GPTDriver GPTD16;
	163	+#endif
	164	+
	165	+/**
	166	+ * @brief GPTD17 driver identifier.
	167	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	168	+ */
	169	+#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
	170	+GPTDriver GPTD17;
	171	+#endif
	172	+
	173	+/**
	174	+ * @brief GPTD21 driver identifier.
	175	+ * @note The driver GPTD21 allocates the timer TIM21 when enabled.
	176	+ */
	177	+#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
	178	+GPTDriver GPTD21;
	179	+#endif
	180	+
	181	+/**
	182	+ * @brief GPTD22 driver identifier.
	183	+ * @note The driver GPTD22 allocates the timer TIM22 when enabled.
	184	+ */
	185	+#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
	186	+GPTDriver GPTD22;
	187	+#endif
	188	+
	189	+/===========================================================================/
	190	+/* Driver local variables and types. */
	191	+/===========================================================================/
	192	+
	193	+/===========================================================================/
	194	+/* Driver local functions. */
	195	+/===========================================================================/
	196	+
	197	+/===========================================================================/
	198	+/* Driver interrupt handlers. */
	199	+/===========================================================================/
	200	+
	201	+#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
	202	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	203	+#if !defined(STM32_TIM1_UP_HANDLER)
	204	+#error "STM32_TIM1_UP_HANDLER not defined"
	205	+#endif
	206	+/**
	207	+ * @brief TIM1 interrupt handler.
	208	+ *
	209	+ * @isr
	210	+ */
	211	+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
	212	+
	213	+ OSAL_IRQ_PROLOGUE();
	214	+
	215	+ gpt_lld_serve_interrupt(&GPTD1);
	216	+
	217	+ OSAL_IRQ_EPILOGUE();
	218	+}
	219	+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
	220	+#endif /* STM32_GPT_USE_TIM1 */
	221	+
	222	+#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
	223	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	224	+#if !defined(STM32_TIM2_HANDLER)
	225	+#error "STM32_TIM2_HANDLER not defined"
	226	+#endif
	227	+/**
	228	+ * @brief TIM2 interrupt handler.
	229	+ *
	230	+ * @isr
	231	+ */
	232	+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
	233	+
	234	+ OSAL_IRQ_PROLOGUE();
	235	+
	236	+ gpt_lld_serve_interrupt(&GPTD2);
	237	+
	238	+ OSAL_IRQ_EPILOGUE();
	239	+}
	240	+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
	241	+#endif /* STM32_GPT_USE_TIM2 */
	242	+
	243	+#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
	244	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	245	+#if !defined(STM32_TIM3_HANDLER)
	246	+#error "STM32_TIM3_HANDLER not defined"
	247	+#endif
	248	+/**
	249	+ * @brief TIM3 interrupt handler.
	250	+ *
	251	+ * @isr
	252	+ */
	253	+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
	254	+
	255	+ OSAL_IRQ_PROLOGUE();
	256	+
	257	+ gpt_lld_serve_interrupt(&GPTD3);
	258	+
	259	+ OSAL_IRQ_EPILOGUE();
	260	+}
	261	+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
	262	+#endif /* STM32_GPT_USE_TIM3 */
	263	+
	264	+#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
	265	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	266	+#if !defined(STM32_TIM4_HANDLER)
	267	+#error "STM32_TIM4_HANDLER not defined"
	268	+#endif
	269	+/**
	270	+ * @brief TIM4 interrupt handler.
	271	+ *
	272	+ * @isr
	273	+ */
	274	+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
	275	+
	276	+ OSAL_IRQ_PROLOGUE();
	277	+
	278	+ gpt_lld_serve_interrupt(&GPTD4);
	279	+
	280	+ OSAL_IRQ_EPILOGUE();
	281	+}
	282	+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
	283	+#endif /* STM32_GPT_USE_TIM4 */
	284	+
	285	+#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
	286	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	287	+#if !defined(STM32_TIM5_HANDLER)
	288	+#error "STM32_TIM5_HANDLER not defined"
	289	+#endif
	290	+/**
	291	+ * @brief TIM5 interrupt handler.
	292	+ *
	293	+ * @isr
	294	+ */
	295	+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
	296	+
	297	+ OSAL_IRQ_PROLOGUE();
	298	+
	299	+ gpt_lld_serve_interrupt(&GPTD5);
	300	+
	301	+ OSAL_IRQ_EPILOGUE();
	302	+}
	303	+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
	304	+#endif /* STM32_GPT_USE_TIM5 */
	305	+
	306	+#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
	307	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	308	+#if !defined(STM32_TIM6_HANDLER)
	309	+#error "STM32_TIM6_HANDLER not defined"
	310	+#endif
	311	+/**
	312	+ * @brief TIM6 interrupt handler.
	313	+ *
	314	+ * @isr
	315	+ */
	316	+OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
	317	+
	318	+ OSAL_IRQ_PROLOGUE();
	319	+
	320	+ gpt_lld_serve_interrupt(&GPTD6);
	321	+
	322	+ OSAL_IRQ_EPILOGUE();
	323	+}
	324	+#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
	325	+#endif /* STM32_GPT_USE_TIM6 */
	326	+
	327	+#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
	328	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	329	+#if !defined(STM32_TIM7_HANDLER)
	330	+#error "STM32_TIM7_HANDLER not defined"
	331	+#endif
	332	+/**
	333	+ * @brief TIM7 interrupt handler.
	334	+ *
	335	+ * @isr
	336	+ */
	337	+OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
	338	+
	339	+ OSAL_IRQ_PROLOGUE();
	340	+
	341	+ gpt_lld_serve_interrupt(&GPTD7);
	342	+
	343	+ OSAL_IRQ_EPILOGUE();
	344	+}
	345	+#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
	346	+#endif /* STM32_GPT_USE_TIM7 */
	347	+
	348	+#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
	349	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	350	+#if !defined(STM32_TIM8_UP_HANDLER)
	351	+#error "STM32_TIM8_UP_HANDLER not defined"
	352	+#endif
	353	+/**
	354	+ * @brief TIM8 interrupt handler.
	355	+ *
	356	+ * @isr
	357	+ */
	358	+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
	359	+
	360	+ OSAL_IRQ_PROLOGUE();
	361	+
	362	+ gpt_lld_serve_interrupt(&GPTD8);
	363	+
	364	+ OSAL_IRQ_EPILOGUE();
	365	+}
	366	+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
	367	+#endif /* STM32_GPT_USE_TIM8 */
	368	+
	369	+#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
	370	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	371	+#error "TIM9 ISR not defined by platform"
	372	+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
	373	+#endif /* STM32_GPT_USE_TIM9 */
	374	+
	375	+#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
	376	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	377	+#error "TIM10 ISR not defined by platform"
	378	+#endif /* !defined(STM32_TIM10_SUPPRESS_ISR) */
	379	+#endif /* STM32_GPT_USE_TIM10 */
	380	+
	381	+#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
	382	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	383	+#error "TIM11 ISR not defined by platform"
	384	+#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
	385	+#endif /* STM32_GPT_USE_TIM11 */
	386	+
	387	+#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
	388	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	389	+#error "TIM12 ISR not defined by platform"
	390	+#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
	391	+#endif /* STM32_GPT_USE_TIM12 */
	392	+
	393	+#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
	394	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	395	+#error "TIM13 ISR not defined by platform"
	396	+#endif /* !defined(STM32_TIM13_SUPPRESS_ISR) */
	397	+#endif /* STM32_GPT_USE_TIM13 */
	398	+
	399	+#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
	400	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	401	+#error "TIM14 ISR not defined by platform"
	402	+#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
	403	+#endif /* STM32_GPT_USE_TIM14 */
	404	+
	405	+#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
	406	+#if !defined(STM32_TIM15_SUPPRESS_ISR)
	407	+#error "TIM15 ISR not defined by platform"
	408	+#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */
	409	+#endif /* STM32_GPT_USE_TIM15 */
	410	+
	411	+#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
	412	+#if !defined(STM32_TIM16_SUPPRESS_ISR)
	413	+#error "TIM16 ISR not defined by platform"
	414	+#endif /* !defined(STM32_TIM16_SUPPRESS_ISR) */
	415	+#endif /* STM32_GPT_USE_TIM16 */
	416	+
	417	+#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
	418	+#if !defined(STM32_TIM17_SUPPRESS_ISR)
	419	+#error "TIM17 ISR not defined by platform"
	420	+#endif /* !defined(STM32_TIM17_SUPPRESS_ISR) */
	421	+#endif /* STM32_GPT_USE_TIM17 */
	422	+
	423	+#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
	424	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	425	+#if !defined(STM32_TIM21_HANDLER)
	426	+#error "STM32_TIM21_HANDLER not defined"
	427	+#endif
	428	+/**
	429	+ * @brief TIM21 interrupt handler.
	430	+ *
	431	+ * @isr
	432	+ */
	433	+OSAL_IRQ_HANDLER(STM32_TIM21_HANDLER) {
	434	+
	435	+ OSAL_IRQ_PROLOGUE();
	436	+
	437	+ gpt_lld_serve_interrupt(&GPTD21);
	438	+
	439	+ OSAL_IRQ_EPILOGUE();
	440	+}
	441	+#endif /* !defined(STM32_TIM21_SUPPRESS_ISR) */
	442	+#endif /* STM32_GPT_USE_TIM21 */
	443	+
	444	+#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
	445	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	446	+#if !defined(STM32_TIM22_HANDLER)
	447	+#error "STM32_TIM22_HANDLER not defined"
	448	+#endif
	449	+/**
	450	+ * @brief TIM22 interrupt handler.
	451	+ *
	452	+ * @isr
	453	+ */
	454	+OSAL_IRQ_HANDLER(STM32_TIM22_HANDLER) {
	455	+
	456	+ OSAL_IRQ_PROLOGUE();
	457	+
	458	+ gpt_lld_serve_interrupt(&GPTD22);
	459	+
	460	+ OSAL_IRQ_EPILOGUE();
	461	+}
	462	+#endif /* !defined(STM32_TIM22_SUPPRESS_ISR) */
	463	+#endif /* STM32_GPT_USE_TIM22 */
	464	+
	465	+/===========================================================================/
	466	+/* Driver exported functions. */
	467	+/===========================================================================/
	468	+
	469	+/**
	470	+ * @brief Low level GPT driver initialization.
	471	+ *
	472	+ * @notapi
	473	+ */
	474	+void gpt_lld_init(void) {
	475	+
	476	+#if STM32_GPT_USE_TIM1
	477	+ /* Driver initialization.*/
	478	+ GPTD1.tim = STM32_TIM1;
	479	+ gptObjectInit(&GPTD1);
	480	+#endif
	481	+
	482	+#if STM32_GPT_USE_TIM2
	483	+ /* Driver initialization.*/
	484	+ GPTD2.tim = STM32_TIM2;
	485	+ gptObjectInit(&GPTD2);
	486	+#endif
	487	+
	488	+#if STM32_GPT_USE_TIM3
	489	+ /* Driver initialization.*/
	490	+ GPTD3.tim = STM32_TIM3;
	491	+ gptObjectInit(&GPTD3);
	492	+#endif
	493	+
	494	+#if STM32_GPT_USE_TIM4
	495	+ /* Driver initialization.*/
	496	+ GPTD4.tim = STM32_TIM4;
	497	+ gptObjectInit(&GPTD4);
	498	+#endif
	499	+
	500	+#if STM32_GPT_USE_TIM5
	501	+ /* Driver initialization.*/
	502	+ GPTD5.tim = STM32_TIM5;
	503	+ gptObjectInit(&GPTD5);
	504	+#endif
	505	+
	506	+#if STM32_GPT_USE_TIM6
	507	+ /* Driver initialization.*/
	508	+ GPTD6.tim = STM32_TIM6;
	509	+ gptObjectInit(&GPTD6);
	510	+#endif
	511	+
	512	+#if STM32_GPT_USE_TIM7
	513	+ /* Driver initialization.*/
	514	+ GPTD7.tim = STM32_TIM7;
	515	+ gptObjectInit(&GPTD7);
	516	+#endif
	517	+
	518	+#if STM32_GPT_USE_TIM8
	519	+ /* Driver initialization.*/
	520	+ GPTD8.tim = STM32_TIM8;
	521	+ gptObjectInit(&GPTD8);
	522	+#endif
	523	+
	524	+#if STM32_GPT_USE_TIM9
	525	+ /* Driver initialization.*/
	526	+ GPTD9.tim = STM32_TIM9;
	527	+ gptObjectInit(&GPTD9);
	528	+#endif
	529	+
	530	+#if STM32_GPT_USE_TIM10
	531	+ /* Driver initialization.*/
	532	+ GPTD10.tim = STM32_TIM10;
	533	+ gptObjectInit(&GPTD10);
	534	+#endif
	535	+
	536	+#if STM32_GPT_USE_TIM11
	537	+ /* Driver initialization.*/
	538	+ GPTD11.tim = STM32_TIM11;
	539	+ gptObjectInit(&GPTD11);
	540	+#endif
	541	+
	542	+#if STM32_GPT_USE_TIM12
	543	+ /* Driver initialization.*/
	544	+ GPTD12.tim = STM32_TIM12;
	545	+ gptObjectInit(&GPTD12);
	546	+#endif
	547	+
	548	+#if STM32_GPT_USE_TIM13
	549	+ /* Driver initialization.*/
	550	+ GPTD13.tim = STM32_TIM13;
	551	+ gptObjectInit(&GPTD13);
	552	+#endif
	553	+
	554	+#if STM32_GPT_USE_TIM14
	555	+ /* Driver initialization.*/
	556	+ GPTD14.tim = STM32_TIM14;
	557	+ gptObjectInit(&GPTD14);
	558	+#endif
	559	+
	560	+#if STM32_GPT_USE_TIM15
	561	+ /* Driver initialization.*/
	562	+ GPTD15.tim = STM32_TIM15;
	563	+ gptObjectInit(&GPTD15);
	564	+#endif
	565	+
	566	+#if STM32_GPT_USE_TIM16
	567	+ /* Driver initialization.*/
	568	+ GPTD16.tim = STM32_TIM16;
	569	+ gptObjectInit(&GPTD16);
	570	+#endif
	571	+
	572	+#if STM32_GPT_USE_TIM17
	573	+ /* Driver initialization.*/
	574	+ GPTD17.tim = STM32_TIM17;
	575	+ gptObjectInit(&GPTD17);
	576	+#endif
	577	+
	578	+#if STM32_GPT_USE_TIM21
	579	+ /* Driver initialization.*/
	580	+ GPTD21.tim = STM32_TIM21;
	581	+ gptObjectInit(&GPTD21);
	582	+#endif
	583	+
	584	+#if STM32_GPT_USE_TIM22
	585	+ /* Driver initialization.*/
	586	+ GPTD22.tim = STM32_TIM22;
	587	+ gptObjectInit(&GPTD22);
	588	+#endif
	589	+}
	590	+
	591	+/**
	592	+ * @brief Configures and activates the GPT peripheral.
	593	+ *
	594	+ * @param[in] gptp pointer to the @p GPTDriver object
	595	+ *
	596	+ * @notapi
	597	+ */
	598	+void gpt_lld_start(GPTDriver *gptp) {
	599	+ uint16_t psc;
	600	+
	601	+ if (gptp->state == GPT_STOP) {
	602	+ /* Clock activation.*/
	603	+#if STM32_GPT_USE_TIM1
	604	+ if (&GPTD1 == gptp) {
	605	+ rccEnableTIM1(true);
	606	+ rccResetTIM1();
	607	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	608	+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
	609	+#endif
	610	+#if defined(STM32_TIM1CLK)
	611	+ gptp->clock = STM32_TIM1CLK;
	612	+#else
	613	+ gptp->clock = STM32_TIMCLK2;
	614	+#endif
	615	+ }
	616	+#endif
	617	+
	618	+#if STM32_GPT_USE_TIM2
	619	+ if (&GPTD2 == gptp) {
	620	+ rccEnableTIM2(true);
	621	+ rccResetTIM2();
	622	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	623	+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
	624	+#endif
	625	+#if defined(STM32_TIM2CLK)
	626	+ gptp->clock = STM32_TIM2CLK;
	627	+#else
	628	+ gptp->clock = STM32_TIMCLK1;
	629	+#endif
	630	+ }
	631	+#endif
	632	+
	633	+#if STM32_GPT_USE_TIM3
	634	+ if (&GPTD3 == gptp) {
	635	+ rccEnableTIM3(true);
	636	+ rccResetTIM3();
	637	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	638	+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
	639	+#endif
	640	+#if defined(STM32_TIM3CLK)
	641	+ gptp->clock = STM32_TIM3CLK;
	642	+#else
	643	+ gptp->clock = STM32_TIMCLK1;
	644	+#endif
	645	+ }
	646	+#endif
	647	+
	648	+#if STM32_GPT_USE_TIM4
	649	+ if (&GPTD4 == gptp) {
	650	+ rccEnableTIM4(true);
	651	+ rccResetTIM4();
	652	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	653	+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
	654	+#endif
	655	+#if defined(STM32_TIM4CLK)
	656	+ gptp->clock = STM32_TIM4CLK;
	657	+#else
	658	+ gptp->clock = STM32_TIMCLK1;
	659	+#endif
	660	+ }
	661	+#endif
	662	+
	663	+#if STM32_GPT_USE_TIM5
	664	+ if (&GPTD5 == gptp) {
	665	+ rccEnableTIM5(true);
	666	+ rccResetTIM5();
	667	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	668	+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
	669	+#endif
	670	+#if defined(STM32_TIM5CLK)
	671	+ gptp->clock = STM32_TIM5CLK;
	672	+#else
	673	+ gptp->clock = STM32_TIMCLK1;
	674	+#endif
	675	+ }
	676	+#endif
	677	+
	678	+#if STM32_GPT_USE_TIM6
	679	+ if (&GPTD6 == gptp) {
	680	+ rccEnableTIM6(true);
	681	+ rccResetTIM6();
	682	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	683	+ nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
	684	+#endif
	685	+#if defined(STM32_TIM6CLK)
	686	+ gptp->clock = STM32_TIM6CLK;
	687	+#else
	688	+ gptp->clock = STM32_TIMCLK1;
	689	+#endif
	690	+ }
	691	+#endif
	692	+
	693	+#if STM32_GPT_USE_TIM7
	694	+ if (&GPTD7 == gptp) {
	695	+ rccEnableTIM7(true);
	696	+ rccResetTIM7();
	697	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	698	+ nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
	699	+#endif
	700	+#if defined(STM32_TIM7CLK)
	701	+ gptp->clock = STM32_TIM7CLK;
	702	+#else
	703	+ gptp->clock = STM32_TIMCLK1;
	704	+#endif
	705	+ }
	706	+#endif
	707	+
	708	+#if STM32_GPT_USE_TIM8
	709	+ if (&GPTD8 == gptp) {
	710	+ rccEnableTIM8(true);
	711	+ rccResetTIM8();
	712	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	713	+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
	714	+#endif
	715	+#if defined(STM32_TIM8CLK)
	716	+ gptp->clock = STM32_TIM8CLK;
	717	+#else
	718	+ gptp->clock = STM32_TIMCLK2;
	719	+#endif
	720	+ }
	721	+#endif
	722	+
	723	+#if STM32_GPT_USE_TIM9
	724	+ if (&GPTD9 == gptp) {
	725	+ rccEnableTIM9(true);
	726	+ rccResetTIM9();
	727	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	728	+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
	729	+#endif
	730	+#if defined(STM32_TIM9CLK)
	731	+ gptp->clock = STM32_TIM9CLK;
	732	+#else
	733	+ gptp->clock = STM32_TIMCLK2;
	734	+#endif
	735	+ }
	736	+#endif
	737	+
	738	+#if STM32_GPT_USE_TIM10
	739	+ if (&GPTD10 == gptp) {
	740	+ rccEnableTIM10(true);
	741	+ rccResetTIM10();
	742	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	743	+ nvicEnableVector(STM32_TIM10_NUMBER, STM32_GPT_TIM10_IRQ_PRIORITY);
	744	+#endif
	745	+#if defined(STM32_TIM10CLK)
	746	+ gptp->clock = STM32_TIM10CLK;
	747	+#else
	748	+ gptp->clock = STM32_TIMCLK2;
	749	+#endif
	750	+ }
	751	+#endif
	752	+
	753	+#if STM32_GPT_USE_TIM11
	754	+ if (&GPTD11 == gptp) {
	755	+ rccEnableTIM11(true);
	756	+ rccResetTIM11();
	757	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	758	+ nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
	759	+#endif
	760	+#if defined(STM32_TIM11CLK)
	761	+ gptp->clock = STM32_TIM11CLK;
	762	+#else
	763	+ gptp->clock = STM32_TIMCLK2;
	764	+#endif
	765	+ }
	766	+#endif
	767	+
	768	+#if STM32_GPT_USE_TIM12
	769	+ if (&GPTD12 == gptp) {
	770	+ rccEnableTIM12(true);
	771	+ rccResetTIM12();
	772	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	773	+ nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
	774	+#endif
	775	+#if defined(STM32_TIM12CLK)
	776	+ gptp->clock = STM32_TIM12CLK;
	777	+#else
	778	+ gptp->clock = STM32_TIMCLK1;
	779	+#endif
	780	+ }
	781	+#endif
	782	+
	783	+#if STM32_GPT_USE_TIM13
	784	+ if (&GPTD13 == gptp) {
	785	+ rccEnableTIM13(true);
	786	+ rccResetTIM13();
	787	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	788	+ nvicEnableVector(STM32_TIM13_NUMBER, STM32_GPT_TIM13_IRQ_PRIORITY);
	789	+#endif
	790	+#if defined(STM32_TIM13CLK)
	791	+ gptp->clock = STM32_TIM13CLK;
	792	+#else
	793	+ gptp->clock = STM32_TIMCLK1;
	794	+#endif
	795	+ }
	796	+#endif
	797	+
	798	+#if STM32_GPT_USE_TIM14
	799	+ if (&GPTD14 == gptp) {
	800	+ rccEnableTIM14(true);
	801	+ rccResetTIM14();
	802	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	803	+ nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
	804	+#endif
	805	+#if defined(STM32_TIM14CLK)
	806	+ gptp->clock = STM32_TIM14CLK;
	807	+#else
	808	+ gptp->clock = STM32_TIMCLK1;
	809	+#endif
	810	+ }
	811	+#endif
	812	+
	813	+#if STM32_GPT_USE_TIM15
	814	+ if (&GPTD15 == gptp) {
	815	+ rccEnableTIM15(true);
	816	+ rccResetTIM15();
	817	+#if defined(STM32_TIM15CLK)
	818	+ gptp->clock = STM32_TIM15CLK;
	819	+#else
	820	+ gptp->clock = STM32_TIMCLK2;
	821	+#endif
	822	+ }
	823	+#endif
	824	+
	825	+#if STM32_GPT_USE_TIM16
	826	+ if (&GPTD16 == gptp) {
	827	+ rccEnableTIM16(true);
	828	+ rccResetTIM16();
	829	+#if defined(STM32_TIM16CLK)
	830	+ gptp->clock = STM32_TIM16CLK;
	831	+#else
	832	+ gptp->clock = STM32_TIMCLK2;
	833	+#endif
	834	+ }
	835	+#endif
	836	+
	837	+#if STM32_GPT_USE_TIM17
	838	+ if (&GPTD17 == gptp) {
	839	+ rccEnableTIM17(true);
	840	+ rccResetTIM17();
	841	+#if defined(STM32_TIM17CLK)
	842	+ gptp->clock = STM32_TIM17CLK;
	843	+#else
	844	+ gptp->clock = STM32_TIMCLK2;
	845	+#endif
	846	+ }
	847	+#endif
	848	+
	849	+#if STM32_GPT_USE_TIM21
	850	+ if (&GPTD21 == gptp) {
	851	+ rccEnableTIM21(true);
	852	+ rccResetTIM21();
	853	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	854	+ nvicEnableVector(STM32_TIM21_NUMBER, STM32_GPT_TIM21_IRQ_PRIORITY);
	855	+#endif
	856	+#if defined(STM32_TIM21CLK)
	857	+ gptp->clock = STM32_TIM21CLK;
	858	+#else
	859	+ gptp->clock = STM32_TIMCLK1;
	860	+#endif
	861	+ }
	862	+#endif
	863	+
	864	+#if STM32_GPT_USE_TIM22
	865	+ if (&GPTD22 == gptp) {
	866	+ rccEnableTIM22(true);
	867	+ rccResetTIM22();
	868	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	869	+ nvicEnableVector(STM32_TIM22_NUMBER, STM32_GPT_TIM22_IRQ_PRIORITY);
	870	+#endif
	871	+#if defined(STM32_TIM22CLK)
	872	+ gptp->clock = STM32_TIM22CLK;
	873	+#else
	874	+ gptp->clock = STM32_TIMCLK1;
	875	+#endif
	876	+ }
	877	+#endif
	878	+ }
	879	+
	880	+ /* Prescaler value calculation.*/
	881	+ psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
	882	+ osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
	883	+ "invalid frequency");
	884	+
	885	+ /* Timer configuration.*/
	886	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
	887	+ gptp->tim->CR2 = gptp->config->cr2;
	888	+ gptp->tim->PSC = psc; /* Prescaler value. */
	889	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	890	+ gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
	891	+ ~STM32_TIM_DIER_IRQ_MASK;
	892	+}
	893	+
	894	+/**
	895	+ * @brief Deactivates the GPT peripheral.
	896	+ *
	897	+ * @param[in] gptp pointer to the @p GPTDriver object
	898	+ *
	899	+ * @notapi
	900	+ */
	901	+void gpt_lld_stop(GPTDriver *gptp) {
	902	+
	903	+ if (gptp->state == GPT_READY) {
	904	+ gptp->tim->CR1 = 0U; /* Timer disabled. */
	905	+ gptp->tim->DIER = 0U; /* All IRQs disabled. */
	906	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	907	+
	908	+#if STM32_GPT_USE_TIM1
	909	+ if (&GPTD1 == gptp) {
	910	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	911	+ nvicDisableVector(STM32_TIM1_UP_NUMBER);
	912	+#endif
	913	+ rccDisableTIM1();
	914	+ }
	915	+#endif
	916	+
	917	+#if STM32_GPT_USE_TIM2
	918	+ if (&GPTD2 == gptp) {
	919	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	920	+ nvicDisableVector(STM32_TIM2_NUMBER);
	921	+#endif
	922	+ rccDisableTIM2();
	923	+ }
	924	+#endif
	925	+
	926	+#if STM32_GPT_USE_TIM3
	927	+ if (&GPTD3 == gptp) {
	928	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	929	+ nvicDisableVector(STM32_TIM3_NUMBER);
	930	+#endif
	931	+ rccDisableTIM3();
	932	+ }
	933	+#endif
	934	+
	935	+#if STM32_GPT_USE_TIM4
	936	+ if (&GPTD4 == gptp) {
	937	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	938	+ nvicDisableVector(STM32_TIM4_NUMBER);
	939	+#endif
	940	+ rccDisableTIM4();
	941	+ }
	942	+#endif
	943	+
	944	+#if STM32_GPT_USE_TIM5
	945	+ if (&GPTD5 == gptp) {
	946	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	947	+ nvicDisableVector(STM32_TIM5_NUMBER);
	948	+#endif
	949	+ rccDisableTIM5();
	950	+ }
	951	+#endif
	952	+
	953	+#if STM32_GPT_USE_TIM6
	954	+ if (&GPTD6 == gptp) {
	955	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	956	+ nvicDisableVector(STM32_TIM6_NUMBER);
	957	+#endif
	958	+ rccDisableTIM6();
	959	+ }
	960	+#endif
	961	+
	962	+#if STM32_GPT_USE_TIM7
	963	+ if (&GPTD7 == gptp) {
	964	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	965	+ nvicDisableVector(STM32_TIM7_NUMBER);
	966	+#endif
	967	+ rccDisableTIM7();
	968	+ }
	969	+#endif
	970	+
	971	+#if STM32_GPT_USE_TIM8
	972	+ if (&GPTD8 == gptp) {
	973	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	974	+ nvicDisableVector(STM32_TIM8_UP_NUMBER);
	975	+#endif
	976	+ rccDisableTIM8();
	977	+ }
	978	+#endif
	979	+
	980	+#if STM32_GPT_USE_TIM9
	981	+ if (&GPTD9 == gptp) {
	982	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	983	+ nvicDisableVector(STM32_TIM9_NUMBER);
	984	+#endif
	985	+ rccDisableTIM9();
	986	+ }
	987	+#endif
	988	+
	989	+#if STM32_GPT_USE_TIM10
	990	+ if (&GPTD10 == gptp) {
	991	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	992	+ nvicDisableVector(STM32_TIM10_NUMBER);
	993	+#endif
	994	+ rccDisableTIM10();
	995	+ }
	996	+#endif
	997	+
	998	+#if STM32_GPT_USE_TIM11
	999	+ if (&GPTD11 == gptp) {
	1000	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	1001	+ nvicDisableVector(STM32_TIM11_NUMBER);
	1002	+#endif
	1003	+ rccDisableTIM11();
	1004	+ }
	1005	+#endif
	1006	+
	1007	+#if STM32_GPT_USE_TIM12
	1008	+ if (&GPTD12 == gptp) {
	1009	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	1010	+ nvicDisableVector(STM32_TIM12_NUMBER);
	1011	+#endif
	1012	+ rccDisableTIM12();
	1013	+ }
	1014	+#endif
	1015	+
	1016	+#if STM32_GPT_USE_TIM13
	1017	+ if (&GPTD13 == gptp) {
	1018	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	1019	+ nvicDisableVector(STM32_TIM13_NUMBER);
	1020	+#endif
	1021	+ rccDisableTIM13();
	1022	+ }
	1023	+#endif
	1024	+
	1025	+#if STM32_GPT_USE_TIM14
	1026	+ if (&GPTD14 == gptp) {
	1027	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	1028	+ nvicDisableVector(STM32_TIM14_NUMBER);
	1029	+#endif
	1030	+ rccDisableTIM14();
	1031	+ }
	1032	+#endif
	1033	+
	1034	+#if STM32_GPT_USE_TIM15
	1035	+ if (&GPTD15 == gptp) {
	1036	+ rccDisableTIM15();
	1037	+ }
	1038	+#endif
	1039	+
	1040	+#if STM32_GPT_USE_TIM16
	1041	+ if (&GPTD16 == gptp) {
	1042	+ rccDisableTIM16();
	1043	+ }
	1044	+#endif
	1045	+
	1046	+#if STM32_GPT_USE_TIM17
	1047	+ if (&GPTD17 == gptp) {
	1048	+ rccDisableTIM17();
	1049	+ }
	1050	+#endif
	1051	+
	1052	+#if STM32_GPT_USE_TIM21
	1053	+ if (&GPTD21 == gptp) {
	1054	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	1055	+ nvicDisableVector(STM32_TIM21_NUMBER);
	1056	+#endif
	1057	+ rccDisableTIM21();
	1058	+ }
	1059	+#endif
	1060	+
	1061	+#if STM32_GPT_USE_TIM22
	1062	+ if (&GPTD22 == gptp) {
	1063	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	1064	+ nvicDisableVector(STM32_TIM22_NUMBER);
	1065	+#endif
	1066	+ rccDisableTIM22();
	1067	+ }
	1068	+#endif
	1069	+ }
	1070	+}
	1071	+
	1072	+/**
	1073	+ * @brief Starts the timer in continuous mode.
	1074	+ *
	1075	+ * @param[in] gptp pointer to the @p GPTDriver object
	1076	+ * @param[in] interval period in ticks
	1077	+ *
	1078	+ * @notapi
	1079	+ */
	1080	+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
	1081	+
	1082	+ gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
	1083	+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
	1084	+ gptp->tim->CNT = 0U; /* Reset counter. */
	1085	+
	1086	+ /* NOTE: After generating the UG event it takes several clock cycles before
	1087	+ SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
	1088	+ before the clearing of SR, to give it some time.*/
	1089	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1090	+ if (NULL != gptp->config->callback)
	1091	+ gptp->tim->DIER \|= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
	1092	+ gptp->tim->CR1 = STM32_TIM_CR1_ARPE \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
	1093	+}
	1094	+
	1095	+/**
	1096	+ * @brief Stops the timer.
	1097	+ *
	1098	+ * @param[in] gptp pointer to the @p GPTDriver object
	1099	+ *
	1100	+ * @notapi
	1101	+ */
	1102	+void gpt_lld_stop_timer(GPTDriver *gptp) {
	1103	+
	1104	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
	1105	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1106	+
	1107	+ /* All interrupts disabled.*/
	1108	+ gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
	1109	+}
	1110	+
	1111	+/**
	1112	+ * @brief Starts the timer in one shot mode and waits for completion.
	1113	+ * @details This function specifically polls the timer waiting for completion
	1114	+ * in order to not have extra delays caused by interrupt servicing,
	1115	+ * this function is only recommended for short delays.
	1116	+ *
	1117	+ * @param[in] gptp pointer to the @p GPTDriver object
	1118	+ * @param[in] interval time interval in ticks
	1119	+ *
	1120	+ * @notapi
	1121	+ */
	1122	+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
	1123	+
	1124	+ gptp->tim->CR1 = STM32_TIM_CR1_UDIS; /* Immediate update. */
	1125	+ gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
	1126	+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
	1127	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1128	+ gptp->tim->CR1 = STM32_TIM_CR1_OPM \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
	1129	+ while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
	1130	+ ;
	1131	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1132	+}
	1133	+
	1134	+/**
	1135	+ * @brief Shared IRQ handler.
	1136	+ *
	1137	+ * @param[in] gptp pointer to a @p GPTDriver object
	1138	+ *
	1139	+ * @notapi
	1140	+ */
	1141	+void gpt_lld_serve_interrupt(GPTDriver *gptp) {
	1142	+ uint32_t sr;
	1143	+
	1144	+ sr = gptp->tim->SR;
	1145	+ sr &= gptp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
	1146	+ gptp->tim->SR = ~sr;
	1147	+ if ((sr & STM32_TIM_SR_UIF) != 0) {
	1148	+ _gpt_isr_invoke_cb(gptp);
	1149	+ }
	1150	+}
	1151	+
	1152	+#endif /* HAL_USE_GPT */
	1153	+
	1154	+/** @} */

--- branches/stable_20.3.x/readme.txt (revision 15841)

+++ branches/stable_20.3.x/readme.txt (revision 15842)

		@@ -74,6 +74,7 @@
74	74	*****************************************************************************
75	75
76	76	* 20.3.5 *
	77	+- FIX: Fixed problem in STM32 gpt_lld_polled_delay() implementation (bug #1241).
77	78	- FIX: Fixed invalid delay loop in STM32G0/WL ADCv5 driver (bug #1240).
78	79	- FIX: Fixed missing clock enables for some GPIOS on some STM32L4s (bug #1237).
79	80	- FIX: Fixed old bugs in serial driver header (bug #1236).

--- branches/stable_21.11.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15841)

+++ branches/stable_21.11.x/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15842)

		@@ -1,1153 +1,1154 @@
1		-/*
2		- ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3		-
4		- Licensed under the Apache License, Version 2.0 (the "License");
5		- you may not use this file except in compliance with the License.
6		- You may obtain a copy of the License at
7		-
8		- http://www.apache.org/licenses/LICENSE-2.0
9		-
10		- Unless required by applicable law or agreed to in writing, software
11		- distributed under the License is distributed on an "AS IS" BASIS,
12		- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13		- See the License for the specific language governing permissions and
14		- limitations under the License.
15		-*/
16		-
17		-/**
18		- * @file TIMv1/hal_gpt_lld.c
19		- * @brief STM32 GPT subsystem low level driver source.
20		- *
21		- * @addtogroup GPT
22		- * @{
23		- */
24		-
25		-#include "hal.h"
26		-
27		-#if HAL_USE_GPT \|\| defined(__DOXYGEN__)
28		-
29		-/===========================================================================/
30		-/* Driver local definitions. */
31		-/===========================================================================/
32		-
33		-/===========================================================================/
34		-/* Driver exported variables. */
35		-/===========================================================================/
36		-
37		-/**
38		- * @brief GPTD1 driver identifier.
39		- * @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
40		- */
41		-#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
42		-GPTDriver GPTD1;
43		-#endif
44		-
45		-/**
46		- * @brief GPTD2 driver identifier.
47		- * @note The driver GPTD2 allocates the timer TIM2 when enabled.
48		- */
49		-#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
50		-GPTDriver GPTD2;
51		-#endif
52		-
53		-/**
54		- * @brief GPTD3 driver identifier.
55		- * @note The driver GPTD3 allocates the timer TIM3 when enabled.
56		- */
57		-#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
58		-GPTDriver GPTD3;
59		-#endif
60		-
61		-/**
62		- * @brief GPTD4 driver identifier.
63		- * @note The driver GPTD4 allocates the timer TIM4 when enabled.
64		- */
65		-#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
66		-GPTDriver GPTD4;
67		-#endif
68		-
69		-/**
70		- * @brief GPTD5 driver identifier.
71		- * @note The driver GPTD5 allocates the timer TIM5 when enabled.
72		- */
73		-#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
74		-GPTDriver GPTD5;
75		-#endif
76		-
77		-/**
78		- * @brief GPTD6 driver identifier.
79		- * @note The driver GPTD6 allocates the timer TIM6 when enabled.
80		- */
81		-#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
82		-GPTDriver GPTD6;
83		-#endif
84		-
85		-/**
86		- * @brief GPTD7 driver identifier.
87		- * @note The driver GPTD7 allocates the timer TIM7 when enabled.
88		- */
89		-#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
90		-GPTDriver GPTD7;
91		-#endif
92		-
93		-/**
94		- * @brief GPTD8 driver identifier.
95		- * @note The driver GPTD8 allocates the timer TIM8 when enabled.
96		- */
97		-#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
98		-GPTDriver GPTD8;
99		-#endif
100		-
101		-/**
102		- * @brief GPTD9 driver identifier.
103		- * @note The driver GPTD9 allocates the timer TIM9 when enabled.
104		- */
105		-#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
106		-GPTDriver GPTD9;
107		-#endif
108		-
109		-/**
110		- * @brief GPTD10 driver identifier.
111		- * @note The driver GPTD10 allocates the timer TIM10 when enabled.
112		- */
113		-#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
114		-GPTDriver GPTD10;
115		-#endif
116		-
117		-/**
118		- * @brief GPTD11 driver identifier.
119		- * @note The driver GPTD11 allocates the timer TIM11 when enabled.
120		- */
121		-#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
122		-GPTDriver GPTD11;
123		-#endif
124		-
125		-/**
126		- * @brief GPTD12 driver identifier.
127		- * @note The driver GPTD12 allocates the timer TIM12 when enabled.
128		- */
129		-#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
130		-GPTDriver GPTD12;
131		-#endif
132		-
133		-/**
134		- * @brief GPTD13 driver identifier.
135		- * @note The driver GPTD13 allocates the timer TIM13 when enabled.
136		- */
137		-#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
138		-GPTDriver GPTD13;
139		-#endif
140		-
141		-/**
142		- * @brief GPTD14 driver identifier.
143		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
144		- */
145		-#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
146		-GPTDriver GPTD14;
147		-#endif
148		-
149		-/**
150		- * @brief GPTD15 driver identifier.
151		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
152		- */
153		-#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
154		-GPTDriver GPTD15;
155		-#endif
156		-
157		-/**
158		- * @brief GPTD16 driver identifier.
159		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
160		- */
161		-#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
162		-GPTDriver GPTD16;
163		-#endif
164		-
165		-/**
166		- * @brief GPTD17 driver identifier.
167		- * @note The driver GPTD14 allocates the timer TIM14 when enabled.
168		- */
169		-#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
170		-GPTDriver GPTD17;
171		-#endif
172		-
173		-/**
174		- * @brief GPTD21 driver identifier.
175		- * @note The driver GPTD21 allocates the timer TIM21 when enabled.
176		- */
177		-#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
178		-GPTDriver GPTD21;
179		-#endif
180		-
181		-/**
182		- * @brief GPTD22 driver identifier.
183		- * @note The driver GPTD22 allocates the timer TIM22 when enabled.
184		- */
185		-#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
186		-GPTDriver GPTD22;
187		-#endif
188		-
189		-/===========================================================================/
190		-/* Driver local variables and types. */
191		-/===========================================================================/
192		-
193		-/===========================================================================/
194		-/* Driver local functions. */
195		-/===========================================================================/
196		-
197		-/===========================================================================/
198		-/* Driver interrupt handlers. */
199		-/===========================================================================/
200		-
201		-#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
202		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
203		-#if !defined(STM32_TIM1_UP_HANDLER)
204		-#error "STM32_TIM1_UP_HANDLER not defined"
205		-#endif
206		-/**
207		- * @brief TIM1 interrupt handler.
208		- *
209		- * @isr
210		- */
211		-OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
212		-
213		- OSAL_IRQ_PROLOGUE();
214		-
215		- gpt_lld_serve_interrupt(&GPTD1);
216		-
217		- OSAL_IRQ_EPILOGUE();
218		-}
219		-#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
220		-#endif /* STM32_GPT_USE_TIM1 */
221		-
222		-#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
223		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
224		-#if !defined(STM32_TIM2_HANDLER)
225		-#error "STM32_TIM2_HANDLER not defined"
226		-#endif
227		-/**
228		- * @brief TIM2 interrupt handler.
229		- *
230		- * @isr
231		- */
232		-OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
233		-
234		- OSAL_IRQ_PROLOGUE();
235		-
236		- gpt_lld_serve_interrupt(&GPTD2);
237		-
238		- OSAL_IRQ_EPILOGUE();
239		-}
240		-#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
241		-#endif /* STM32_GPT_USE_TIM2 */
242		-
243		-#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
244		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
245		-#if !defined(STM32_TIM3_HANDLER)
246		-#error "STM32_TIM3_HANDLER not defined"
247		-#endif
248		-/**
249		- * @brief TIM3 interrupt handler.
250		- *
251		- * @isr
252		- */
253		-OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
254		-
255		- OSAL_IRQ_PROLOGUE();
256		-
257		- gpt_lld_serve_interrupt(&GPTD3);
258		-
259		- OSAL_IRQ_EPILOGUE();
260		-}
261		-#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
262		-#endif /* STM32_GPT_USE_TIM3 */
263		-
264		-#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
265		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
266		-#if !defined(STM32_TIM4_HANDLER)
267		-#error "STM32_TIM4_HANDLER not defined"
268		-#endif
269		-/**
270		- * @brief TIM4 interrupt handler.
271		- *
272		- * @isr
273		- */
274		-OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
275		-
276		- OSAL_IRQ_PROLOGUE();
277		-
278		- gpt_lld_serve_interrupt(&GPTD4);
279		-
280		- OSAL_IRQ_EPILOGUE();
281		-}
282		-#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
283		-#endif /* STM32_GPT_USE_TIM4 */
284		-
285		-#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
286		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
287		-#if !defined(STM32_TIM5_HANDLER)
288		-#error "STM32_TIM5_HANDLER not defined"
289		-#endif
290		-/**
291		- * @brief TIM5 interrupt handler.
292		- *
293		- * @isr
294		- */
295		-OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
296		-
297		- OSAL_IRQ_PROLOGUE();
298		-
299		- gpt_lld_serve_interrupt(&GPTD5);
300		-
301		- OSAL_IRQ_EPILOGUE();
302		-}
303		-#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
304		-#endif /* STM32_GPT_USE_TIM5 */
305		-
306		-#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
307		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
308		-#if !defined(STM32_TIM6_HANDLER)
309		-#error "STM32_TIM6_HANDLER not defined"
310		-#endif
311		-/**
312		- * @brief TIM6 interrupt handler.
313		- *
314		- * @isr
315		- */
316		-OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
317		-
318		- OSAL_IRQ_PROLOGUE();
319		-
320		- gpt_lld_serve_interrupt(&GPTD6);
321		-
322		- OSAL_IRQ_EPILOGUE();
323		-}
324		-#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
325		-#endif /* STM32_GPT_USE_TIM6 */
326		-
327		-#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
328		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
329		-#if !defined(STM32_TIM7_HANDLER)
330		-#error "STM32_TIM7_HANDLER not defined"
331		-#endif
332		-/**
333		- * @brief TIM7 interrupt handler.
334		- *
335		- * @isr
336		- */
337		-OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
338		-
339		- OSAL_IRQ_PROLOGUE();
340		-
341		- gpt_lld_serve_interrupt(&GPTD7);
342		-
343		- OSAL_IRQ_EPILOGUE();
344		-}
345		-#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
346		-#endif /* STM32_GPT_USE_TIM7 */
347		-
348		-#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
349		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
350		-#if !defined(STM32_TIM8_UP_HANDLER)
351		-#error "STM32_TIM8_UP_HANDLER not defined"
352		-#endif
353		-/**
354		- * @brief TIM8 interrupt handler.
355		- *
356		- * @isr
357		- */
358		-OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
359		-
360		- OSAL_IRQ_PROLOGUE();
361		-
362		- gpt_lld_serve_interrupt(&GPTD8);
363		-
364		- OSAL_IRQ_EPILOGUE();
365		-}
366		-#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
367		-#endif /* STM32_GPT_USE_TIM8 */
368		-
369		-#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
370		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
371		-#error "TIM9 ISR not defined by platform"
372		-#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
373		-#endif /* STM32_GPT_USE_TIM9 */
374		-
375		-#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
376		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
377		-#error "TIM10 ISR not defined by platform"
378		-#endif /* !defined(STM32_TIM10_SUPPRESS_ISR) */
379		-#endif /* STM32_GPT_USE_TIM10 */
380		-
381		-#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
382		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
383		-#error "TIM11 ISR not defined by platform"
384		-#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
385		-#endif /* STM32_GPT_USE_TIM11 */
386		-
387		-#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
388		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
389		-#error "TIM12 ISR not defined by platform"
390		-#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
391		-#endif /* STM32_GPT_USE_TIM12 */
392		-
393		-#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
394		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
395		-#error "TIM13 ISR not defined by platform"
396		-#endif /* !defined(STM32_TIM13_SUPPRESS_ISR) */
397		-#endif /* STM32_GPT_USE_TIM13 */
398		-
399		-#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
400		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
401		-#error "TIM14 ISR not defined by platform"
402		-#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
403		-#endif /* STM32_GPT_USE_TIM14 */
404		-
405		-#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
406		-#if !defined(STM32_TIM15_SUPPRESS_ISR)
407		-#error "TIM15 ISR not defined by platform"
408		-#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */
409		-#endif /* STM32_GPT_USE_TIM15 */
410		-
411		-#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
412		-#if !defined(STM32_TIM16_SUPPRESS_ISR)
413		-#error "TIM16 ISR not defined by platform"
414		-#endif /* !defined(STM32_TIM16_SUPPRESS_ISR) */
415		-#endif /* STM32_GPT_USE_TIM16 */
416		-
417		-#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
418		-#if !defined(STM32_TIM17_SUPPRESS_ISR)
419		-#error "TIM17 ISR not defined by platform"
420		-#endif /* !defined(STM32_TIM17_SUPPRESS_ISR) */
421		-#endif /* STM32_GPT_USE_TIM17 */
422		-
423		-#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
424		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
425		-#if !defined(STM32_TIM21_HANDLER)
426		-#error "STM32_TIM21_HANDLER not defined"
427		-#endif
428		-/**
429		- * @brief TIM21 interrupt handler.
430		- *
431		- * @isr
432		- */
433		-OSAL_IRQ_HANDLER(STM32_TIM21_HANDLER) {
434		-
435		- OSAL_IRQ_PROLOGUE();
436		-
437		- gpt_lld_serve_interrupt(&GPTD21);
438		-
439		- OSAL_IRQ_EPILOGUE();
440		-}
441		-#endif /* !defined(STM32_TIM21_SUPPRESS_ISR) */
442		-#endif /* STM32_GPT_USE_TIM21 */
443		-
444		-#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
445		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
446		-#if !defined(STM32_TIM22_HANDLER)
447		-#error "STM32_TIM22_HANDLER not defined"
448		-#endif
449		-/**
450		- * @brief TIM22 interrupt handler.
451		- *
452		- * @isr
453		- */
454		-OSAL_IRQ_HANDLER(STM32_TIM22_HANDLER) {
455		-
456		- OSAL_IRQ_PROLOGUE();
457		-
458		- gpt_lld_serve_interrupt(&GPTD22);
459		-
460		- OSAL_IRQ_EPILOGUE();
461		-}
462		-#endif /* !defined(STM32_TIM22_SUPPRESS_ISR) */
463		-#endif /* STM32_GPT_USE_TIM22 */
464		-
465		-/===========================================================================/
466		-/* Driver exported functions. */
467		-/===========================================================================/
468		-
469		-/**
470		- * @brief Low level GPT driver initialization.
471		- *
472		- * @notapi
473		- */
474		-void gpt_lld_init(void) {
475		-
476		-#if STM32_GPT_USE_TIM1
477		- /* Driver initialization.*/
478		- GPTD1.tim = STM32_TIM1;
479		- gptObjectInit(&GPTD1);
480		-#endif
481		-
482		-#if STM32_GPT_USE_TIM2
483		- /* Driver initialization.*/
484		- GPTD2.tim = STM32_TIM2;
485		- gptObjectInit(&GPTD2);
486		-#endif
487		-
488		-#if STM32_GPT_USE_TIM3
489		- /* Driver initialization.*/
490		- GPTD3.tim = STM32_TIM3;
491		- gptObjectInit(&GPTD3);
492		-#endif
493		-
494		-#if STM32_GPT_USE_TIM4
495		- /* Driver initialization.*/
496		- GPTD4.tim = STM32_TIM4;
497		- gptObjectInit(&GPTD4);
498		-#endif
499		-
500		-#if STM32_GPT_USE_TIM5
501		- /* Driver initialization.*/
502		- GPTD5.tim = STM32_TIM5;
503		- gptObjectInit(&GPTD5);
504		-#endif
505		-
506		-#if STM32_GPT_USE_TIM6
507		- /* Driver initialization.*/
508		- GPTD6.tim = STM32_TIM6;
509		- gptObjectInit(&GPTD6);
510		-#endif
511		-
512		-#if STM32_GPT_USE_TIM7
513		- /* Driver initialization.*/
514		- GPTD7.tim = STM32_TIM7;
515		- gptObjectInit(&GPTD7);
516		-#endif
517		-
518		-#if STM32_GPT_USE_TIM8
519		- /* Driver initialization.*/
520		- GPTD8.tim = STM32_TIM8;
521		- gptObjectInit(&GPTD8);
522		-#endif
523		-
524		-#if STM32_GPT_USE_TIM9
525		- /* Driver initialization.*/
526		- GPTD9.tim = STM32_TIM9;
527		- gptObjectInit(&GPTD9);
528		-#endif
529		-
530		-#if STM32_GPT_USE_TIM10
531		- /* Driver initialization.*/
532		- GPTD10.tim = STM32_TIM10;
533		- gptObjectInit(&GPTD10);
534		-#endif
535		-
536		-#if STM32_GPT_USE_TIM11
537		- /* Driver initialization.*/
538		- GPTD11.tim = STM32_TIM11;
539		- gptObjectInit(&GPTD11);
540		-#endif
541		-
542		-#if STM32_GPT_USE_TIM12
543		- /* Driver initialization.*/
544		- GPTD12.tim = STM32_TIM12;
545		- gptObjectInit(&GPTD12);
546		-#endif
547		-
548		-#if STM32_GPT_USE_TIM13
549		- /* Driver initialization.*/
550		- GPTD13.tim = STM32_TIM13;
551		- gptObjectInit(&GPTD13);
552		-#endif
553		-
554		-#if STM32_GPT_USE_TIM14
555		- /* Driver initialization.*/
556		- GPTD14.tim = STM32_TIM14;
557		- gptObjectInit(&GPTD14);
558		-#endif
559		-
560		-#if STM32_GPT_USE_TIM15
561		- /* Driver initialization.*/
562		- GPTD15.tim = STM32_TIM15;
563		- gptObjectInit(&GPTD15);
564		-#endif
565		-
566		-#if STM32_GPT_USE_TIM16
567		- /* Driver initialization.*/
568		- GPTD16.tim = STM32_TIM16;
569		- gptObjectInit(&GPTD16);
570		-#endif
571		-
572		-#if STM32_GPT_USE_TIM17
573		- /* Driver initialization.*/
574		- GPTD17.tim = STM32_TIM17;
575		- gptObjectInit(&GPTD17);
576		-#endif
577		-
578		-#if STM32_GPT_USE_TIM21
579		- /* Driver initialization.*/
580		- GPTD21.tim = STM32_TIM21;
581		- gptObjectInit(&GPTD21);
582		-#endif
583		-
584		-#if STM32_GPT_USE_TIM22
585		- /* Driver initialization.*/
586		- GPTD22.tim = STM32_TIM22;
587		- gptObjectInit(&GPTD22);
588		-#endif
589		-}
590		-
591		-/**
592		- * @brief Configures and activates the GPT peripheral.
593		- *
594		- * @param[in] gptp pointer to the @p GPTDriver object
595		- *
596		- * @notapi
597		- */
598		-void gpt_lld_start(GPTDriver *gptp) {
599		- uint16_t psc;
600		-
601		- if (gptp->state == GPT_STOP) {
602		- /* Clock activation.*/
603		-#if STM32_GPT_USE_TIM1
604		- if (&GPTD1 == gptp) {
605		- rccEnableTIM1(true);
606		- rccResetTIM1();
607		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
608		- nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
609		-#endif
610		-#if defined(STM32_TIM1CLK)
611		- gptp->clock = STM32_TIM1CLK;
612		-#else
613		- gptp->clock = STM32_TIMCLK2;
614		-#endif
615		- }
616		-#endif
617		-
618		-#if STM32_GPT_USE_TIM2
619		- if (&GPTD2 == gptp) {
620		- rccEnableTIM2(true);
621		- rccResetTIM2();
622		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
623		- nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
624		-#endif
625		-#if defined(STM32_TIM2CLK)
626		- gptp->clock = STM32_TIM2CLK;
627		-#else
628		- gptp->clock = STM32_TIMCLK1;
629		-#endif
630		- }
631		-#endif
632		-
633		-#if STM32_GPT_USE_TIM3
634		- if (&GPTD3 == gptp) {
635		- rccEnableTIM3(true);
636		- rccResetTIM3();
637		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
638		- nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
639		-#endif
640		-#if defined(STM32_TIM3CLK)
641		- gptp->clock = STM32_TIM3CLK;
642		-#else
643		- gptp->clock = STM32_TIMCLK1;
644		-#endif
645		- }
646		-#endif
647		-
648		-#if STM32_GPT_USE_TIM4
649		- if (&GPTD4 == gptp) {
650		- rccEnableTIM4(true);
651		- rccResetTIM4();
652		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
653		- nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
654		-#endif
655		-#if defined(STM32_TIM4CLK)
656		- gptp->clock = STM32_TIM4CLK;
657		-#else
658		- gptp->clock = STM32_TIMCLK1;
659		-#endif
660		- }
661		-#endif
662		-
663		-#if STM32_GPT_USE_TIM5
664		- if (&GPTD5 == gptp) {
665		- rccEnableTIM5(true);
666		- rccResetTIM5();
667		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
668		- nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
669		-#endif
670		-#if defined(STM32_TIM5CLK)
671		- gptp->clock = STM32_TIM5CLK;
672		-#else
673		- gptp->clock = STM32_TIMCLK1;
674		-#endif
675		- }
676		-#endif
677		-
678		-#if STM32_GPT_USE_TIM6
679		- if (&GPTD6 == gptp) {
680		- rccEnableTIM6(true);
681		- rccResetTIM6();
682		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
683		- nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
684		-#endif
685		-#if defined(STM32_TIM6CLK)
686		- gptp->clock = STM32_TIM6CLK;
687		-#else
688		- gptp->clock = STM32_TIMCLK1;
689		-#endif
690		- }
691		-#endif
692		-
693		-#if STM32_GPT_USE_TIM7
694		- if (&GPTD7 == gptp) {
695		- rccEnableTIM7(true);
696		- rccResetTIM7();
697		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
698		- nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
699		-#endif
700		-#if defined(STM32_TIM7CLK)
701		- gptp->clock = STM32_TIM7CLK;
702		-#else
703		- gptp->clock = STM32_TIMCLK1;
704		-#endif
705		- }
706		-#endif
707		-
708		-#if STM32_GPT_USE_TIM8
709		- if (&GPTD8 == gptp) {
710		- rccEnableTIM8(true);
711		- rccResetTIM8();
712		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
713		- nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
714		-#endif
715		-#if defined(STM32_TIM8CLK)
716		- gptp->clock = STM32_TIM8CLK;
717		-#else
718		- gptp->clock = STM32_TIMCLK2;
719		-#endif
720		- }
721		-#endif
722		-
723		-#if STM32_GPT_USE_TIM9
724		- if (&GPTD9 == gptp) {
725		- rccEnableTIM9(true);
726		- rccResetTIM9();
727		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
728		- nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
729		-#endif
730		-#if defined(STM32_TIM9CLK)
731		- gptp->clock = STM32_TIM9CLK;
732		-#else
733		- gptp->clock = STM32_TIMCLK2;
734		-#endif
735		- }
736		-#endif
737		-
738		-#if STM32_GPT_USE_TIM10
739		- if (&GPTD10 == gptp) {
740		- rccEnableTIM10(true);
741		- rccResetTIM10();
742		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
743		- nvicEnableVector(STM32_TIM10_NUMBER, STM32_GPT_TIM10_IRQ_PRIORITY);
744		-#endif
745		-#if defined(STM32_TIM10CLK)
746		- gptp->clock = STM32_TIM10CLK;
747		-#else
748		- gptp->clock = STM32_TIMCLK2;
749		-#endif
750		- }
751		-#endif
752		-
753		-#if STM32_GPT_USE_TIM11
754		- if (&GPTD11 == gptp) {
755		- rccEnableTIM11(true);
756		- rccResetTIM11();
757		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
758		- nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
759		-#endif
760		-#if defined(STM32_TIM11CLK)
761		- gptp->clock = STM32_TIM11CLK;
762		-#else
763		- gptp->clock = STM32_TIMCLK2;
764		-#endif
765		- }
766		-#endif
767		-
768		-#if STM32_GPT_USE_TIM12
769		- if (&GPTD12 == gptp) {
770		- rccEnableTIM12(true);
771		- rccResetTIM12();
772		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
773		- nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
774		-#endif
775		-#if defined(STM32_TIM12CLK)
776		- gptp->clock = STM32_TIM12CLK;
777		-#else
778		- gptp->clock = STM32_TIMCLK1;
779		-#endif
780		- }
781		-#endif
782		-
783		-#if STM32_GPT_USE_TIM13
784		- if (&GPTD13 == gptp) {
785		- rccEnableTIM13(true);
786		- rccResetTIM13();
787		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
788		- nvicEnableVector(STM32_TIM13_NUMBER, STM32_GPT_TIM13_IRQ_PRIORITY);
789		-#endif
790		-#if defined(STM32_TIM13CLK)
791		- gptp->clock = STM32_TIM13CLK;
792		-#else
793		- gptp->clock = STM32_TIMCLK1;
794		-#endif
795		- }
796		-#endif
797		-
798		-#if STM32_GPT_USE_TIM14
799		- if (&GPTD14 == gptp) {
800		- rccEnableTIM14(true);
801		- rccResetTIM14();
802		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
803		- nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
804		-#endif
805		-#if defined(STM32_TIM14CLK)
806		- gptp->clock = STM32_TIM14CLK;
807		-#else
808		- gptp->clock = STM32_TIMCLK1;
809		-#endif
810		- }
811		-#endif
812		-
813		-#if STM32_GPT_USE_TIM15
814		- if (&GPTD15 == gptp) {
815		- rccEnableTIM15(true);
816		- rccResetTIM15();
817		-#if defined(STM32_TIM15CLK)
818		- gptp->clock = STM32_TIM15CLK;
819		-#else
820		- gptp->clock = STM32_TIMCLK2;
821		-#endif
822		- }
823		-#endif
824		-
825		-#if STM32_GPT_USE_TIM16
826		- if (&GPTD16 == gptp) {
827		- rccEnableTIM16(true);
828		- rccResetTIM16();
829		-#if defined(STM32_TIM16CLK)
830		- gptp->clock = STM32_TIM16CLK;
831		-#else
832		- gptp->clock = STM32_TIMCLK2;
833		-#endif
834		- }
835		-#endif
836		-
837		-#if STM32_GPT_USE_TIM17
838		- if (&GPTD17 == gptp) {
839		- rccEnableTIM17(true);
840		- rccResetTIM17();
841		-#if defined(STM32_TIM17CLK)
842		- gptp->clock = STM32_TIM17CLK;
843		-#else
844		- gptp->clock = STM32_TIMCLK2;
845		-#endif
846		- }
847		-#endif
848		-
849		-#if STM32_GPT_USE_TIM21
850		- if (&GPTD21 == gptp) {
851		- rccEnableTIM21(true);
852		- rccResetTIM21();
853		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
854		- nvicEnableVector(STM32_TIM21_NUMBER, STM32_GPT_TIM21_IRQ_PRIORITY);
855		-#endif
856		-#if defined(STM32_TIM21CLK)
857		- gptp->clock = STM32_TIM21CLK;
858		-#else
859		- gptp->clock = STM32_TIMCLK1;
860		-#endif
861		- }
862		-#endif
863		-
864		-#if STM32_GPT_USE_TIM22
865		- if (&GPTD22 == gptp) {
866		- rccEnableTIM22(true);
867		- rccResetTIM22();
868		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
869		- nvicEnableVector(STM32_TIM22_NUMBER, STM32_GPT_TIM22_IRQ_PRIORITY);
870		-#endif
871		-#if defined(STM32_TIM22CLK)
872		- gptp->clock = STM32_TIM22CLK;
873		-#else
874		- gptp->clock = STM32_TIMCLK1;
875		-#endif
876		- }
877		-#endif
878		- }
879		-
880		- /* Prescaler value calculation.*/
881		- psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
882		- osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
883		- "invalid frequency");
884		-
885		- /* Timer configuration.*/
886		- gptp->tim->CR1 = 0; /* Initially stopped. */
887		- gptp->tim->CR2 = gptp->config->cr2;
888		- gptp->tim->PSC = psc; /* Prescaler value. */
889		- gptp->tim->SR = 0; /* Clear pending IRQs. */
890		- gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
891		- ~STM32_TIM_DIER_IRQ_MASK;
892		-}
893		-
894		-/**
895		- * @brief Deactivates the GPT peripheral.
896		- *
897		- * @param[in] gptp pointer to the @p GPTDriver object
898		- *
899		- * @notapi
900		- */
901		-void gpt_lld_stop(GPTDriver *gptp) {
902		-
903		- if (gptp->state == GPT_READY) {
904		- gptp->tim->CR1 = 0; /* Timer disabled. */
905		- gptp->tim->DIER = 0; /* All IRQs disabled. */
906		- gptp->tim->SR = 0; /* Clear pending IRQs. */
907		-
908		-#if STM32_GPT_USE_TIM1
909		- if (&GPTD1 == gptp) {
910		-#if !defined(STM32_TIM1_SUPPRESS_ISR)
911		- nvicDisableVector(STM32_TIM1_UP_NUMBER);
912		-#endif
913		- rccDisableTIM1();
914		- }
915		-#endif
916		-
917		-#if STM32_GPT_USE_TIM2
918		- if (&GPTD2 == gptp) {
919		-#if !defined(STM32_TIM2_SUPPRESS_ISR)
920		- nvicDisableVector(STM32_TIM2_NUMBER);
921		-#endif
922		- rccDisableTIM2();
923		- }
924		-#endif
925		-
926		-#if STM32_GPT_USE_TIM3
927		- if (&GPTD3 == gptp) {
928		-#if !defined(STM32_TIM3_SUPPRESS_ISR)
929		- nvicDisableVector(STM32_TIM3_NUMBER);
930		-#endif
931		- rccDisableTIM3();
932		- }
933		-#endif
934		-
935		-#if STM32_GPT_USE_TIM4
936		- if (&GPTD4 == gptp) {
937		-#if !defined(STM32_TIM4_SUPPRESS_ISR)
938		- nvicDisableVector(STM32_TIM4_NUMBER);
939		-#endif
940		- rccDisableTIM4();
941		- }
942		-#endif
943		-
944		-#if STM32_GPT_USE_TIM5
945		- if (&GPTD5 == gptp) {
946		-#if !defined(STM32_TIM5_SUPPRESS_ISR)
947		- nvicDisableVector(STM32_TIM5_NUMBER);
948		-#endif
949		- rccDisableTIM5();
950		- }
951		-#endif
952		-
953		-#if STM32_GPT_USE_TIM6
954		- if (&GPTD6 == gptp) {
955		-#if !defined(STM32_TIM6_SUPPRESS_ISR)
956		- nvicDisableVector(STM32_TIM6_NUMBER);
957		-#endif
958		- rccDisableTIM6();
959		- }
960		-#endif
961		-
962		-#if STM32_GPT_USE_TIM7
963		- if (&GPTD7 == gptp) {
964		-#if !defined(STM32_TIM7_SUPPRESS_ISR)
965		- nvicDisableVector(STM32_TIM7_NUMBER);
966		-#endif
967		- rccDisableTIM7();
968		- }
969		-#endif
970		-
971		-#if STM32_GPT_USE_TIM8
972		- if (&GPTD8 == gptp) {
973		-#if !defined(STM32_TIM8_SUPPRESS_ISR)
974		- nvicDisableVector(STM32_TIM8_UP_NUMBER);
975		-#endif
976		- rccDisableTIM8();
977		- }
978		-#endif
979		-
980		-#if STM32_GPT_USE_TIM9
981		- if (&GPTD9 == gptp) {
982		-#if !defined(STM32_TIM9_SUPPRESS_ISR)
983		- nvicDisableVector(STM32_TIM9_NUMBER);
984		-#endif
985		- rccDisableTIM9();
986		- }
987		-#endif
988		-
989		-#if STM32_GPT_USE_TIM10
990		- if (&GPTD10 == gptp) {
991		-#if !defined(STM32_TIM10_SUPPRESS_ISR)
992		- nvicDisableVector(STM32_TIM10_NUMBER);
993		-#endif
994		- rccDisableTIM10();
995		- }
996		-#endif
997		-
998		-#if STM32_GPT_USE_TIM11
999		- if (&GPTD11 == gptp) {
1000		-#if !defined(STM32_TIM11_SUPPRESS_ISR)
1001		- nvicDisableVector(STM32_TIM11_NUMBER);
1002		-#endif
1003		- rccDisableTIM11();
1004		- }
1005		-#endif
1006		-
1007		-#if STM32_GPT_USE_TIM12
1008		- if (&GPTD12 == gptp) {
1009		-#if !defined(STM32_TIM12_SUPPRESS_ISR)
1010		- nvicDisableVector(STM32_TIM12_NUMBER);
1011		-#endif
1012		- rccDisableTIM12();
1013		- }
1014		-#endif
1015		-
1016		-#if STM32_GPT_USE_TIM13
1017		- if (&GPTD13 == gptp) {
1018		-#if !defined(STM32_TIM13_SUPPRESS_ISR)
1019		- nvicDisableVector(STM32_TIM13_NUMBER);
1020		-#endif
1021		- rccDisableTIM13();
1022		- }
1023		-#endif
1024		-
1025		-#if STM32_GPT_USE_TIM14
1026		- if (&GPTD14 == gptp) {
1027		-#if !defined(STM32_TIM14_SUPPRESS_ISR)
1028		- nvicDisableVector(STM32_TIM14_NUMBER);
1029		-#endif
1030		- rccDisableTIM14();
1031		- }
1032		-#endif
1033		-
1034		-#if STM32_GPT_USE_TIM15
1035		- if (&GPTD15 == gptp) {
1036		- rccDisableTIM15();
1037		- }
1038		-#endif
1039		-
1040		-#if STM32_GPT_USE_TIM16
1041		- if (&GPTD16 == gptp) {
1042		- rccDisableTIM16();
1043		- }
1044		-#endif
1045		-
1046		-#if STM32_GPT_USE_TIM17
1047		- if (&GPTD17 == gptp) {
1048		- rccDisableTIM17();
1049		- }
1050		-#endif
1051		-
1052		-#if STM32_GPT_USE_TIM21
1053		- if (&GPTD21 == gptp) {
1054		-#if !defined(STM32_TIM21_SUPPRESS_ISR)
1055		- nvicDisableVector(STM32_TIM21_NUMBER);
1056		-#endif
1057		- rccDisableTIM21();
1058		- }
1059		-#endif
1060		-
1061		-#if STM32_GPT_USE_TIM22
1062		- if (&GPTD22 == gptp) {
1063		-#if !defined(STM32_TIM22_SUPPRESS_ISR)
1064		- nvicDisableVector(STM32_TIM22_NUMBER);
1065		-#endif
1066		- rccDisableTIM22();
1067		- }
1068		-#endif
1069		- }
1070		-}
1071		-
1072		-/**
1073		- * @brief Starts the timer in continuous mode.
1074		- *
1075		- * @param[in] gptp pointer to the @p GPTDriver object
1076		- * @param[in] interval period in ticks
1077		- *
1078		- * @notapi
1079		- */
1080		-void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
1081		-
1082		- gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1083		- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1084		- gptp->tim->CNT = 0; /* Reset counter. */
1085		-
1086		- /* NOTE: After generating the UG event it takes several clock cycles before
1087		- SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
1088		- before the clearing of SR, to give it some time.*/
1089		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1090		- if (NULL != gptp->config->callback)
1091		- gptp->tim->DIER \|= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
1092		- gptp->tim->CR1 = STM32_TIM_CR1_ARPE \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
1093		-}
1094		-
1095		-/**
1096		- * @brief Stops the timer.
1097		- *
1098		- * @param[in] gptp pointer to the @p GPTDriver object
1099		- *
1100		- * @notapi
1101		- */
1102		-void gpt_lld_stop_timer(GPTDriver *gptp) {
1103		-
1104		- gptp->tim->CR1 = 0; /* Initially stopped. */
1105		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1106		-
1107		- /* All interrupts disabled.*/
1108		- gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
1109		-}
1110		-
1111		-/**
1112		- * @brief Starts the timer in one shot mode and waits for completion.
1113		- * @details This function specifically polls the timer waiting for completion
1114		- * in order to not have extra delays caused by interrupt servicing,
1115		- * this function is only recommended for short delays.
1116		- *
1117		- * @param[in] gptp pointer to the @p GPTDriver object
1118		- * @param[in] interval time interval in ticks
1119		- *
1120		- * @notapi
1121		- */
1122		-void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
1123		-
1124		- gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1125		- gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1126		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1127		- gptp->tim->CR1 = STM32_TIM_CR1_OPM \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
1128		- while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
1129		- ;
1130		- gptp->tim->SR = 0; /* Clear pending IRQs. */
1131		-}
1132		-
1133		-/**
1134		- * @brief Shared IRQ handler.
1135		- *
1136		- * @param[in] gptp pointer to a @p GPTDriver object
1137		- *
1138		- * @notapi
1139		- */
1140		-void gpt_lld_serve_interrupt(GPTDriver *gptp) {
1141		- uint32_t sr;
1142		-
1143		- sr = gptp->tim->SR;
1144		- sr &= gptp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
1145		- gptp->tim->SR = ~sr;
1146		- if ((sr & STM32_TIM_SR_UIF) != 0) {
1147		- _gpt_isr_invoke_cb(gptp);
1148		- }
1149		-}
1150		-
1151		-#endif /* HAL_USE_GPT */
1152		-
1153		-/** @} */
	1	+/*
	2	+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
	3	+
	4	+ Licensed under the Apache License, Version 2.0 (the "License");
	5	+ you may not use this file except in compliance with the License.
	6	+ You may obtain a copy of the License at
	7	+
	8	+ http://www.apache.org/licenses/LICENSE-2.0
	9	+
	10	+ Unless required by applicable law or agreed to in writing, software
	11	+ distributed under the License is distributed on an "AS IS" BASIS,
	12	+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	+ See the License for the specific language governing permissions and
	14	+ limitations under the License.
	15	+*/
	16	+
	17	+/**
	18	+ * @file TIMv1/hal_gpt_lld.c
	19	+ * @brief STM32 GPT subsystem low level driver source.
	20	+ *
	21	+ * @addtogroup GPT
	22	+ * @{
	23	+ */
	24	+
	25	+#include "hal.h"
	26	+
	27	+#if HAL_USE_GPT \|\| defined(__DOXYGEN__)
	28	+
	29	+/===========================================================================/
	30	+/* Driver local definitions. */
	31	+/===========================================================================/
	32	+
	33	+/===========================================================================/
	34	+/* Driver exported variables. */
	35	+/===========================================================================/
	36	+
	37	+/**
	38	+ * @brief GPTD1 driver identifier.
	39	+ * @note The driver GPTD1 allocates the complex timer TIM1 when enabled.
	40	+ */
	41	+#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
	42	+GPTDriver GPTD1;
	43	+#endif
	44	+
	45	+/**
	46	+ * @brief GPTD2 driver identifier.
	47	+ * @note The driver GPTD2 allocates the timer TIM2 when enabled.
	48	+ */
	49	+#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
	50	+GPTDriver GPTD2;
	51	+#endif
	52	+
	53	+/**
	54	+ * @brief GPTD3 driver identifier.
	55	+ * @note The driver GPTD3 allocates the timer TIM3 when enabled.
	56	+ */
	57	+#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
	58	+GPTDriver GPTD3;
	59	+#endif
	60	+
	61	+/**
	62	+ * @brief GPTD4 driver identifier.
	63	+ * @note The driver GPTD4 allocates the timer TIM4 when enabled.
	64	+ */
	65	+#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
	66	+GPTDriver GPTD4;
	67	+#endif
	68	+
	69	+/**
	70	+ * @brief GPTD5 driver identifier.
	71	+ * @note The driver GPTD5 allocates the timer TIM5 when enabled.
	72	+ */
	73	+#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
	74	+GPTDriver GPTD5;
	75	+#endif
	76	+
	77	+/**
	78	+ * @brief GPTD6 driver identifier.
	79	+ * @note The driver GPTD6 allocates the timer TIM6 when enabled.
	80	+ */
	81	+#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
	82	+GPTDriver GPTD6;
	83	+#endif
	84	+
	85	+/**
	86	+ * @brief GPTD7 driver identifier.
	87	+ * @note The driver GPTD7 allocates the timer TIM7 when enabled.
	88	+ */
	89	+#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
	90	+GPTDriver GPTD7;
	91	+#endif
	92	+
	93	+/**
	94	+ * @brief GPTD8 driver identifier.
	95	+ * @note The driver GPTD8 allocates the timer TIM8 when enabled.
	96	+ */
	97	+#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
	98	+GPTDriver GPTD8;
	99	+#endif
	100	+
	101	+/**
	102	+ * @brief GPTD9 driver identifier.
	103	+ * @note The driver GPTD9 allocates the timer TIM9 when enabled.
	104	+ */
	105	+#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
	106	+GPTDriver GPTD9;
	107	+#endif
	108	+
	109	+/**
	110	+ * @brief GPTD10 driver identifier.
	111	+ * @note The driver GPTD10 allocates the timer TIM10 when enabled.
	112	+ */
	113	+#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
	114	+GPTDriver GPTD10;
	115	+#endif
	116	+
	117	+/**
	118	+ * @brief GPTD11 driver identifier.
	119	+ * @note The driver GPTD11 allocates the timer TIM11 when enabled.
	120	+ */
	121	+#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
	122	+GPTDriver GPTD11;
	123	+#endif
	124	+
	125	+/**
	126	+ * @brief GPTD12 driver identifier.
	127	+ * @note The driver GPTD12 allocates the timer TIM12 when enabled.
	128	+ */
	129	+#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
	130	+GPTDriver GPTD12;
	131	+#endif
	132	+
	133	+/**
	134	+ * @brief GPTD13 driver identifier.
	135	+ * @note The driver GPTD13 allocates the timer TIM13 when enabled.
	136	+ */
	137	+#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
	138	+GPTDriver GPTD13;
	139	+#endif
	140	+
	141	+/**
	142	+ * @brief GPTD14 driver identifier.
	143	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	144	+ */
	145	+#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
	146	+GPTDriver GPTD14;
	147	+#endif
	148	+
	149	+/**
	150	+ * @brief GPTD15 driver identifier.
	151	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	152	+ */
	153	+#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
	154	+GPTDriver GPTD15;
	155	+#endif
	156	+
	157	+/**
	158	+ * @brief GPTD16 driver identifier.
	159	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	160	+ */
	161	+#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
	162	+GPTDriver GPTD16;
	163	+#endif
	164	+
	165	+/**
	166	+ * @brief GPTD17 driver identifier.
	167	+ * @note The driver GPTD14 allocates the timer TIM14 when enabled.
	168	+ */
	169	+#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
	170	+GPTDriver GPTD17;
	171	+#endif
	172	+
	173	+/**
	174	+ * @brief GPTD21 driver identifier.
	175	+ * @note The driver GPTD21 allocates the timer TIM21 when enabled.
	176	+ */
	177	+#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
	178	+GPTDriver GPTD21;
	179	+#endif
	180	+
	181	+/**
	182	+ * @brief GPTD22 driver identifier.
	183	+ * @note The driver GPTD22 allocates the timer TIM22 when enabled.
	184	+ */
	185	+#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
	186	+GPTDriver GPTD22;
	187	+#endif
	188	+
	189	+/===========================================================================/
	190	+/* Driver local variables and types. */
	191	+/===========================================================================/
	192	+
	193	+/===========================================================================/
	194	+/* Driver local functions. */
	195	+/===========================================================================/
	196	+
	197	+/===========================================================================/
	198	+/* Driver interrupt handlers. */
	199	+/===========================================================================/
	200	+
	201	+#if STM32_GPT_USE_TIM1 \|\| defined(__DOXYGEN__)
	202	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	203	+#if !defined(STM32_TIM1_UP_HANDLER)
	204	+#error "STM32_TIM1_UP_HANDLER not defined"
	205	+#endif
	206	+/**
	207	+ * @brief TIM1 interrupt handler.
	208	+ *
	209	+ * @isr
	210	+ */
	211	+OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
	212	+
	213	+ OSAL_IRQ_PROLOGUE();
	214	+
	215	+ gpt_lld_serve_interrupt(&GPTD1);
	216	+
	217	+ OSAL_IRQ_EPILOGUE();
	218	+}
	219	+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
	220	+#endif /* STM32_GPT_USE_TIM1 */
	221	+
	222	+#if STM32_GPT_USE_TIM2 \|\| defined(__DOXYGEN__)
	223	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	224	+#if !defined(STM32_TIM2_HANDLER)
	225	+#error "STM32_TIM2_HANDLER not defined"
	226	+#endif
	227	+/**
	228	+ * @brief TIM2 interrupt handler.
	229	+ *
	230	+ * @isr
	231	+ */
	232	+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
	233	+
	234	+ OSAL_IRQ_PROLOGUE();
	235	+
	236	+ gpt_lld_serve_interrupt(&GPTD2);
	237	+
	238	+ OSAL_IRQ_EPILOGUE();
	239	+}
	240	+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
	241	+#endif /* STM32_GPT_USE_TIM2 */
	242	+
	243	+#if STM32_GPT_USE_TIM3 \|\| defined(__DOXYGEN__)
	244	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	245	+#if !defined(STM32_TIM3_HANDLER)
	246	+#error "STM32_TIM3_HANDLER not defined"
	247	+#endif
	248	+/**
	249	+ * @brief TIM3 interrupt handler.
	250	+ *
	251	+ * @isr
	252	+ */
	253	+OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
	254	+
	255	+ OSAL_IRQ_PROLOGUE();
	256	+
	257	+ gpt_lld_serve_interrupt(&GPTD3);
	258	+
	259	+ OSAL_IRQ_EPILOGUE();
	260	+}
	261	+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
	262	+#endif /* STM32_GPT_USE_TIM3 */
	263	+
	264	+#if STM32_GPT_USE_TIM4 \|\| defined(__DOXYGEN__)
	265	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	266	+#if !defined(STM32_TIM4_HANDLER)
	267	+#error "STM32_TIM4_HANDLER not defined"
	268	+#endif
	269	+/**
	270	+ * @brief TIM4 interrupt handler.
	271	+ *
	272	+ * @isr
	273	+ */
	274	+OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
	275	+
	276	+ OSAL_IRQ_PROLOGUE();
	277	+
	278	+ gpt_lld_serve_interrupt(&GPTD4);
	279	+
	280	+ OSAL_IRQ_EPILOGUE();
	281	+}
	282	+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
	283	+#endif /* STM32_GPT_USE_TIM4 */
	284	+
	285	+#if STM32_GPT_USE_TIM5 \|\| defined(__DOXYGEN__)
	286	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	287	+#if !defined(STM32_TIM5_HANDLER)
	288	+#error "STM32_TIM5_HANDLER not defined"
	289	+#endif
	290	+/**
	291	+ * @brief TIM5 interrupt handler.
	292	+ *
	293	+ * @isr
	294	+ */
	295	+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
	296	+
	297	+ OSAL_IRQ_PROLOGUE();
	298	+
	299	+ gpt_lld_serve_interrupt(&GPTD5);
	300	+
	301	+ OSAL_IRQ_EPILOGUE();
	302	+}
	303	+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
	304	+#endif /* STM32_GPT_USE_TIM5 */
	305	+
	306	+#if STM32_GPT_USE_TIM6 \|\| defined(__DOXYGEN__)
	307	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	308	+#if !defined(STM32_TIM6_HANDLER)
	309	+#error "STM32_TIM6_HANDLER not defined"
	310	+#endif
	311	+/**
	312	+ * @brief TIM6 interrupt handler.
	313	+ *
	314	+ * @isr
	315	+ */
	316	+OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
	317	+
	318	+ OSAL_IRQ_PROLOGUE();
	319	+
	320	+ gpt_lld_serve_interrupt(&GPTD6);
	321	+
	322	+ OSAL_IRQ_EPILOGUE();
	323	+}
	324	+#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
	325	+#endif /* STM32_GPT_USE_TIM6 */
	326	+
	327	+#if STM32_GPT_USE_TIM7 \|\| defined(__DOXYGEN__)
	328	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	329	+#if !defined(STM32_TIM7_HANDLER)
	330	+#error "STM32_TIM7_HANDLER not defined"
	331	+#endif
	332	+/**
	333	+ * @brief TIM7 interrupt handler.
	334	+ *
	335	+ * @isr
	336	+ */
	337	+OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
	338	+
	339	+ OSAL_IRQ_PROLOGUE();
	340	+
	341	+ gpt_lld_serve_interrupt(&GPTD7);
	342	+
	343	+ OSAL_IRQ_EPILOGUE();
	344	+}
	345	+#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
	346	+#endif /* STM32_GPT_USE_TIM7 */
	347	+
	348	+#if STM32_GPT_USE_TIM8 \|\| defined(__DOXYGEN__)
	349	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	350	+#if !defined(STM32_TIM8_UP_HANDLER)
	351	+#error "STM32_TIM8_UP_HANDLER not defined"
	352	+#endif
	353	+/**
	354	+ * @brief TIM8 interrupt handler.
	355	+ *
	356	+ * @isr
	357	+ */
	358	+OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
	359	+
	360	+ OSAL_IRQ_PROLOGUE();
	361	+
	362	+ gpt_lld_serve_interrupt(&GPTD8);
	363	+
	364	+ OSAL_IRQ_EPILOGUE();
	365	+}
	366	+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
	367	+#endif /* STM32_GPT_USE_TIM8 */
	368	+
	369	+#if STM32_GPT_USE_TIM9 \|\| defined(__DOXYGEN__)
	370	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	371	+#error "TIM9 ISR not defined by platform"
	372	+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
	373	+#endif /* STM32_GPT_USE_TIM9 */
	374	+
	375	+#if STM32_GPT_USE_TIM10 \|\| defined(__DOXYGEN__)
	376	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	377	+#error "TIM10 ISR not defined by platform"
	378	+#endif /* !defined(STM32_TIM10_SUPPRESS_ISR) */
	379	+#endif /* STM32_GPT_USE_TIM10 */
	380	+
	381	+#if STM32_GPT_USE_TIM11 \|\| defined(__DOXYGEN__)
	382	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	383	+#error "TIM11 ISR not defined by platform"
	384	+#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
	385	+#endif /* STM32_GPT_USE_TIM11 */
	386	+
	387	+#if STM32_GPT_USE_TIM12 \|\| defined(__DOXYGEN__)
	388	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	389	+#error "TIM12 ISR not defined by platform"
	390	+#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
	391	+#endif /* STM32_GPT_USE_TIM12 */
	392	+
	393	+#if STM32_GPT_USE_TIM13 \|\| defined(__DOXYGEN__)
	394	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	395	+#error "TIM13 ISR not defined by platform"
	396	+#endif /* !defined(STM32_TIM13_SUPPRESS_ISR) */
	397	+#endif /* STM32_GPT_USE_TIM13 */
	398	+
	399	+#if STM32_GPT_USE_TIM14 \|\| defined(__DOXYGEN__)
	400	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	401	+#error "TIM14 ISR not defined by platform"
	402	+#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
	403	+#endif /* STM32_GPT_USE_TIM14 */
	404	+
	405	+#if STM32_GPT_USE_TIM15 \|\| defined(__DOXYGEN__)
	406	+#if !defined(STM32_TIM15_SUPPRESS_ISR)
	407	+#error "TIM15 ISR not defined by platform"
	408	+#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */
	409	+#endif /* STM32_GPT_USE_TIM15 */
	410	+
	411	+#if STM32_GPT_USE_TIM16 \|\| defined(__DOXYGEN__)
	412	+#if !defined(STM32_TIM16_SUPPRESS_ISR)
	413	+#error "TIM16 ISR not defined by platform"
	414	+#endif /* !defined(STM32_TIM16_SUPPRESS_ISR) */
	415	+#endif /* STM32_GPT_USE_TIM16 */
	416	+
	417	+#if STM32_GPT_USE_TIM17 \|\| defined(__DOXYGEN__)
	418	+#if !defined(STM32_TIM17_SUPPRESS_ISR)
	419	+#error "TIM17 ISR not defined by platform"
	420	+#endif /* !defined(STM32_TIM17_SUPPRESS_ISR) */
	421	+#endif /* STM32_GPT_USE_TIM17 */
	422	+
	423	+#if STM32_GPT_USE_TIM21 \|\| defined(__DOXYGEN__)
	424	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	425	+#if !defined(STM32_TIM21_HANDLER)
	426	+#error "STM32_TIM21_HANDLER not defined"
	427	+#endif
	428	+/**
	429	+ * @brief TIM21 interrupt handler.
	430	+ *
	431	+ * @isr
	432	+ */
	433	+OSAL_IRQ_HANDLER(STM32_TIM21_HANDLER) {
	434	+
	435	+ OSAL_IRQ_PROLOGUE();
	436	+
	437	+ gpt_lld_serve_interrupt(&GPTD21);
	438	+
	439	+ OSAL_IRQ_EPILOGUE();
	440	+}
	441	+#endif /* !defined(STM32_TIM21_SUPPRESS_ISR) */
	442	+#endif /* STM32_GPT_USE_TIM21 */
	443	+
	444	+#if STM32_GPT_USE_TIM22 \|\| defined(__DOXYGEN__)
	445	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	446	+#if !defined(STM32_TIM22_HANDLER)
	447	+#error "STM32_TIM22_HANDLER not defined"
	448	+#endif
	449	+/**
	450	+ * @brief TIM22 interrupt handler.
	451	+ *
	452	+ * @isr
	453	+ */
	454	+OSAL_IRQ_HANDLER(STM32_TIM22_HANDLER) {
	455	+
	456	+ OSAL_IRQ_PROLOGUE();
	457	+
	458	+ gpt_lld_serve_interrupt(&GPTD22);
	459	+
	460	+ OSAL_IRQ_EPILOGUE();
	461	+}
	462	+#endif /* !defined(STM32_TIM22_SUPPRESS_ISR) */
	463	+#endif /* STM32_GPT_USE_TIM22 */
	464	+
	465	+/===========================================================================/
	466	+/* Driver exported functions. */
	467	+/===========================================================================/
	468	+
	469	+/**
	470	+ * @brief Low level GPT driver initialization.
	471	+ *
	472	+ * @notapi
	473	+ */
	474	+void gpt_lld_init(void) {
	475	+
	476	+#if STM32_GPT_USE_TIM1
	477	+ /* Driver initialization.*/
	478	+ GPTD1.tim = STM32_TIM1;
	479	+ gptObjectInit(&GPTD1);
	480	+#endif
	481	+
	482	+#if STM32_GPT_USE_TIM2
	483	+ /* Driver initialization.*/
	484	+ GPTD2.tim = STM32_TIM2;
	485	+ gptObjectInit(&GPTD2);
	486	+#endif
	487	+
	488	+#if STM32_GPT_USE_TIM3
	489	+ /* Driver initialization.*/
	490	+ GPTD3.tim = STM32_TIM3;
	491	+ gptObjectInit(&GPTD3);
	492	+#endif
	493	+
	494	+#if STM32_GPT_USE_TIM4
	495	+ /* Driver initialization.*/
	496	+ GPTD4.tim = STM32_TIM4;
	497	+ gptObjectInit(&GPTD4);
	498	+#endif
	499	+
	500	+#if STM32_GPT_USE_TIM5
	501	+ /* Driver initialization.*/
	502	+ GPTD5.tim = STM32_TIM5;
	503	+ gptObjectInit(&GPTD5);
	504	+#endif
	505	+
	506	+#if STM32_GPT_USE_TIM6
	507	+ /* Driver initialization.*/
	508	+ GPTD6.tim = STM32_TIM6;
	509	+ gptObjectInit(&GPTD6);
	510	+#endif
	511	+
	512	+#if STM32_GPT_USE_TIM7
	513	+ /* Driver initialization.*/
	514	+ GPTD7.tim = STM32_TIM7;
	515	+ gptObjectInit(&GPTD7);
	516	+#endif
	517	+
	518	+#if STM32_GPT_USE_TIM8
	519	+ /* Driver initialization.*/
	520	+ GPTD8.tim = STM32_TIM8;
	521	+ gptObjectInit(&GPTD8);
	522	+#endif
	523	+
	524	+#if STM32_GPT_USE_TIM9
	525	+ /* Driver initialization.*/
	526	+ GPTD9.tim = STM32_TIM9;
	527	+ gptObjectInit(&GPTD9);
	528	+#endif
	529	+
	530	+#if STM32_GPT_USE_TIM10
	531	+ /* Driver initialization.*/
	532	+ GPTD10.tim = STM32_TIM10;
	533	+ gptObjectInit(&GPTD10);
	534	+#endif
	535	+
	536	+#if STM32_GPT_USE_TIM11
	537	+ /* Driver initialization.*/
	538	+ GPTD11.tim = STM32_TIM11;
	539	+ gptObjectInit(&GPTD11);
	540	+#endif
	541	+
	542	+#if STM32_GPT_USE_TIM12
	543	+ /* Driver initialization.*/
	544	+ GPTD12.tim = STM32_TIM12;
	545	+ gptObjectInit(&GPTD12);
	546	+#endif
	547	+
	548	+#if STM32_GPT_USE_TIM13
	549	+ /* Driver initialization.*/
	550	+ GPTD13.tim = STM32_TIM13;
	551	+ gptObjectInit(&GPTD13);
	552	+#endif
	553	+
	554	+#if STM32_GPT_USE_TIM14
	555	+ /* Driver initialization.*/
	556	+ GPTD14.tim = STM32_TIM14;
	557	+ gptObjectInit(&GPTD14);
	558	+#endif
	559	+
	560	+#if STM32_GPT_USE_TIM15
	561	+ /* Driver initialization.*/
	562	+ GPTD15.tim = STM32_TIM15;
	563	+ gptObjectInit(&GPTD15);
	564	+#endif
	565	+
	566	+#if STM32_GPT_USE_TIM16
	567	+ /* Driver initialization.*/
	568	+ GPTD16.tim = STM32_TIM16;
	569	+ gptObjectInit(&GPTD16);
	570	+#endif
	571	+
	572	+#if STM32_GPT_USE_TIM17
	573	+ /* Driver initialization.*/
	574	+ GPTD17.tim = STM32_TIM17;
	575	+ gptObjectInit(&GPTD17);
	576	+#endif
	577	+
	578	+#if STM32_GPT_USE_TIM21
	579	+ /* Driver initialization.*/
	580	+ GPTD21.tim = STM32_TIM21;
	581	+ gptObjectInit(&GPTD21);
	582	+#endif
	583	+
	584	+#if STM32_GPT_USE_TIM22
	585	+ /* Driver initialization.*/
	586	+ GPTD22.tim = STM32_TIM22;
	587	+ gptObjectInit(&GPTD22);
	588	+#endif
	589	+}
	590	+
	591	+/**
	592	+ * @brief Configures and activates the GPT peripheral.
	593	+ *
	594	+ * @param[in] gptp pointer to the @p GPTDriver object
	595	+ *
	596	+ * @notapi
	597	+ */
	598	+void gpt_lld_start(GPTDriver *gptp) {
	599	+ uint16_t psc;
	600	+
	601	+ if (gptp->state == GPT_STOP) {
	602	+ /* Clock activation.*/
	603	+#if STM32_GPT_USE_TIM1
	604	+ if (&GPTD1 == gptp) {
	605	+ rccEnableTIM1(true);
	606	+ rccResetTIM1();
	607	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	608	+ nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
	609	+#endif
	610	+#if defined(STM32_TIM1CLK)
	611	+ gptp->clock = STM32_TIM1CLK;
	612	+#else
	613	+ gptp->clock = STM32_TIMCLK2;
	614	+#endif
	615	+ }
	616	+#endif
	617	+
	618	+#if STM32_GPT_USE_TIM2
	619	+ if (&GPTD2 == gptp) {
	620	+ rccEnableTIM2(true);
	621	+ rccResetTIM2();
	622	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	623	+ nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
	624	+#endif
	625	+#if defined(STM32_TIM2CLK)
	626	+ gptp->clock = STM32_TIM2CLK;
	627	+#else
	628	+ gptp->clock = STM32_TIMCLK1;
	629	+#endif
	630	+ }
	631	+#endif
	632	+
	633	+#if STM32_GPT_USE_TIM3
	634	+ if (&GPTD3 == gptp) {
	635	+ rccEnableTIM3(true);
	636	+ rccResetTIM3();
	637	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	638	+ nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
	639	+#endif
	640	+#if defined(STM32_TIM3CLK)
	641	+ gptp->clock = STM32_TIM3CLK;
	642	+#else
	643	+ gptp->clock = STM32_TIMCLK1;
	644	+#endif
	645	+ }
	646	+#endif
	647	+
	648	+#if STM32_GPT_USE_TIM4
	649	+ if (&GPTD4 == gptp) {
	650	+ rccEnableTIM4(true);
	651	+ rccResetTIM4();
	652	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	653	+ nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
	654	+#endif
	655	+#if defined(STM32_TIM4CLK)
	656	+ gptp->clock = STM32_TIM4CLK;
	657	+#else
	658	+ gptp->clock = STM32_TIMCLK1;
	659	+#endif
	660	+ }
	661	+#endif
	662	+
	663	+#if STM32_GPT_USE_TIM5
	664	+ if (&GPTD5 == gptp) {
	665	+ rccEnableTIM5(true);
	666	+ rccResetTIM5();
	667	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	668	+ nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
	669	+#endif
	670	+#if defined(STM32_TIM5CLK)
	671	+ gptp->clock = STM32_TIM5CLK;
	672	+#else
	673	+ gptp->clock = STM32_TIMCLK1;
	674	+#endif
	675	+ }
	676	+#endif
	677	+
	678	+#if STM32_GPT_USE_TIM6
	679	+ if (&GPTD6 == gptp) {
	680	+ rccEnableTIM6(true);
	681	+ rccResetTIM6();
	682	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	683	+ nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
	684	+#endif
	685	+#if defined(STM32_TIM6CLK)
	686	+ gptp->clock = STM32_TIM6CLK;
	687	+#else
	688	+ gptp->clock = STM32_TIMCLK1;
	689	+#endif
	690	+ }
	691	+#endif
	692	+
	693	+#if STM32_GPT_USE_TIM7
	694	+ if (&GPTD7 == gptp) {
	695	+ rccEnableTIM7(true);
	696	+ rccResetTIM7();
	697	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	698	+ nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
	699	+#endif
	700	+#if defined(STM32_TIM7CLK)
	701	+ gptp->clock = STM32_TIM7CLK;
	702	+#else
	703	+ gptp->clock = STM32_TIMCLK1;
	704	+#endif
	705	+ }
	706	+#endif
	707	+
	708	+#if STM32_GPT_USE_TIM8
	709	+ if (&GPTD8 == gptp) {
	710	+ rccEnableTIM8(true);
	711	+ rccResetTIM8();
	712	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	713	+ nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
	714	+#endif
	715	+#if defined(STM32_TIM8CLK)
	716	+ gptp->clock = STM32_TIM8CLK;
	717	+#else
	718	+ gptp->clock = STM32_TIMCLK2;
	719	+#endif
	720	+ }
	721	+#endif
	722	+
	723	+#if STM32_GPT_USE_TIM9
	724	+ if (&GPTD9 == gptp) {
	725	+ rccEnableTIM9(true);
	726	+ rccResetTIM9();
	727	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	728	+ nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
	729	+#endif
	730	+#if defined(STM32_TIM9CLK)
	731	+ gptp->clock = STM32_TIM9CLK;
	732	+#else
	733	+ gptp->clock = STM32_TIMCLK2;
	734	+#endif
	735	+ }
	736	+#endif
	737	+
	738	+#if STM32_GPT_USE_TIM10
	739	+ if (&GPTD10 == gptp) {
	740	+ rccEnableTIM10(true);
	741	+ rccResetTIM10();
	742	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	743	+ nvicEnableVector(STM32_TIM10_NUMBER, STM32_GPT_TIM10_IRQ_PRIORITY);
	744	+#endif
	745	+#if defined(STM32_TIM10CLK)
	746	+ gptp->clock = STM32_TIM10CLK;
	747	+#else
	748	+ gptp->clock = STM32_TIMCLK2;
	749	+#endif
	750	+ }
	751	+#endif
	752	+
	753	+#if STM32_GPT_USE_TIM11
	754	+ if (&GPTD11 == gptp) {
	755	+ rccEnableTIM11(true);
	756	+ rccResetTIM11();
	757	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	758	+ nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
	759	+#endif
	760	+#if defined(STM32_TIM11CLK)
	761	+ gptp->clock = STM32_TIM11CLK;
	762	+#else
	763	+ gptp->clock = STM32_TIMCLK2;
	764	+#endif
	765	+ }
	766	+#endif
	767	+
	768	+#if STM32_GPT_USE_TIM12
	769	+ if (&GPTD12 == gptp) {
	770	+ rccEnableTIM12(true);
	771	+ rccResetTIM12();
	772	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	773	+ nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
	774	+#endif
	775	+#if defined(STM32_TIM12CLK)
	776	+ gptp->clock = STM32_TIM12CLK;
	777	+#else
	778	+ gptp->clock = STM32_TIMCLK1;
	779	+#endif
	780	+ }
	781	+#endif
	782	+
	783	+#if STM32_GPT_USE_TIM13
	784	+ if (&GPTD13 == gptp) {
	785	+ rccEnableTIM13(true);
	786	+ rccResetTIM13();
	787	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	788	+ nvicEnableVector(STM32_TIM13_NUMBER, STM32_GPT_TIM13_IRQ_PRIORITY);
	789	+#endif
	790	+#if defined(STM32_TIM13CLK)
	791	+ gptp->clock = STM32_TIM13CLK;
	792	+#else
	793	+ gptp->clock = STM32_TIMCLK1;
	794	+#endif
	795	+ }
	796	+#endif
	797	+
	798	+#if STM32_GPT_USE_TIM14
	799	+ if (&GPTD14 == gptp) {
	800	+ rccEnableTIM14(true);
	801	+ rccResetTIM14();
	802	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	803	+ nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
	804	+#endif
	805	+#if defined(STM32_TIM14CLK)
	806	+ gptp->clock = STM32_TIM14CLK;
	807	+#else
	808	+ gptp->clock = STM32_TIMCLK1;
	809	+#endif
	810	+ }
	811	+#endif
	812	+
	813	+#if STM32_GPT_USE_TIM15
	814	+ if (&GPTD15 == gptp) {
	815	+ rccEnableTIM15(true);
	816	+ rccResetTIM15();
	817	+#if defined(STM32_TIM15CLK)
	818	+ gptp->clock = STM32_TIM15CLK;
	819	+#else
	820	+ gptp->clock = STM32_TIMCLK2;
	821	+#endif
	822	+ }
	823	+#endif
	824	+
	825	+#if STM32_GPT_USE_TIM16
	826	+ if (&GPTD16 == gptp) {
	827	+ rccEnableTIM16(true);
	828	+ rccResetTIM16();
	829	+#if defined(STM32_TIM16CLK)
	830	+ gptp->clock = STM32_TIM16CLK;
	831	+#else
	832	+ gptp->clock = STM32_TIMCLK2;
	833	+#endif
	834	+ }
	835	+#endif
	836	+
	837	+#if STM32_GPT_USE_TIM17
	838	+ if (&GPTD17 == gptp) {
	839	+ rccEnableTIM17(true);
	840	+ rccResetTIM17();
	841	+#if defined(STM32_TIM17CLK)
	842	+ gptp->clock = STM32_TIM17CLK;
	843	+#else
	844	+ gptp->clock = STM32_TIMCLK2;
	845	+#endif
	846	+ }
	847	+#endif
	848	+
	849	+#if STM32_GPT_USE_TIM21
	850	+ if (&GPTD21 == gptp) {
	851	+ rccEnableTIM21(true);
	852	+ rccResetTIM21();
	853	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	854	+ nvicEnableVector(STM32_TIM21_NUMBER, STM32_GPT_TIM21_IRQ_PRIORITY);
	855	+#endif
	856	+#if defined(STM32_TIM21CLK)
	857	+ gptp->clock = STM32_TIM21CLK;
	858	+#else
	859	+ gptp->clock = STM32_TIMCLK1;
	860	+#endif
	861	+ }
	862	+#endif
	863	+
	864	+#if STM32_GPT_USE_TIM22
	865	+ if (&GPTD22 == gptp) {
	866	+ rccEnableTIM22(true);
	867	+ rccResetTIM22();
	868	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	869	+ nvicEnableVector(STM32_TIM22_NUMBER, STM32_GPT_TIM22_IRQ_PRIORITY);
	870	+#endif
	871	+#if defined(STM32_TIM22CLK)
	872	+ gptp->clock = STM32_TIM22CLK;
	873	+#else
	874	+ gptp->clock = STM32_TIMCLK1;
	875	+#endif
	876	+ }
	877	+#endif
	878	+ }
	879	+
	880	+ /* Prescaler value calculation.*/
	881	+ psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
	882	+ osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
	883	+ "invalid frequency");
	884	+
	885	+ /* Timer configuration.*/
	886	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
	887	+ gptp->tim->CR2 = gptp->config->cr2;
	888	+ gptp->tim->PSC = psc; /* Prescaler value. */
	889	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	890	+ gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
	891	+ ~STM32_TIM_DIER_IRQ_MASK;
	892	+}
	893	+
	894	+/**
	895	+ * @brief Deactivates the GPT peripheral.
	896	+ *
	897	+ * @param[in] gptp pointer to the @p GPTDriver object
	898	+ *
	899	+ * @notapi
	900	+ */
	901	+void gpt_lld_stop(GPTDriver *gptp) {
	902	+
	903	+ if (gptp->state == GPT_READY) {
	904	+ gptp->tim->CR1 = 0U; /* Timer disabled. */
	905	+ gptp->tim->DIER = 0U; /* All IRQs disabled. */
	906	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	907	+
	908	+#if STM32_GPT_USE_TIM1
	909	+ if (&GPTD1 == gptp) {
	910	+#if !defined(STM32_TIM1_SUPPRESS_ISR)
	911	+ nvicDisableVector(STM32_TIM1_UP_NUMBER);
	912	+#endif
	913	+ rccDisableTIM1();
	914	+ }
	915	+#endif
	916	+
	917	+#if STM32_GPT_USE_TIM2
	918	+ if (&GPTD2 == gptp) {
	919	+#if !defined(STM32_TIM2_SUPPRESS_ISR)
	920	+ nvicDisableVector(STM32_TIM2_NUMBER);
	921	+#endif
	922	+ rccDisableTIM2();
	923	+ }
	924	+#endif
	925	+
	926	+#if STM32_GPT_USE_TIM3
	927	+ if (&GPTD3 == gptp) {
	928	+#if !defined(STM32_TIM3_SUPPRESS_ISR)
	929	+ nvicDisableVector(STM32_TIM3_NUMBER);
	930	+#endif
	931	+ rccDisableTIM3();
	932	+ }
	933	+#endif
	934	+
	935	+#if STM32_GPT_USE_TIM4
	936	+ if (&GPTD4 == gptp) {
	937	+#if !defined(STM32_TIM4_SUPPRESS_ISR)
	938	+ nvicDisableVector(STM32_TIM4_NUMBER);
	939	+#endif
	940	+ rccDisableTIM4();
	941	+ }
	942	+#endif
	943	+
	944	+#if STM32_GPT_USE_TIM5
	945	+ if (&GPTD5 == gptp) {
	946	+#if !defined(STM32_TIM5_SUPPRESS_ISR)
	947	+ nvicDisableVector(STM32_TIM5_NUMBER);
	948	+#endif
	949	+ rccDisableTIM5();
	950	+ }
	951	+#endif
	952	+
	953	+#if STM32_GPT_USE_TIM6
	954	+ if (&GPTD6 == gptp) {
	955	+#if !defined(STM32_TIM6_SUPPRESS_ISR)
	956	+ nvicDisableVector(STM32_TIM6_NUMBER);
	957	+#endif
	958	+ rccDisableTIM6();
	959	+ }
	960	+#endif
	961	+
	962	+#if STM32_GPT_USE_TIM7
	963	+ if (&GPTD7 == gptp) {
	964	+#if !defined(STM32_TIM7_SUPPRESS_ISR)
	965	+ nvicDisableVector(STM32_TIM7_NUMBER);
	966	+#endif
	967	+ rccDisableTIM7();
	968	+ }
	969	+#endif
	970	+
	971	+#if STM32_GPT_USE_TIM8
	972	+ if (&GPTD8 == gptp) {
	973	+#if !defined(STM32_TIM8_SUPPRESS_ISR)
	974	+ nvicDisableVector(STM32_TIM8_UP_NUMBER);
	975	+#endif
	976	+ rccDisableTIM8();
	977	+ }
	978	+#endif
	979	+
	980	+#if STM32_GPT_USE_TIM9
	981	+ if (&GPTD9 == gptp) {
	982	+#if !defined(STM32_TIM9_SUPPRESS_ISR)
	983	+ nvicDisableVector(STM32_TIM9_NUMBER);
	984	+#endif
	985	+ rccDisableTIM9();
	986	+ }
	987	+#endif
	988	+
	989	+#if STM32_GPT_USE_TIM10
	990	+ if (&GPTD10 == gptp) {
	991	+#if !defined(STM32_TIM10_SUPPRESS_ISR)
	992	+ nvicDisableVector(STM32_TIM10_NUMBER);
	993	+#endif
	994	+ rccDisableTIM10();
	995	+ }
	996	+#endif
	997	+
	998	+#if STM32_GPT_USE_TIM11
	999	+ if (&GPTD11 == gptp) {
	1000	+#if !defined(STM32_TIM11_SUPPRESS_ISR)
	1001	+ nvicDisableVector(STM32_TIM11_NUMBER);
	1002	+#endif
	1003	+ rccDisableTIM11();
	1004	+ }
	1005	+#endif
	1006	+
	1007	+#if STM32_GPT_USE_TIM12
	1008	+ if (&GPTD12 == gptp) {
	1009	+#if !defined(STM32_TIM12_SUPPRESS_ISR)
	1010	+ nvicDisableVector(STM32_TIM12_NUMBER);
	1011	+#endif
	1012	+ rccDisableTIM12();
	1013	+ }
	1014	+#endif
	1015	+
	1016	+#if STM32_GPT_USE_TIM13
	1017	+ if (&GPTD13 == gptp) {
	1018	+#if !defined(STM32_TIM13_SUPPRESS_ISR)
	1019	+ nvicDisableVector(STM32_TIM13_NUMBER);
	1020	+#endif
	1021	+ rccDisableTIM13();
	1022	+ }
	1023	+#endif
	1024	+
	1025	+#if STM32_GPT_USE_TIM14
	1026	+ if (&GPTD14 == gptp) {
	1027	+#if !defined(STM32_TIM14_SUPPRESS_ISR)
	1028	+ nvicDisableVector(STM32_TIM14_NUMBER);
	1029	+#endif
	1030	+ rccDisableTIM14();
	1031	+ }
	1032	+#endif
	1033	+
	1034	+#if STM32_GPT_USE_TIM15
	1035	+ if (&GPTD15 == gptp) {
	1036	+ rccDisableTIM15();
	1037	+ }
	1038	+#endif
	1039	+
	1040	+#if STM32_GPT_USE_TIM16
	1041	+ if (&GPTD16 == gptp) {
	1042	+ rccDisableTIM16();
	1043	+ }
	1044	+#endif
	1045	+
	1046	+#if STM32_GPT_USE_TIM17
	1047	+ if (&GPTD17 == gptp) {
	1048	+ rccDisableTIM17();
	1049	+ }
	1050	+#endif
	1051	+
	1052	+#if STM32_GPT_USE_TIM21
	1053	+ if (&GPTD21 == gptp) {
	1054	+#if !defined(STM32_TIM21_SUPPRESS_ISR)
	1055	+ nvicDisableVector(STM32_TIM21_NUMBER);
	1056	+#endif
	1057	+ rccDisableTIM21();
	1058	+ }
	1059	+#endif
	1060	+
	1061	+#if STM32_GPT_USE_TIM22
	1062	+ if (&GPTD22 == gptp) {
	1063	+#if !defined(STM32_TIM22_SUPPRESS_ISR)
	1064	+ nvicDisableVector(STM32_TIM22_NUMBER);
	1065	+#endif
	1066	+ rccDisableTIM22();
	1067	+ }
	1068	+#endif
	1069	+ }
	1070	+}
	1071	+
	1072	+/**
	1073	+ * @brief Starts the timer in continuous mode.
	1074	+ *
	1075	+ * @param[in] gptp pointer to the @p GPTDriver object
	1076	+ * @param[in] interval period in ticks
	1077	+ *
	1078	+ * @notapi
	1079	+ */
	1080	+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
	1081	+
	1082	+ gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
	1083	+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
	1084	+ gptp->tim->CNT = 0U; /* Reset counter. */
	1085	+
	1086	+ /* NOTE: After generating the UG event it takes several clock cycles before
	1087	+ SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
	1088	+ before the clearing of SR, to give it some time.*/
	1089	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1090	+ if (NULL != gptp->config->callback)
	1091	+ gptp->tim->DIER \|= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
	1092	+ gptp->tim->CR1 = STM32_TIM_CR1_ARPE \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
	1093	+}
	1094	+
	1095	+/**
	1096	+ * @brief Stops the timer.
	1097	+ *
	1098	+ * @param[in] gptp pointer to the @p GPTDriver object
	1099	+ *
	1100	+ * @notapi
	1101	+ */
	1102	+void gpt_lld_stop_timer(GPTDriver *gptp) {
	1103	+
	1104	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
	1105	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1106	+
	1107	+ /* All interrupts disabled.*/
	1108	+ gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
	1109	+}
	1110	+
	1111	+/**
	1112	+ * @brief Starts the timer in one shot mode and waits for completion.
	1113	+ * @details This function specifically polls the timer waiting for completion
	1114	+ * in order to not have extra delays caused by interrupt servicing,
	1115	+ * this function is only recommended for short delays.
	1116	+ *
	1117	+ * @param[in] gptp pointer to the @p GPTDriver object
	1118	+ * @param[in] interval time interval in ticks
	1119	+ *
	1120	+ * @notapi
	1121	+ */
	1122	+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
	1123	+
	1124	+ gptp->tim->CR1 = STM32_TIM_CR1_UDIS; /* Immediate update. */
	1125	+ gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
	1126	+ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
	1127	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1128	+ gptp->tim->CR1 = STM32_TIM_CR1_OPM \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
	1129	+ while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
	1130	+ ;
	1131	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
	1132	+}
	1133	+
	1134	+/**
	1135	+ * @brief Shared IRQ handler.
	1136	+ *
	1137	+ * @param[in] gptp pointer to a @p GPTDriver object
	1138	+ *
	1139	+ * @notapi
	1140	+ */
	1141	+void gpt_lld_serve_interrupt(GPTDriver *gptp) {
	1142	+ uint32_t sr;
	1143	+
	1144	+ sr = gptp->tim->SR;
	1145	+ sr &= gptp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
	1146	+ gptp->tim->SR = ~sr;
	1147	+ if ((sr & STM32_TIM_SR_UIF) != 0) {
	1148	+ _gpt_isr_invoke_cb(gptp);
	1149	+ }
	1150	+}
	1151	+
	1152	+#endif /* HAL_USE_GPT */
	1153	+
	1154	+/** @} */

--- branches/stable_21.11.x/readme.txt (revision 15841)

+++ branches/stable_21.11.x/readme.txt (revision 15842)

		@@ -75,6 +75,7 @@
75	75
76	76	* 21.11.3 *
77	77	- NEW: Added EFL driver support for STM32F401/411.
	78	+- FIX: Fixed problem in STM32 gpt_lld_polled_delay() implementation (bug #1241).
78	79	- FIX: Fixed invalid delay loop in STM32G0/WL ADCv5 driver (bug #1240).
79	80	- FIX: Fixed missing clock enables for some GPIOS on some STM32L4s (bug #1237).
80	81	- FIX: Fixed old bugs in serial driver header (bug #1236).

--- trunk/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15841)

+++ trunk/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c (revision 15842)

		@@ -883,10 +883,10 @@
883	883	"invalid frequency");
884	884
885	885	/* Timer configuration.*/
886		- gptp->tim->CR1 = 0; /* Initially stopped. */
	886	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
887	887	gptp->tim->CR2 = gptp->config->cr2;
888	888	gptp->tim->PSC = psc; /* Prescaler value. */
889		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	889	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
890	890	gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
891	891	~STM32_TIM_DIER_IRQ_MASK;
892	892	}

		@@ -901,9 +901,9 @@
901	901	void gpt_lld_stop(GPTDriver *gptp) {
902	902
903	903	if (gptp->state == GPT_READY) {
904		- gptp->tim->CR1 = 0; /* Timer disabled. */
905		- gptp->tim->DIER = 0; /* All IRQs disabled. */
906		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	904	+ gptp->tim->CR1 = 0U; /* Timer disabled. */
	905	+ gptp->tim->DIER = 0U; /* All IRQs disabled. */
	906	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
907	907
908	908	#if STM32_GPT_USE_TIM1
909	909	if (&GPTD1 == gptp) {

		@@ -1081,12 +1081,12 @@
1081	1081
1082	1082	gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1083	1083	gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1084		- gptp->tim->CNT = 0; /* Reset counter. */
	1084	+ gptp->tim->CNT = 0U; /* Reset counter. */
1085	1085
1086	1086	/* NOTE: After generating the UG event it takes several clock cycles before
1087	1087	SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
1088	1088	before the clearing of SR, to give it some time.*/
1089		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	1089	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
1090	1090	if (NULL != gptp->config->callback)
1091	1091	gptp->tim->DIER \|= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
1092	1092	gptp->tim->CR1 = STM32_TIM_CR1_ARPE \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;

		@@ -1101,8 +1101,8 @@
1101	1101	*/
1102	1102	void gpt_lld_stop_timer(GPTDriver *gptp) {
1103	1103
1104		- gptp->tim->CR1 = 0; /* Initially stopped. */
1105		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	1104	+ gptp->tim->CR1 = 0U; /* Initially stopped. */
	1105	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
1106	1106
1107	1107	/* All interrupts disabled.*/
1108	1108	gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;

		@@ -1121,13 +1121,14 @@
1121	1121	*/
1122	1122	void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
1123	1123
	1124	+ gptp->tim->CR1 = STM32_TIM_CR1_UDIS; /* Immediate update. */
1124	1125	gptp->tim->ARR = (uint32_t)(interval - 1U); /* Time constant. */
1125	1126	gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
1126		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	1127	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
1127	1128	gptp->tim->CR1 = STM32_TIM_CR1_OPM \| STM32_TIM_CR1_URS \| STM32_TIM_CR1_CEN;
1128	1129	while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
1129	1130	;
1130		- gptp->tim->SR = 0; /* Clear pending IRQs. */
	1131	+ gptp->tim->SR = 0U; /* Clear pending IRQs. */
1131	1132	}
1132	1133
1133	1134	/**

--- trunk/readme.txt (revision 15841)

+++ trunk/readme.txt (revision 15842)

		@@ -130,6 +130,8 @@
130	130	- NEW: Increased stacks size in RT test suite from 128 to 192. added an
131	131	option to override the stack size by defining THREADS_STACK_SIZE
132	132	in the makefile.
	133	+- FIX: Fixed problem in STM32 gpt_lld_polled_delay() implementation (bug #1241)
	134	+ (backported to 20.3.5)(backported to 21.11.3).
133	135	- FIX: Fixed invalid delay loop in STM32G0/WL ADCv5 driver (bug #1240)
134	136	(backported to 20.3.5)(backported to 21.11.3).
135	137	- FIX: Fixed STM32_MCOSEL setting problem (bug #1239)(*********TODO********* backported to 21.11.3).

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