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Commit MetaInfo

修订版1896 (tree)
时间2010-04-30 00:57:42
作者lbednarz

Log Message

ready for merge

更改概述

差异

--- branches/coldfire_dev/boards/GENERIC_MCF5206e/board.c (revision 1895)
+++ branches/coldfire_dev/boards/GENERIC_MCF5206e/board.c (revision 1896)
@@ -1,6 +1,6 @@
11
2-#include <ch.h>
3-#include <hal.h>
2+#include "ch.h"
3+#include "hal.h"
44
55 #include "board.h"
66
@@ -15,6 +15,7 @@
1515 chSysUnlockFromIsr();
1616
1717 sim->timer.TER1 |= mcf5206e_TIMER_TER_REF;
18+
1819 CH_IRQ_EPILOGUE();
1920 }
2021
@@ -31,12 +32,12 @@
3132 /*
3233 * PAL initialization.
3334 */
34-// palClearPad(IOPORT1, PIO_LED);
35- palSetPad(IOPORT1, PIO_LED);
36- palSetPadMode(IOPORT1, PIO_LED, PAL_MODE_OUTPUT_PUSHPULL);
35+// palClearPad(IOPORT1, GPIO_LED);
36+ palSetPad(IOPORT1, GPIO_LED);
37+ palSetPadMode(IOPORT1, GPIO_LED, PAL_MODE_OUTPUT_PUSHPULL);
3738
3839 /*
39- * Disable interrupts.
40+ * Disable interrupts from SIM.
4041 */
4142 sim->sim.IMR = 0xFFFF;
4243
@@ -44,21 +45,21 @@
4445 * Timer 1 setup.
4546 */
4647 sim->timer.TMR1 = 0; // disable timer
47- *(volatile uint32_t *)0x30000074 = (uint32_t)SYSIrqHandler;
48- sim->sim.ICR9 = mcf5206e_SIM_ICR_AVEC|
49- mcf5206e_SIM_ICR_IL(5)|
50- mcf5206e_SIM_ICR_IP(3);
48+ *(volatile uint32_t *)(VBR+0x74) = (uint32_t)SYSIrqHandler;
49+ sim->sim.ICR9 = mcf5206e_SIM_ICR_AVEC|
50+ mcf5206e_SIM_ICR_IL(5)|
51+ mcf5206e_SIM_ICR_IP(3);
5152
52- sim->timer.TCN1 = 0;
53- sim->timer.TRR1 = 200000L/CH_FREQUENCY; // period = 200 / 200000 = 0.001s
54- sim->timer.TER1 = 0xFF;
55- sim->timer.TMR1 = mcf5206e_TIMER_TMR_PS(250-1)| // prescaler: 50MHz/250=200kHz
56- mcf5206e_TIMER_TMR_CE_NONE| // disable interrupt on capture event
57- mcf5206e_TIMER_TMR_ORI| // enable interrupt upon reaching the reference value (trr)
58- mcf5206e_TIMER_TMR_FRR| // timer count is reset immediately after reaching the reference value
59- mcf5206e_TIMER_TMR_CLK_MSCLK| // input clock source is F_CPU
60- mcf5206e_TIMER_TMR_RST; // enable timer
61- sim->sim.IMR &= ~mcf5206e_SIM_IMR_T1; // enable timer interrupt
53+ sim->timer.TCN1 = 0;
54+ sim->timer.TRR1 = 200000L/CH_FREQUENCY; // period = 200 / 200000 = 0.001s
55+ sim->timer.TER1 = 0xFF;
56+ sim->timer.TMR1 = mcf5206e_TIMER_TMR_PS(250-1)| // prescaler: 50MHz/250=200kHz
57+ mcf5206e_TIMER_TMR_CE_NONE| // disable interrupt on capture event
58+ mcf5206e_TIMER_TMR_ORI| // enable interrupt upon reaching the reference value (trr)
59+ mcf5206e_TIMER_TMR_FRR| // timer count is reset immediately after reaching the reference value
60+ mcf5206e_TIMER_TMR_CLK_MSCLK| // input clock source is F_CPU
61+ mcf5206e_TIMER_TMR_RST; // enable timer
62+ sim->sim.IMR &= ~mcf5206e_SIM_IMR_T1; // enable timer interrupt
6263
6364 /*
6465 * Other initializations.
--- branches/coldfire_dev/boards/GENERIC_MCF5206e/board.h (revision 1895)
+++ branches/coldfire_dev/boards/GENERIC_MCF5206e/board.h (revision 1896)
@@ -31,26 +31,27 @@
3131
3232 #define BOARD_MY_COLDFIRE
3333
34-#define MBAR 0x10000000
34+#define MBAR 0x10000000
35+#define VBR 0x30000000
3536
36-#define _BV(x) (1<<x)
37+#define _BV(x) (1<<x)
3738
38-#define bitLED 0
39+//#define bitLED 0
3940
40-#define LEDOn() sim->pp.PPDAT &= ~_BV(bitLED)
41-#define LEDOff() sim->pp.PPDAT |= _BV(bitLED)
41+//#define LEDOn() sim->pp.PPDAT &= ~_BV(bitLED)
42+//#define LEDOff() sim->pp.PPDAT |= _BV(bitLED)
4243
4344 /*
4445 * Initial I/O setup.
4546 */
46-#define VAL_PIO_OUT 0x00 /* Output data. */
47-#define VAL_PIO_DIR 0x01 /* Direction. */
47+#define VAL_GPIO_OUT 0x00 /* Output data. */
48+#define VAL_GPIO_DIR 0x01 /* Direction. */
4849
4950 /*
5051 * I/O definitions.
5152 */
52-#define PIO_LED 0
53-#define PIO_LED_MASK (1<<PIO_LED)
53+#define GPIO_LED 0
54+#define GPIO_LED_MASK (1<<GPIO_LED)
5455
5556 extern volatile mcf5206e_IMM *sim;
5657
--- branches/coldfire_dev/demos/COLDFIRE-MCF5206e-GCC/main.c (revision 1895)
+++ branches/coldfire_dev/demos/COLDFIRE-MCF5206e-GCC/main.c (revision 1896)
@@ -12,13 +12,13 @@
1212 mcf5206e_UART_UMR1_PM_NONE|mcf5206e_UART_UMR1_BC_8
1313 };
1414
15-static WORKING_AREA(waThread1, 64);
16-static msg_t Thread1(void *arg) {
15+static WORKING_AREA(waBlinker, 64);
16+static msg_t blinker_thread(void *arg) {
1717
1818 while (TRUE) {
19- palClearPad(IOPORT1, PIO_LED);
19+ palClearPad(IOPORT1, GPIO_LED);
2020 chThdSleepMilliseconds(100);
21- palSetPad(IOPORT1, PIO_LED);
21+ palSetPad(IOPORT1, GPIO_LED);
2222 chThdSleepMilliseconds(900);
2323 }
2424 return 0;
@@ -36,7 +36,7 @@
3636 /*
3737 * Creates the blinker thread.
3838 */
39- chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
39+ chThdCreateStatic(waBlinker, sizeof(waBlinker), NORMALPRIO, blinker_thread, NULL);
4040
4141 /*
4242 * Normal main() thread activity.
@@ -45,19 +45,7 @@
4545 chThdSleepMilliseconds(1000);
4646 sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14);
4747 TestThread(&SD1);
48+ }
4849
49-
50-/*
51- switch (chFDDGetTimeout(&COM1, 500))
52- {
53- case '1':
54- chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14);
55- break;
56- case '2':
57- TestThread(&COM1);
58- break;
59- }
60-*/
61- }
6250 return 0;
6351 }
--- branches/coldfire_dev/demos/COLDFIRE-MCF5206e-GCC/mcuconf.h (revision 1895)
+++ branches/coldfire_dev/demos/COLDFIRE-MCF5206e-GCC/mcuconf.h (revision 1896)
@@ -46,10 +46,10 @@
4646 */
4747 #define USE_COLDFIRE_UART1 TRUE
4848 #define USE_COLDFIRE_UART2 FALSE
49-//#define MCF5206E_UART1_PRIORITY 1
50-//#define MCF5206E_UART2_PRIORITY 2
49+#define COLDFIRE_UART1_PRIORITY 2
50+#define COLDFIRE_UART2_PRIORITY 2
5151
5252 /*
5353 * SPI driver system settings.
5454 */
55-//#define USE_MCF5206E_SPI1 TRUE
55+//#define USE_COLDFIRE_SPI1 TRUE
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/hal_lld.c (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/hal_lld.c (revision 1896)
@@ -18,9 +18,9 @@
1818 */
1919
2020 /**
21- * @file templates/hal_lld.c
22- * @brief HAL Driver subsystem low level driver source template.
23- * @addtogroup HAL_LLD
21+ * @file COLDFIRE/hal_lld.c
22+ * @brief COLDFIRE HAL subsystem low level driver source template.
23+ * @addtogroup COLDFIRE_HAL
2424 * @{
2525 */
2626
@@ -39,9 +39,9 @@
3939 * @brief PAL setup.
4040 * @details Digital I/O ports static configuration as defined in @p board.h.
4141 */
42-const MCF5206ePIOConfig pal_default_config =
42+const MCF5206eGPIOConfig pal_default_config =
4343 {
44- {VAL_PIO_OUT, VAL_PIO_DIR},
44+ {VAL_GPIO_OUT, VAL_GPIO_DIR},
4545 };
4646
4747 /*===========================================================================*/
@@ -52,6 +52,15 @@
5252 /* Driver interrupt handlers. */
5353 /*===========================================================================*/
5454
55+CH_IRQ_HANDLER(SpuriousIrqHandler) {
56+
57+ CH_IRQ_PROLOGUE();
58+
59+ COLDFIRE_SPURIOUS_HANDLER_HOOK();
60+
61+ CH_IRQ_EPILOGUE();
62+}
63+
5564 /*===========================================================================*/
5665 /* Driver exported functions. */
5766 /*===========================================================================*/
@@ -61,6 +70,11 @@
6170 */
6271 void hal_lld_init(void) {
6372
73+ /*
74+ * Spurious interrupt setup
75+ */
76+ *(volatile uint32_t *)(VBR+0x60) = (uint32_t)SpuriousIrqHandler;
77+
6478 }
6579
6680 /** @} */
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/hal_lld.h (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/hal_lld.h (revision 1896)
@@ -18,9 +18,9 @@
1818 */
1919
2020 /**
21- * @file templates/hal_lld.h
22- * @brief HAL subsystem low level driver header template.
23- * @addtogroup HAL_LLD
21+ * @file COLDFIRE/hal_lld.h
22+ * @brief COLDFIRE HAL subsystem low level driver header.
23+ * @addtogroup COLDFIRE_HAL
2424 * @{
2525 */
2626
@@ -38,6 +38,13 @@
3838 /* Driver pre-compile time settings. */
3939 /*===========================================================================*/
4040
41+/**
42+ * @brief Default action for the spurious handler, nothing.
43+ */
44+#if !defined(COLDFIRE_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__)
45+#define COLDFIRE_SPURIOUS_HANDLER_HOOK()
46+#endif
47+
4148 /*===========================================================================*/
4249 /* Derived constants and error checks. */
4350 /*===========================================================================*/
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/pal_lld.c (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/pal_lld.c (revision 1896)
@@ -18,9 +18,9 @@
1818 */
1919
2020 /**
21- * @file templates/pal_lld.c
22- * @brief PAL subsystem low level driver template.
23- * @addtogroup PAL_LLD
21+ * @file COLDFIRE/pal_lld.c
22+ * @brief COLDFIRE GPIO low level driver template.
23+ * @addtogroup COLDFIRE_LLD
2424 * @{
2525 */
2626
@@ -50,12 +50,12 @@
5050 /*===========================================================================*/
5151
5252 /**
53- * @brief AT91SAM7 I/O ports configuration.
54- * @details PIO registers initialization.
53+ * @brief COLDFIRE GPIO ports configuration.
54+ * @details GPIO registers initialization.
5555 *
56- * @param[in] config the AT91SAM7 ports configuration
56+ * @param[in] config the COLDFIRE ports configuration
5757 */
58-void _pal_lld_init(const MCF5206ePIOConfig *config) {
58+void _pal_lld_init(const MCF5206eGPIOConfig *config) {
5959
6060 sim->pp.PPDDR = config->P0data.dir;
6161 sim->pp.PPDAT = config->P0data.out;
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/pal_lld.h (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/pal_lld.h (revision 1896)
@@ -18,9 +18,9 @@
1818 */
1919
2020 /**
21- * @file templates/pal_lld.h
22- * @brief PAL subsystem low level driver header template.
23- * @addtogroup PAL_LLD
21+ * @file COLDFIRE/pal_lld.h
22+ * @brief COLDFIRE GPIO low level driver header.
23+ * @addtogroup COLDFIRE_PAL
2424 * @{
2525 */
2626
@@ -44,12 +44,12 @@
4444 /*===========================================================================*/
4545
4646 /**
47- * @brief Setup registers common to all the Coldfire ports.
47+ * @brief MCF5206e setup registers.
4848 */
4949 typedef struct {
5050 uint8_t out;
5151 uint8_t dir;
52-} mcf5206e_pio_setup_t;
52+} mcf5206e_gpio_setup_t;
5353
5454 /**
5555 * @brief Generic I/O ports static initializer.
@@ -67,19 +67,19 @@
6767 * .
6868 */
6969 typedef struct {
70- mcf5206e_pio_setup_t P0data;
71-} MCF5206ePIOConfig;
70+ mcf5206e_gpio_setup_t P0data;
71+} MCF5206eGPIOConfig;
7272
7373 /**
7474 * @brief Width, in bits, of an I/O port.
7575 */
76-#define PAL_IOPORTS_WIDTH 16
76+#define PAL_IOPORTS_WIDTH 8
7777
7878 /**
7979 * @brief Whole port mask.
8080 * @brief This macro specifies all the valid bits into a port.
8181 */
82-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
82+#define PAL_WHOLE_PORT ((ioportmask_t)0xFF)
8383
8484 /**
8585 * @brief Digital I/O port sized unsigned type.
@@ -333,12 +333,12 @@
333333 */
334334 //#define pal_lld_setpadmode(port, pad, mode)
335335
336-extern const MCF5206ePIOConfig pal_default_config;
336+extern const MCF5206eGPIOConfig pal_default_config;
337337
338338 #ifdef __cplusplus
339339 extern "C" {
340340 #endif
341- void _pal_lld_init(const MCF5206ePIOConfig *config);
341+ void _pal_lld_init(const MCF5206eGPIOConfig *config);
342342 void _pal_lld_setgroupmode(ioportid_t port,
343343 ioportmask_t mask,
344344 uint_fast8_t mode);
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/serial_lld.c (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/serial_lld.c (revision 1896)
@@ -25,7 +25,7 @@
2525 */
2626
2727 /**
28- * @file ColdFire/coldfire_serial.c
28+ * @file COLDFIRE/coldfire_serial.c
2929 * @brief ColdFire low level serial driver code.
3030 * @addtogroup COLDFIRE_SERIAL
3131 * @{
@@ -102,15 +102,16 @@
102102 sdp->uart1->UIR = mcf5206e_UART_UIMR_FFULL;
103103
104104 sdp->uart1->UIR = mcf5206e_UART_UIMR_FFULL;
105- *(volatile uint32_t *)0x30000078 = (uint32_t)UART1IrqHandler;
105+ *(volatile uint32_t *)(VBR+0x78) = (uint32_t)UART1IrqHandler;
106106 sim->sim.ICR12 = mcf5206e_SIM_ICR_AVEC|
107107 mcf5206e_SIM_ICR_IL(6)|
108- mcf5206e_SIM_ICR_IP(2);
108+ mcf5206e_SIM_ICR_IP(COLDFIRE_UART1_PRIORITY);
109109 sim->sim.IMR &= ~mcf5206e_SIM_IMR_UART1;
110110 }
111111 #endif
112112
113113 #if USE_COLDFIRE_UART2 || defined(__DOXYGEN__)
114+#error CODE NOT TESTED
114115 if (sdp == &SD2)
115116 {
116117 sdp->uart2->UCR = mcf5206e_UART_UCR_RESET_TX;
@@ -124,10 +125,10 @@
124125 sdp->uart2->UIR = mcf5206e_UART_UIMR_FFULL;
125126
126127 sdp->uart2->UIR = mcf5206e_UART_UIMR_FFULL;
127-// *(volatile uint32_t *)0x30000078 = (uint32_t)UART2IrqHandler;
128-// sim->sim.ICR12 = mcf5206e_SIM_ICR_AVEC|
129-// mcf5206e_SIM_ICR_IL(6)|
130-// mcf5206e_SIM_ICR_IP(2);
128+// *(volatile uint32_t *)(VBR+0x70) = (uint32_t)UART2IrqHandler;
129+// sim->sim.ICR13 = mcf5206e_SIM_ICR_AVEC|
130+// mcf5206e_SIM_ICR_IL(4)|
131+// mcf5206e_SIM_ICR_IP(COLDFIRE_UART1_PRIORITY);
131132 // sim->sim.IMR &= ~mcf5206e_SIM_IMR_UART2;
132133 }
133134 #endif
@@ -208,32 +209,32 @@
208209 */
209210 void serve_interrupt1(SerialDriver *sdp)
210211 {
211- uint8_t usr = sdp->uart1->USR;
212+ uint8_t usr = sdp->uart1->USR;
212213
213-// TODO: test it
214- if (usr & (mcf5206e_UART_USR_RB | mcf5206e_UART_USR_FE | mcf5206e_UART_USR_PE | mcf5206e_UART_USR_OE)) {
215- set_error(sdp, usr);
214+// TODO: test it
215+ if (usr & (mcf5206e_UART_USR_RB | mcf5206e_UART_USR_FE | mcf5206e_UART_USR_PE | mcf5206e_UART_USR_OE)) {
216+ set_error(sdp, usr);
217+ }
218+ if (usr & mcf5206e_UART_USR_RXRDY)
219+ {
220+ chSysLockFromIsr();
221+ sdIncomingDataI(sdp, (uint8_t)sdp->uart1->UBUF);
222+ chSysUnlockFromIsr();
223+ }
224+ if (usr & mcf5206e_UART_USR_TXRDY)
225+ {
226+ msg_t b;
227+
228+ chSysLockFromIsr();
229+ b = chOQGetI(&sdp->oqueue);
230+ if (b < Q_OK) {
231+ chEvtBroadcastI(&sdp->oevent);
232+ sdp->uart1->UIR = mcf5206e_UART_UIMR_FFULL;
216233 }
217- if (usr & mcf5206e_UART_USR_RXRDY)
218- {
219- chSysLockFromIsr();
220- sdIncomingDataI(sdp, (uint8_t)sdp->uart1->UBUF);
221- chSysUnlockFromIsr();
222- }
223- if (usr & mcf5206e_UART_USR_TXRDY)
224- {
225- msg_t b;
226-
227- chSysLockFromIsr();
228- b = chOQGetI(&sdp->oqueue);
229- if (b < Q_OK) {
230- chEvtBroadcastI(&sdp->oevent);
231- sdp->uart1->UIR = mcf5206e_UART_UIMR_FFULL;
232- }
233- else
234- sdp->uart1->UBUF = b;
235- chSysUnlockFromIsr();
236- }
234+ else
235+ sdp->uart1->UBUF = b;
236+ chSysUnlockFromIsr();
237+ }
237238 }
238239
239240 /**
@@ -243,34 +244,34 @@
243244 */
244245 void serve_interrupt2(SerialDriver *sdp)
245246 {
246- uint8_t usr = sdp->uart2->USR;
247+ uint8_t usr = sdp->uart2->USR;
247248
248249 /*
249250 TODO: test it
250251 if (usr & (mcf5206e_UART_USR_RB | mcf5206e_UART_USR_FE | mcf5206e_UART_USR_PE | mcf5206e_UART_USR_OE)) {
251- SetError(usr, com);
252+ set_error(sdp, usr);
252253 }
253254 */
254- if (usr & mcf5206e_UART_USR_RXRDY)
255- {
256- chSysLockFromIsr();
257- sdIncomingDataI(sdp, (uint8_t)sdp->uart2->UBUF);
258- chSysUnlockFromIsr();
259- }
260- if (usr & mcf5206e_UART_USR_TXRDY)
261- {
262- msg_t b;
255+ if (usr & mcf5206e_UART_USR_RXRDY)
256+ {
257+ chSysLockFromIsr();
258+ sdIncomingDataI(sdp, (uint8_t)sdp->uart2->UBUF);
259+ chSysUnlockFromIsr();
260+ }
261+ if (usr & mcf5206e_UART_USR_TXRDY)
262+ {
263+ msg_t b;
263264
264- chSysLockFromIsr();
265- b = chOQGetI(&sdp->oqueue);
266- if (b < Q_OK) {
267- chEvtBroadcastI(&sdp->oevent);
268- sdp->uart2->UIR = mcf5206e_UART_UIMR_FFULL;
269- }
270- else
271- sdp->uart2->UBUF = b;
272- chSysUnlockFromIsr();
273- }
265+ chSysLockFromIsr();
266+ b = chOQGetI(&sdp->oqueue);
267+ if (b < Q_OK) {
268+ chEvtBroadcastI(&sdp->oevent);
269+ sdp->uart2->UIR = mcf5206e_UART_UIMR_FFULL;
270+ }
271+ else
272+ sdp->uart2->UBUF = b;
273+ chSysUnlockFromIsr();
274+ }
274275 }
275276
276277 /*===========================================================================*/
@@ -332,43 +333,6 @@
332333 if (sdp->state == SD_STOP) {
333334 uart_init(sdp);
334335 }
335-/*
336- if (sdp->state == SD_STOP) {
337-#if USE_STM32_USART1
338- if (&SD1 == sdp) {
339- RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
340- NVICEnableVector(USART1_IRQn, STM32_USART1_PRIORITY);
341- }
342-#endif
343-#if USE_STM32_USART2
344- if (&SD2 == sdp) {
345- RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
346- NVICEnableVector(USART2_IRQn, STM32_USART2_PRIORITY);
347- }
348-#endif
349-#if USE_STM32_USART3
350- if (&SD3 == sdp) {
351- RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
352- NVICEnableVector(USART3_IRQn, STM32_USART3_PRIORITY);
353- }
354-#endif
355-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
356-#if USE_STM32_UART4
357- if (&SD4 == sdp) {
358- RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
359- NVICEnableVector(UART4_IRQn, STM32_UART4_PRIORITY);
360- }
361-#endif
362-#if USE_STM32_UART5
363- if (&SD5 == sdp) {
364- RCC->APB1ENR |= RCC_APB1ENR_UART5EN;
365- NVICEnableVector(UART5_IRQn, STM32_UART5_PRIORITY);
366- }
367-#endif
368-#endif
369- }
370-*/
371-// uart_init(sdp);
372336 }
373337
374338 /**
@@ -382,22 +346,6 @@
382346
383347 if (sdp->state == SD_READY) {
384348 uart_deinit(sdp);
385-/*
386-#if USE_STM32_USART1
387- if (&SD1 == sdp) {
388- RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
389- NVICDisableVector(USART1_IRQn);
390- return;
391- }
392-#endif
393-#if USE_STM32_USART2
394- if (&SD2 == sdp) {
395- RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
396- NVICDisableVector(USART2_IRQn);
397- return;
398- }
399-#endif
400-*/
401349 }
402350 }
403351
@@ -404,155 +352,3 @@
404352 #endif /* CH_HAL_USE_SERIAL */
405353
406354 /** @} */
407-
408-
409-
410-
411-
412-
413-
414-
415-
416-
417-
418-
419-
420-
421-#if 0
422-#include <ch.h>
423-#include <signal.h>
424-
425-#include "board.h"
426-//#include "coldfire_serial.h"
427-#include "mcf5206e.h"
428-
429-//static void SetError(uint8_t usr, FullDuplexDriver *com) {
430-/*
431- TODO: test it
432- dflags_t sts = 0;
433-
434- if (usr & mcf5206e_UART_USR_OE)
435- sts |= SD_OVERRUN_ERROR;
436- if (usr & mcf5206e_UART_USR_PE)
437- sts |= SD_PARITY_ERROR;
438- if (usr & mcf5206e_UART_USR_FE)
439- sts |= SD_FRAMING_ERROR;
440- if (usr & mcf5206e_UART_USR_RB)
441- sts |= SD_BREAK_DETECTED;
442- chSysLockFromIsr();
443- chFDDAddFlagsI(com, sts);
444- chSysUnlockFromIsr();
445-*/
446-//}
447-
448-#if USE_COLDFIRE_USART0 || defined(__DOXYGEN__)
449-
450-/** @brief USART0 serial driver identifier.*/
451-FullDuplexDriver COM1;
452-
453-static uint8_t ib1[SERIAL_BUFFERS_SIZE];
454-static uint8_t ob1[SERIAL_BUFFERS_SIZE];
455-
456-
457-void ServeInterrupt(mcf5206e_UART1 *u, FullDuplexDriver *com)
458-{
459- uint8_t usr = u->USR;
460-
461-/*
462- TODO: test it
463- if (usr & (mcf5206e_UART_USR_RB | mcf5206e_UART_USR_FE | mcf5206e_UART_USR_PE | mcf5206e_UART_USR_OE)) {
464- SetError(usr, com);
465- }
466-*/
467- if (usr & mcf5206e_UART_USR_RXRDY)
468- {
469- chSysLockFromIsr();
470- chFDDIncomingDataI(com, u->UBUF);
471- chSysUnlockFromIsr();
472- }
473- if (usr & mcf5206e_UART_USR_TXRDY)
474- {
475- chSysLockFromIsr();
476- msg_t b = chFDDRequestDataI(com);
477- chSysUnlockFromIsr();
478- if (b < Q_OK) {
479- u->UIR = mcf5206e_UART_UIMR_FFULL;
480- } else {
481- u->UBUF = b;
482- }
483- }
484-}
485-
486-
487-CH_IRQ_HANDLER(UARTIrqHandler) {
488-
489- CH_IRQ_PROLOGUE();
490-
491- ServeInterrupt((mcf5206e_UART1 *)&sim->uart1, &COM1);
492-
493- CH_IRQ_EPILOGUE();
494-}
495-
496-
497-static void OutNotify1(void) {
498-
499- sim->uart1.UIR = mcf5206e_UART_UIMR_FFULL | mcf5206e_UART_UIMR_TXRDY;
500-}
501-
502-/**
503- * @brief USART0 setup.
504- * @details This function must be invoked with interrupts disabled.
505- * @param div The divider value as calculated by the @p UBR() macro.
506- * @param mod The value for the @p U0MCTL register.
507- * @param ctl The value for the @p U0CTL register.
508- * @note Does not reset the I/O queues.
509- */
510-void usart0_setup(uint32_t baud) {
511- uint32_t b;
512-
513- b = F_CPU*10/32L;
514- if (baud)
515- b /= baud;
516- if ((b % 10) >= 5)
517- b += 10;
518-
519- sim->uart1.UCR = mcf5206e_UART_UCR_RESET_TX;
520- sim->uart1.UCR = mcf5206e_UART_UCR_RESET_RX;
521- sim->uart1.UCR = mcf5206e_UART_UCR_RESET_MR;
522- sim->uart1.UBG1 = (b/10)>>8;
523- sim->uart1.UBG2 = (b/10)&0xFF;
524- sim->uart1.USR = mcf5206e_UART_UCSR_RX_TIMER|mcf5206e_UART_UCSR_TX_TIMER;
525- sim->uart1.UMR = mcf5206e_UART_UMR1_PM_NONE|mcf5206e_UART_UMR1_BC_8;
526- sim->uart1.UCR = mcf5206e_UART_UCR_TX_ENABLED|mcf5206e_UART_UCR_RX_ENABLED;
527- sim->uart1.UIR = mcf5206e_UART_UIMR_FFULL;
528-
529- sim->uart1.UIR = mcf5206e_UART_UIMR_FFULL;
530- *(volatile uint32_t *)0x78 = (uint32_t)UARTIrqHandler;
531- sim->sim.ICR12 = mcf5206e_SIM_ICR_AVEC|
532- mcf5206e_SIM_ICR_IL(6)|
533- mcf5206e_SIM_ICR_IP(2);
534- sim->sim.IMR &= ~mcf5206e_SIM_IMR_UART1;
535-}
536-#endif /* USE_COLDFIRE_USART0 */
537-
538-#if USE_COLDFIRE_USART1 || defined(__DOXYGEN__)
539-#endif
540-
541-/**
542- * @brief Serial driver initialization.
543- * @note The serial ports are initialized at @p 57600-8-N-1 by default.
544- */
545-void serial_init(void) {
546-
547- /* I/O queues setup.*/
548-#if USE_COLDFIRE_USART0
549- chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
550- usart0_setup(DEFAULT_USART_BITRATE);
551-#endif
552-
553-#if USE_COLDFIRE_USART1
554-#endif
555-}
556-
557-/** @} */
558-#endif
--- branches/coldfire_dev/os/hal/platforms/MCF5206e/serial_lld.h (revision 1895)
+++ branches/coldfire_dev/os/hal/platforms/MCF5206e/serial_lld.h (revision 1896)
@@ -25,7 +25,7 @@
2525 */
2626
2727 /**
28- * @file ColdFire/serial_lld.h
28+ * @file COLDFIRE/serial_lld.h
2929 * @brief COLDFIRE low level serial driver header.
3030 * @addtogroup COLDFIRE_SERIAL
3131 * @{
@@ -82,7 +82,7 @@
8282 */
8383 typedef struct {
8484 /**
85- * @brief Initialization value for the UBG register.
85+ * @brief Bit rate.
8686 */
8787 uint32_t sc_speed;
8888 /**
@@ -97,6 +97,7 @@
9797
9898 /**
9999 * @brief @p SerialDriver specific data.
100+ * @note Structure mcf5206e_UART1 differs from mcf5206e_UART2 !!!.
100101 */
101102 #define _serial_driver_data \
102103 _base_asynchronous_channel_data \
@@ -117,7 +118,7 @@
117118 /* Output circular buffer.*/ \
118119 uint8_t ob[SERIAL_BUFFERS_SIZE]; \
119120 /* End of the mandatory fields.*/ \
120- /* Pointer to the USART registers block.*/ \
121+ /* Pointers to the UART registers blocks.*/ \
121122 mcf5206e_UART1 *uart1; \
122123 mcf5206e_UART2 *uart2;
123124
@@ -137,7 +138,6 @@
137138 #if USE_COLDFIRE_UART2
138139 extern SerialDriver SD2;
139140 #endif
140-#endif
141141
142142 #ifdef __cplusplus
143143 extern "C" {
@@ -150,6 +150,8 @@
150150 #endif
151151 /** @endcond*/
152152
153+#endif /* CH_HAL_USE_SERIAL */
154+
153155 #endif /* _SERIAL_LLD_H_ */
154156
155157 /** @} */
--- branches/coldfire_dev/os/ports/GCC/CF/chcore.h (revision 1895)
+++ branches/coldfire_dev/os/ports/GCC/CF/chcore.h (revision 1896)
@@ -56,6 +56,7 @@
5656 * @brief Interrupt saved context.
5757 * @details This structure represents the stack frame saved during a
5858 * preemption-capable interrupt handler.
59+ * @note Checked for O2 and Os optimizations only.
5960 */
6061 struct extctx {
6162 uint32_t d0;
@@ -102,6 +103,7 @@
102103 * @brief Platform dependent part of the @p chThdInit() API.
103104 * @details This code usually setup the context switching frame represented
104105 * by an @p intctx structure.
106+ * @note Initial values for registers d2-d7 and a3-a4 are for test purposes only.
105107 */
106108 #define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
107109 tp->p_ctx.sp = (struct intctx *)((uint8_t *)workspace + \
--- branches/coldfire_dev/os/ports/GCC/CF/crt0.s (revision 1895)
+++ branches/coldfire_dev/os/ports/GCC/CF/crt0.s (revision 1896)
@@ -20,12 +20,12 @@
2020 */
2121 movel #__ram_end__, %a7
2222
23-
23+/* enable cache */
2424 movel #0x01000000, %d0
2525 movec %d0, %CACR
2626 movel #0x80000100, %d0
2727 movec %d0, %CACR
28-
28+/* init bss section */
2929 movel #__bss_start,%d1
3030 movel #__bss_end, %d0
3131 cmpl %d0, %d1
@@ -36,7 +36,7 @@
3636 1: clrb (%a0)+
3737 subql #1, %d0
3838 bpl 1b
39-
39+/* init data section */
4040 2: lea _etext,%a1
4141 lea _data,%a0
4242 cmpl %a0,%a1
@@ -49,7 +49,7 @@
4949 cmpl %d0,%a0
5050 bcs.s COPYLOOP
5151 NOCOPY:
52-
52+/* init hardware */
5353 jsr hwinit
5454
5555 /*
@@ -56,6 +56,7 @@
5656 TODO: Insert ctors init here.
5757 */
5858
59+/* enable global interrupts */
5960 move #0x2000, %sr
6061 jsr main
6162 rts
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