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项目描述

Confluence is a functional programming language for reactive system design, including FPGAs, ASICs, and hard-real-time software. Confluence system descriptions have a large information to linecount ratio. It is typically two to five times more compact than Verilog. Confluence can compile a single body of source code into to Verilog, VHDL, C, and NuSMV.

系统要求

System requirement is not defined
Information regarding Project Releases and Project Resources. Note that the information here is a quote from Freecode.com page, and the downloads themselves may not be hosted on OSDN.

2005-02-18 05:43
0.10.3

此版本包括最初的股骨颈骨折C型发生器,可实现从汇流编译路径C.新功能包括一个新的模拟器的数据结构,从而能够同时运行多个仿真模型,并提供对所有层次名为设计的信号。这版本也包括了伊卡洛斯的Verilog股骨颈骨折发电机,提供从到C的Verilog,VHDL语言,NuSMV和JHDL路径。
标签: Major feature enhancements
This release includes the initial FNF C model generator that
enables a compilation path from Confluence to C. New
features include a new simulator data structure, which
enables
running multiple simulation models at once, and provides
access to all hierarchical named signals in a design.
This release also includes the Icarus Verilog FNF
generator, providing a path from Verilog to C, VHDL, NuSMV,
and JHDL.

2005-02-02 05:41
0.10.2

增加了一个新的代码生成器,允许其进入JHDL,基于Java的编译硬件描述语言。
标签: Major feature enhancements
Adds a new code generator that allows it to compile into JHDL, a Java-based hardware description language.

2005-01-09 10:57
0.10.0

在此版本中,编译器后端的集成股骨颈骨折,形成语言之间的评估和模型生成一个干净的分区。
标签: Major feature enhancements
In this release, the compiler backend was integrated with
FNF, forming a clean partition between language evaluation
and model generation.

Project Resources