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项目描述

Qucs is a circuit simulator with a graphical user

  1. It aims to support all kinds of

circuit simulation types, including DC, AC, S-parameter, and harmonic balance analysis.

系统要求

System requirement is not defined
Information regarding Project Releases and Project Resources. Note that the information here is a quote from Freecode.com page, and the downloads themselves may not be hosted on OSDN.

2011-03-19 05:28
0.0.16

此版本带有一个交互式的GNU /倍频程接口。语法为倍频程,的Verilog - HDL和Verilog - A的语法高亮显示已添加。预编译的VHDL模块和用户编写VHDL代码制成的支持现在库。有几个新的元件,如晶体管模型NIGBT,HICUM二级v2.24,HICUM L0的v1.2g和HICUM L0的1.3版,隧道二极管,理想的耦合传输线和一个理想的混合。现在的方程求解器具有EMI接收器功能实施。命令行的qucsconv Matlab的V4的数据转换器支持的文件格式作为出口。
This release comes with an interactive GNU/Octave interface. Syntax highlighting for Octave, Verilog-HDL, and Verilog-A syntax has been added. Pre-compiled VHDL modules and libraries made from user-written VHDL code are supported now. There are several new components, such as transistor models NIGBT, HICUM L2 v2.24, HICUM L0 v1.2g and HICUM L0 v1.3, tunnel diode, ideal coupled transmission line, and an ideal hybrid. The equation solver now has EMI receiver functionality implemented. The qucsconv command line data converter supports Matlab v4 as an export file format.

2009-04-26 05:13
0.0.15

此版本带有成阿拉伯文和捷克,为MOSFET的稳压器,压敏电阻模型库,以及理想成分的新译本,以及许多新的洛桑联邦理工学院等原始组件EKV NMOS管/ PMOS的2.6版本,HICUM L0 1.2版,和众多的数字基元。传递参数的Verilog - HDL和VHDL子电路和输入VHDL的文件的一般参数现在支持以及任意输入/输出信号英寸在Qucs转换器工具现在可让您翻译成库元素现有HICUM模型以及多项式C和L的和F,魔法,英,法和G多项式的SPICE来源的翻译。
标签: Major feature enhancements, Bugfixes
This release comes with new translations into Arabic and Czech, model libraries for MOSFETs regulators, varistors, and ideal components, and many new primitive components such as EPFL-EKV NMOS/PMOS V2.6, HICUM L0 v1.2, and numerous digital primitives. Passing parameters to Verilog-HDL and VHDL subcircuits and typed generic parameters of VHDL files are now supported as well as arbitrary in/out signals. The Qucs-Converter tool now allows you to translate existing HICUM models into library elements as well as the translation of polynomial C's and L's and F, H, E, and G polynomial SPICE sources.

2008-04-10 22:37
0.0.14

此版本带有一些新的部件,即DIAC的,可控硅,晶闸管,对数放大器,HICUM L0 1.12,电位器,射频设备定义方程,场效应晶体管(Curtice,Statz的TOM - 1,和TOM - 2)。在Qucs - Transcalc工具还包含合成及共面线类型分析。在Win32环境下印刷终于被修复。支持次区域和超文本中的图形画剧本已添加。最后但并非最不重要的PlotVs版本()与3个或多个参数已被添加到方程求解器的能力。
标签: Minor feature enhancements
This release comes with a few new components, i.e., diac, triac, thyristor, logarithmic amplifier, HICUM L0 v1.12, potentiometer, equation defined RF device, and MESFET (Curtice, Statz, TOM-1, and TOM-2). The Qucs-Transcalc tool also contains synthesis and analysis of coplanar line types. Printing under Win32 has finally been fixed. Support for sub- and super-script in graphical text paintings has been added. Last but not least, versions of PlotVs() with 3 or more arguments have been added to the equation solver capabilities.

2007-12-30 18:24
0.0.13

此版本来了,即基于文件的电流和电压源,一些新的组件模块化运算放大器,以及HICUM二级v2.22设备模型。在方程组,立即向量和矩阵允许以及工程的数字符号,以及更强大的功能已被添加(随机,srandom,StabFactor和StabMeasure)。 Touchstone文件可以出口和CSV文件可以导入使用命令行数据转换器QucsConv。
标签: Minor feature enhancements
This release comes with some new components, i.e. file-based current and voltage sources, a modular operational amplifier, and the HICUM L2 v2.22 device model. In equations, immediate vectors and matrices are allowed as well as engineering notation of numbers, and some more functions have been added (random, srandom, StabFactor, and StabMeasure). Touchstone files can be exported and CSV files can be imported using the command line data converter QucsConv.

2007-06-17 16:28
0.0.12

此版本带有一个翻译成乌克兰,在SPICE组件选择预处理,和两个新的组件(指数电压和电流源)。图书馆现在可以包含模拟和数字子电路。模拟模型是大大加强了象征性的定义设备。在方程求解器可用功能列表已经扩展以支持更多的功能,逻辑和理性的经营者,三元?:建立。纯数字模拟也可以用Verilog进行,作为替代的VHDL的高密度脂蛋白。
标签: Major feature enhancements
This release comes with a translation into Ukrainian, a selectable preprocessor in the SPICE component, and two new components (exponential voltage and current source). Libraries can now contain analogue as well as digital subcircuits. Analogue modelling is substantially strengthened by symbolically defined devices. The list of available functions in the equation solver has been extended to support more functions, logical and rational operators, and the ternary ?: construct. Pure digital simulations can be also performed by Verilog-HDL as an alternative to VHDL.

Project Resources