Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/
修订版 | 49846ecd134b04295d86d70abbac1f489a31a94c (tree) |
---|---|
时间 | 2020-02-15 06:30:01 |
作者 | Alexandre Belloni <alexandre.belloni@boot...> |
Commiter | Greg Kroah-Hartman |
ARM: dts: at91: sama5d3: fix maximum peripheral clock rates
commit ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da upstream.
Currently the maximum rate for peripheral clock is calculated based on a
typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
device trees to match the maximum rate based on 166MHz.
Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks")
Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@@ -1106,49 +1106,49 @@ | ||
1106 | 1106 | usart0_clk: usart0_clk { |
1107 | 1107 | #clock-cells = <0>; |
1108 | 1108 | reg = <12>; |
1109 | - atmel,clk-output-range = <0 66000000>; | |
1109 | + atmel,clk-output-range = <0 83000000>; | |
1110 | 1110 | }; |
1111 | 1111 | |
1112 | 1112 | usart1_clk: usart1_clk { |
1113 | 1113 | #clock-cells = <0>; |
1114 | 1114 | reg = <13>; |
1115 | - atmel,clk-output-range = <0 66000000>; | |
1115 | + atmel,clk-output-range = <0 83000000>; | |
1116 | 1116 | }; |
1117 | 1117 | |
1118 | 1118 | usart2_clk: usart2_clk { |
1119 | 1119 | #clock-cells = <0>; |
1120 | 1120 | reg = <14>; |
1121 | - atmel,clk-output-range = <0 66000000>; | |
1121 | + atmel,clk-output-range = <0 83000000>; | |
1122 | 1122 | }; |
1123 | 1123 | |
1124 | 1124 | usart3_clk: usart3_clk { |
1125 | 1125 | #clock-cells = <0>; |
1126 | 1126 | reg = <15>; |
1127 | - atmel,clk-output-range = <0 66000000>; | |
1127 | + atmel,clk-output-range = <0 83000000>; | |
1128 | 1128 | }; |
1129 | 1129 | |
1130 | 1130 | uart0_clk: uart0_clk { |
1131 | 1131 | #clock-cells = <0>; |
1132 | 1132 | reg = <16>; |
1133 | - atmel,clk-output-range = <0 66000000>; | |
1133 | + atmel,clk-output-range = <0 83000000>; | |
1134 | 1134 | }; |
1135 | 1135 | |
1136 | 1136 | twi0_clk: twi0_clk { |
1137 | 1137 | reg = <18>; |
1138 | 1138 | #clock-cells = <0>; |
1139 | - atmel,clk-output-range = <0 16625000>; | |
1139 | + atmel,clk-output-range = <0 41500000>; | |
1140 | 1140 | }; |
1141 | 1141 | |
1142 | 1142 | twi1_clk: twi1_clk { |
1143 | 1143 | #clock-cells = <0>; |
1144 | 1144 | reg = <19>; |
1145 | - atmel,clk-output-range = <0 16625000>; | |
1145 | + atmel,clk-output-range = <0 41500000>; | |
1146 | 1146 | }; |
1147 | 1147 | |
1148 | 1148 | twi2_clk: twi2_clk { |
1149 | 1149 | #clock-cells = <0>; |
1150 | 1150 | reg = <20>; |
1151 | - atmel,clk-output-range = <0 16625000>; | |
1151 | + atmel,clk-output-range = <0 41500000>; | |
1152 | 1152 | }; |
1153 | 1153 | |
1154 | 1154 | mci0_clk: mci0_clk { |
@@ -1164,19 +1164,19 @@ | ||
1164 | 1164 | spi0_clk: spi0_clk { |
1165 | 1165 | #clock-cells = <0>; |
1166 | 1166 | reg = <24>; |
1167 | - atmel,clk-output-range = <0 133000000>; | |
1167 | + atmel,clk-output-range = <0 166000000>; | |
1168 | 1168 | }; |
1169 | 1169 | |
1170 | 1170 | spi1_clk: spi1_clk { |
1171 | 1171 | #clock-cells = <0>; |
1172 | 1172 | reg = <25>; |
1173 | - atmel,clk-output-range = <0 133000000>; | |
1173 | + atmel,clk-output-range = <0 166000000>; | |
1174 | 1174 | }; |
1175 | 1175 | |
1176 | 1176 | tcb0_clk: tcb0_clk { |
1177 | 1177 | #clock-cells = <0>; |
1178 | 1178 | reg = <26>; |
1179 | - atmel,clk-output-range = <0 133000000>; | |
1179 | + atmel,clk-output-range = <0 166000000>; | |
1180 | 1180 | }; |
1181 | 1181 | |
1182 | 1182 | pwm_clk: pwm_clk { |
@@ -1187,7 +1187,7 @@ | ||
1187 | 1187 | adc_clk: adc_clk { |
1188 | 1188 | #clock-cells = <0>; |
1189 | 1189 | reg = <29>; |
1190 | - atmel,clk-output-range = <0 66000000>; | |
1190 | + atmel,clk-output-range = <0 83000000>; | |
1191 | 1191 | }; |
1192 | 1192 | |
1193 | 1193 | dma0_clk: dma0_clk { |
@@ -1218,13 +1218,13 @@ | ||
1218 | 1218 | ssc0_clk: ssc0_clk { |
1219 | 1219 | #clock-cells = <0>; |
1220 | 1220 | reg = <38>; |
1221 | - atmel,clk-output-range = <0 66000000>; | |
1221 | + atmel,clk-output-range = <0 83000000>; | |
1222 | 1222 | }; |
1223 | 1223 | |
1224 | 1224 | ssc1_clk: ssc1_clk { |
1225 | 1225 | #clock-cells = <0>; |
1226 | 1226 | reg = <39>; |
1227 | - atmel,clk-output-range = <0 66000000>; | |
1227 | + atmel,clk-output-range = <0 83000000>; | |
1228 | 1228 | }; |
1229 | 1229 | |
1230 | 1230 | sha_clk: sha_clk { |
@@ -37,13 +37,13 @@ | ||
37 | 37 | can0_clk: can0_clk { |
38 | 38 | #clock-cells = <0>; |
39 | 39 | reg = <40>; |
40 | - atmel,clk-output-range = <0 66000000>; | |
40 | + atmel,clk-output-range = <0 83000000>; | |
41 | 41 | }; |
42 | 42 | |
43 | 43 | can1_clk: can1_clk { |
44 | 44 | #clock-cells = <0>; |
45 | 45 | reg = <41>; |
46 | - atmel,clk-output-range = <0 66000000>; | |
46 | + atmel,clk-output-range = <0 83000000>; | |
47 | 47 | }; |
48 | 48 | }; |
49 | 49 | }; |
@@ -42,13 +42,13 @@ | ||
42 | 42 | uart0_clk: uart0_clk { |
43 | 43 | #clock-cells = <0>; |
44 | 44 | reg = <16>; |
45 | - atmel,clk-output-range = <0 66000000>; | |
45 | + atmel,clk-output-range = <0 83000000>; | |
46 | 46 | }; |
47 | 47 | |
48 | 48 | uart1_clk: uart1_clk { |
49 | 49 | #clock-cells = <0>; |
50 | 50 | reg = <17>; |
51 | - atmel,clk-output-range = <0 66000000>; | |
51 | + atmel,clk-output-range = <0 83000000>; | |
52 | 52 | }; |
53 | 53 | }; |
54 | 54 | }; |