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kernel_xiaomi_msm8998: 提交

Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/


Commit MetaInfo

修订版49846ecd134b04295d86d70abbac1f489a31a94c (tree)
时间2020-02-15 06:30:01
作者Alexandre Belloni <alexandre.belloni@boot...>
CommiterGreg Kroah-Hartman

Log Message

ARM: dts: at91: sama5d3: fix maximum peripheral clock rates

commit ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da upstream.

Currently the maximum rate for peripheral clock is calculated based on a
typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
device trees to match the maximum rate based on 166MHz.

Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks")
Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

更改概述

差异

--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1106,49 +1106,49 @@
11061106 usart0_clk: usart0_clk {
11071107 #clock-cells = <0>;
11081108 reg = <12>;
1109- atmel,clk-output-range = <0 66000000>;
1109+ atmel,clk-output-range = <0 83000000>;
11101110 };
11111111
11121112 usart1_clk: usart1_clk {
11131113 #clock-cells = <0>;
11141114 reg = <13>;
1115- atmel,clk-output-range = <0 66000000>;
1115+ atmel,clk-output-range = <0 83000000>;
11161116 };
11171117
11181118 usart2_clk: usart2_clk {
11191119 #clock-cells = <0>;
11201120 reg = <14>;
1121- atmel,clk-output-range = <0 66000000>;
1121+ atmel,clk-output-range = <0 83000000>;
11221122 };
11231123
11241124 usart3_clk: usart3_clk {
11251125 #clock-cells = <0>;
11261126 reg = <15>;
1127- atmel,clk-output-range = <0 66000000>;
1127+ atmel,clk-output-range = <0 83000000>;
11281128 };
11291129
11301130 uart0_clk: uart0_clk {
11311131 #clock-cells = <0>;
11321132 reg = <16>;
1133- atmel,clk-output-range = <0 66000000>;
1133+ atmel,clk-output-range = <0 83000000>;
11341134 };
11351135
11361136 twi0_clk: twi0_clk {
11371137 reg = <18>;
11381138 #clock-cells = <0>;
1139- atmel,clk-output-range = <0 16625000>;
1139+ atmel,clk-output-range = <0 41500000>;
11401140 };
11411141
11421142 twi1_clk: twi1_clk {
11431143 #clock-cells = <0>;
11441144 reg = <19>;
1145- atmel,clk-output-range = <0 16625000>;
1145+ atmel,clk-output-range = <0 41500000>;
11461146 };
11471147
11481148 twi2_clk: twi2_clk {
11491149 #clock-cells = <0>;
11501150 reg = <20>;
1151- atmel,clk-output-range = <0 16625000>;
1151+ atmel,clk-output-range = <0 41500000>;
11521152 };
11531153
11541154 mci0_clk: mci0_clk {
@@ -1164,19 +1164,19 @@
11641164 spi0_clk: spi0_clk {
11651165 #clock-cells = <0>;
11661166 reg = <24>;
1167- atmel,clk-output-range = <0 133000000>;
1167+ atmel,clk-output-range = <0 166000000>;
11681168 };
11691169
11701170 spi1_clk: spi1_clk {
11711171 #clock-cells = <0>;
11721172 reg = <25>;
1173- atmel,clk-output-range = <0 133000000>;
1173+ atmel,clk-output-range = <0 166000000>;
11741174 };
11751175
11761176 tcb0_clk: tcb0_clk {
11771177 #clock-cells = <0>;
11781178 reg = <26>;
1179- atmel,clk-output-range = <0 133000000>;
1179+ atmel,clk-output-range = <0 166000000>;
11801180 };
11811181
11821182 pwm_clk: pwm_clk {
@@ -1187,7 +1187,7 @@
11871187 adc_clk: adc_clk {
11881188 #clock-cells = <0>;
11891189 reg = <29>;
1190- atmel,clk-output-range = <0 66000000>;
1190+ atmel,clk-output-range = <0 83000000>;
11911191 };
11921192
11931193 dma0_clk: dma0_clk {
@@ -1218,13 +1218,13 @@
12181218 ssc0_clk: ssc0_clk {
12191219 #clock-cells = <0>;
12201220 reg = <38>;
1221- atmel,clk-output-range = <0 66000000>;
1221+ atmel,clk-output-range = <0 83000000>;
12221222 };
12231223
12241224 ssc1_clk: ssc1_clk {
12251225 #clock-cells = <0>;
12261226 reg = <39>;
1227- atmel,clk-output-range = <0 66000000>;
1227+ atmel,clk-output-range = <0 83000000>;
12281228 };
12291229
12301230 sha_clk: sha_clk {
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -37,13 +37,13 @@
3737 can0_clk: can0_clk {
3838 #clock-cells = <0>;
3939 reg = <40>;
40- atmel,clk-output-range = <0 66000000>;
40+ atmel,clk-output-range = <0 83000000>;
4141 };
4242
4343 can1_clk: can1_clk {
4444 #clock-cells = <0>;
4545 reg = <41>;
46- atmel,clk-output-range = <0 66000000>;
46+ atmel,clk-output-range = <0 83000000>;
4747 };
4848 };
4949 };
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -42,13 +42,13 @@
4242 uart0_clk: uart0_clk {
4343 #clock-cells = <0>;
4444 reg = <16>;
45- atmel,clk-output-range = <0 66000000>;
45+ atmel,clk-output-range = <0 83000000>;
4646 };
4747
4848 uart1_clk: uart1_clk {
4949 #clock-cells = <0>;
5050 reg = <17>;
51- atmel,clk-output-range = <0 66000000>;
51+ atmel,clk-output-range = <0 83000000>;
5252 };
5353 };
5454 };
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