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文件信息

文件大小
500,982 字节
MD5
6f7a7d30b634e7591586ee1615d00919

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项目描述

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.