提交: 33cb208e497186ed33e49bbb71e6d8229afc496f - binutils_os216 (git)

GNU Binutils with patches for OS216

Commit MetaInfo

• 修订版: 33cb208e497186ed33e49bbb71e6d8229afc496f (tree)
• 时间: 2002-06-19 06:21:06
• 作者: nobody <>
• Commiter: nobody <>

Log Message

This commit was manufactured by cvs2svn to create branch
'cagney_regbuf-20020515-branch'.

Cherrypick from master 2002-06-18 21:21:05 UTC Dave Brolley <[e-mail]> '2002-06-18 Dave Brolley <[e-mail]>':

bfd/cpu-frv.c
bfd/elf32-frv.c
include/elf/frv.h
opcodes/frv-asm.c
opcodes/frv-desc.c
opcodes/frv-desc.h
opcodes/frv-dis.c
opcodes/frv-ibld.c
opcodes/frv-opc.c
opcodes/frv-opc.h

更改概述

• add: bfd/cpu-frv.c
• add: bfd/elf32-frv.c
• add: include/elf/frv.h
• add: opcodes/frv-asm.c
• add: opcodes/frv-desc.c
• add: opcodes/frv-desc.h
• add: opcodes/frv-dis.c
• add: opcodes/frv-ibld.c
• add: opcodes/frv-opc.c
• add: opcodes/frv-opc.h

差异

--- /dev/null
+++ b/bfd/cpu-frv.c
@@ -0,0 +1,64 @@
+/* BFD support for the FRV processor.
+   Copyright (C) 2002 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+enum {
+  I_frv_generic,
+  I_frv_simple,
+  I_frv_500,
+  I_frv_300,
+};
+
+#define FRV_ARCH(MACHINE, NAME, DEFAULT, NEXT)				\
+{									\
+  32,	                        /* 32 bits in a word */			\
+  32,	                        /* 32 bits in an address */		\
+  8,	                        /* 8 bits in a byte */			\
+  bfd_arch_frv,			/* architecture */			\
+  MACHINE,			/* which machine */			\
+  "frv",			/* architecture name */			\
+  NAME,				/* machine name */			\
+  4,				/* default alignment */			\
+  DEFAULT,			/* is this the default? */		\
+  bfd_default_compatible,	/* architecture comparison fn */	\
+  bfd_default_scan,		/* string to architecture convert fn */	\
+  NEXT				/* next in list */			\
+}
+
+static const bfd_arch_info_type arch_info_300
+  = FRV_ARCH (bfd_mach_fr300,   "fr300",   false, (bfd_arch_info_type *)0);
+
+static const bfd_arch_info_type arch_info_400
+  = FRV_ARCH (bfd_mach_fr400, "fr400", false, &arch_info_300);
+
+static const bfd_arch_info_type arch_info_500
+  = FRV_ARCH (bfd_mach_fr500, "fr500", false, &arch_info_400);
+
+static const bfd_arch_info_type arch_info_simple
+  = FRV_ARCH (bfd_mach_frvsimple, "simple", false, &arch_info_500);
+
+static const bfd_arch_info_type arch_info_tomcat
+  = FRV_ARCH (bfd_mach_frvtomcat, "tomcat", false, &arch_info_simple);
+
+const bfd_arch_info_type bfd_frv_arch
+  = FRV_ARCH (bfd_mach_frv, "frv", true, &arch_info_tomcat);
+

--- /dev/null
+++ b/bfd/elf32-frv.c
@@ -0,0 +1,1405 @@
+/* FRV-specific support for 32-bit ELF.
+   Copyright (C) 2002 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/frv.h"
+
+/* Forward declarations.  */
+static bfd_reloc_status_type elf32_frv_relocate_lo16
+  PARAMS ((bfd *,  Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_hi16
+  PARAMS ((bfd *,  Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_label24
+  PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_gprel12
+  PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_gprelu12
+  PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_gprello
+  PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static bfd_reloc_status_type elf32_frv_relocate_gprelhi
+  PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma));
+static reloc_howto_type *frv_reloc_type_lookup
+  PARAMS ((bfd *, bfd_reloc_code_real_type));
+static void frv_info_to_howto_rela 
+  PARAMS ((bfd *, arelent *, Elf32_Internal_Rela *));
+static boolean elf32_frv_relocate_section 
+  PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **));
+static boolean elf32_frv_add_symbol_hook
+  PARAMS (( bfd *, struct bfd_link_info *, const Elf_Internal_Sym *, const char **, flagword *, asection **, bfd_vma *));
+static bfd_reloc_status_type frv_final_link_relocate
+  PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma));
+static boolean elf32_frv_gc_sweep_hook
+  PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *));
+static asection * elf32_frv_gc_mark_hook
+  PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *));
+static boolean elf32_frv_check_relocs
+  PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *));
+static int elf32_frv_machine PARAMS ((bfd *));
+static boolean elf32_frv_object_p PARAMS ((bfd *));
+static boolean frv_elf_set_private_flags PARAMS ((bfd *, flagword));
+static boolean frv_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *));
+static boolean frv_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *));
+static boolean frv_elf_print_private_bfd_data PARAMS ((bfd *, PTR));
+
+static reloc_howto_type elf32_frv_howto_table [] =
+{
+  /* This reloc does nothing.  */
+  HOWTO (R_FRV_NONE,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_NONE",		/* name */
+	 false,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0,			/* dst_mask */
+	 false),		/* pcrel_offset */
+
+  /* A 32 bit absolute relocation.  */
+  HOWTO (R_FRV_32,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_32",		/* name */
+	 false,			/* partial_inplace */
+	 0xffffffff,		/* src_mask */
+	 0xffffffff,		/* dst_mask */
+	 false),		/* pcrel_offset */
+
+  /* A 16 bit pc-relative relocation.  */
+  HOWTO (R_FRV_LABEL16,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 true,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_LABEL16",	/* name */
+	 false,			/* partial_inplace */
+	 0xffff,		/* src_mask */
+	 0xffff,		/* dst_mask */
+	 true),		        /* pcrel_offset */
+
+  /* A 24-bit pc-relative relocation.  */
+  HOWTO (R_FRV_LABEL24,	/* type */
+	 2,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 26,			/* bitsize */
+	 true,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_LABEL24",	/* name */
+	 false,			/* partial_inplace */
+	 0x7e03ffff,		/* src_mask */
+	 0x7e03ffff,		/* dst_mask */
+	 true),		        /* pcrel_offset */
+
+  HOWTO (R_FRV_LO16,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_LO16",		/* name */
+	false,			/* partial_inplace */
+	 0xffff,		/* src_mask */
+	 0xffff,		/* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_HI16,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_HI16",		/* name */
+	 false,			/* partial_inplace */
+	 0xffff,		/* src_mask */
+	 0xffff,		/* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_GPREL12,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 12,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_GPREL12",       /* name */
+	 false,			/* partial_inplace */
+	 0xfff,		        /* src_mask */
+	 0xfff,		        /* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_GPRELU12,        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 12,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_GPRELU12",      /* name */
+	 false,			/* partial_inplace */
+	 0xfff,		        /* src_mask */
+	 0x3f03f,	        /* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_GPREL32,         /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_GPREL32",	/* name */
+	 false,			/* partial_inplace */
+	 0xffffffff,            /* src_mask */
+	 0xffffffff,		/* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_GPRELHI,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_GPRELHI",	/* name */
+	 false,			/* partial_inplace */
+	 0xffff,		        /* src_mask */
+	 0xffff,		/* dst_mask */
+	 false),	        /* pcrel_offset */
+
+  HOWTO (R_FRV_GPRELLO,	        /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 16,			/* bitsize */
+	 false,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_dont, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_FRV_GPRELLO",	/* name */
+	 false,			/* partial_inplace */
+	 0xffff,		        /* src_mask */
+	 0xffff,		/* dst_mask */
+	 false),	        /* pcrel_offset */
+};
+
+/* GNU extension to record C++ vtable hierarchy.  */
+static reloc_howto_type elf32_frv_vtinherit_howto =
+  HOWTO (R_FRV_GNU_VTINHERIT,   /* type */
+         0,                     /* rightshift */
+         2,                     /* size (0 = byte, 1 = short, 2 = long) */
+         0,                     /* bitsize */
+         false,                 /* pc_relative */
+         0,                     /* bitpos */
+         complain_overflow_dont, /* complain_on_overflow */
+         NULL,                  /* special_function */
+         "R_FRV_GNU_VTINHERIT", /* name */
+         false,                 /* partial_inplace */
+         0,                     /* src_mask */
+         0,                     /* dst_mask */
+         false);                /* pcrel_offset */
+
+  /* GNU extension to record C++ vtable member usage.  */
+static reloc_howto_type elf32_frv_vtentry_howto =
+  HOWTO (R_FRV_GNU_VTENTRY,     /* type */
+         0,                     /* rightshift */
+         2,                     /* size (0 = byte, 1 = short, 2 = long) */
+         0,                     /* bitsize */
+         false,                 /* pc_relative */
+         0,                     /* bitpos */
+         complain_overflow_dont, /* complain_on_overflow */
+         _bfd_elf_rel_vtable_reloc_fn,  /* special_function */
+         "R_FRV_GNU_VTENTRY",   /* name */
+         false,                 /* partial_inplace */
+         0,                     /* src_mask */
+         0,                     /* dst_mask */
+         false);                /* pcrel_offset */
+
+/* Map BFD reloc types to FRV ELF reloc types.  */
+#if 0
+struct frv_reloc_map
+{
+  unsigned int bfd_reloc_val;
+  unsigned int frv_reloc_val;
+};
+
+static const struct frv_reloc_map frv_reloc_map [] =
+{
+  { BFD_RELOC_NONE,           R_FRV_NONE },
+  { BFD_RELOC_32,             R_FRV_32 },
+  { BFD_RELOC_FRV_LABEL16,    R_FRV_LABEL16 },
+  { BFD_RELOC_FRV_LABEL24,    R_FRV_LABEL24 },
+  { BFD_RELOC_FRV_LO16,       R_FRV_LO16 },
+  { BFD_RELOC_FRV_HI16,       R_FRV_HI16 },
+  { BFD_RELOC_FRV_GPREL12,    R_FRV_GPREL12 },
+  { BFD_RELOC_FRV_GPRELU12,   R_FRV_GPRELU12 },
+  { BFD_RELOC_FRV_GPREL32,    R_FRV_GPREL32 },
+  { BFD_RELOC_FRV_GPRELHI,    R_FRV_GPRELHI },
+  { BFD_RELOC_FRV_GPRELLO,    R_FRV_GPRELLO },
+  { BFD_RELOC_VTABLE_INHERIT, R_FRV_GNU_VTINHERIT },
+  { BFD_RELOC_VTABLE_ENTRY,   R_FRV_GNU_VTENTRY },
+};
+#endif
+
+/* Handle an FRV small data reloc.  */
+
+static bfd_reloc_status_type
+elf32_frv_relocate_gprel12 (info, input_bfd, input_section, relocation, contents, value)
+     struct bfd_link_info *info;
+     bfd *input_bfd;
+     asection *input_section;
+     Elf_Internal_Rela *relocation;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+  bfd_vma gp;
+  struct bfd_link_hash_entry *h;
+
+  h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true);
+
+  gp = (h->u.def.value
+	+ h->u.def.section->output_section->vma
+	+ h->u.def.section->output_offset);
+
+  value -= input_section->output_section->vma;
+  value -= (gp - input_section->output_section->vma);
+
+  insn = bfd_get_32 (input_bfd, contents + relocation->r_offset);
+
+  value += relocation->r_addend;
+
+  if ((long) value > 0x7ff || (long) value < -0x800)
+    return bfd_reloc_overflow;
+
+  bfd_put_32 (input_bfd,
+	      (insn & 0xfffff000) | (value & 0xfff),
+	      contents + relocation->r_offset);
+
+  return bfd_reloc_ok;
+}
+
+/* Handle an FRV small data reloc. for the u12 field.  */
+
+static bfd_reloc_status_type
+elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, relocation, contents, value)
+     struct bfd_link_info *info;
+     bfd *input_bfd;
+     asection *input_section;
+     Elf_Internal_Rela *relocation;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+  bfd_vma gp;
+  struct bfd_link_hash_entry *h;
+  bfd_vma mask;
+
+  h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true);
+
+  gp = (h->u.def.value
+	+ h->u.def.section->output_section->vma
+	+ h->u.def.section->output_offset);
+ 
+  value -= input_section->output_section->vma;
+  value -= (gp - input_section->output_section->vma);
+
+  insn = bfd_get_32 (input_bfd, contents + relocation->r_offset);
+
+  value += relocation->r_addend;
+
+  if ((long) value > 0x7ff || (long) value < -0x800)
+    return bfd_reloc_overflow;
+
+  /* The high 6 bits go into bits 17-12. The low 6 bits go into bits 5-0.  */
+  mask = 0x3f03f;
+  insn = (insn & ~mask) | ((value & 0xfc0) << 12) | (value & 0x3f);
+
+  bfd_put_32 (input_bfd, insn, contents + relocation->r_offset);
+
+  return bfd_reloc_ok;
+}
+
+/* Handle an FRV ELF HI16 reloc.  */
+
+static bfd_reloc_status_type
+elf32_frv_relocate_hi16 (input_bfd, relhi, contents, value)
+     bfd *input_bfd;
+     Elf_Internal_Rela *relhi;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+
+  insn = bfd_get_32 (input_bfd, contents + relhi->r_offset);
+
+  value += relhi->r_addend;
+  value = ((value >> 16) & 0xffff);
+
+  insn = (insn & 0xffff0000) | value;
+
+  if ((long) value > 0xffff || (long) value < -0x10000)
+    return bfd_reloc_overflow;
+
+  bfd_put_32 (input_bfd, insn, contents + relhi->r_offset);
+  return bfd_reloc_ok;
+
+}
+static bfd_reloc_status_type
+elf32_frv_relocate_lo16 (input_bfd, rello, contents, value)
+     bfd *input_bfd;
+     Elf_Internal_Rela *rello;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+
+  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
+
+  value += rello->r_addend;
+  value = value & 0xffff;
+
+  insn = (insn & 0xffff0000) | value;
+
+  if ((long) value > 0xffff || (long) value < -0x10000)
+    return bfd_reloc_overflow;
+
+  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
+  return bfd_reloc_ok;
+}
+
+/* Perform the relocation for the CALL label24 instruction.  */
+
+static bfd_reloc_status_type
+elf32_frv_relocate_label24 (input_bfd, input_section, rello, contents, value)
+     bfd *input_bfd;
+     asection *input_section;
+     Elf_Internal_Rela *rello;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+  bfd_vma label6;
+  bfd_vma label18;
+
+  /* The format for the call instruction is:
+
+    0 000000 0001111 000000000000000000 
+      label6 opcode  label18
+
+    The branch calculation is: pc + (4*label24)
+    where label24 is the concatenation of label6 and label18.  */
+
+  /* Grab the instruction.  */
+  insn = bfd_get_32 (input_bfd, contents + rello->r_offset);
+
+  value -= input_section->output_section->vma + input_section->output_offset;
+  value -= rello->r_offset;
+  value += rello->r_addend;
+
+  value = value >> 2;
+
+  label6  = value & 0xfc0000;
+  label6  = label6 << 7;
+
+  label18 = value & 0x3ffff;
+
+  insn = insn & 0x803c0000;
+  insn = insn | label6;
+  insn = insn | label18;
+
+  bfd_put_32 (input_bfd, insn, contents + rello->r_offset);
+
+  return bfd_reloc_ok;
+}
+
+static bfd_reloc_status_type
+elf32_frv_relocate_gprelhi (info, input_bfd, input_section, relocation, contents, value)
+     struct bfd_link_info *info;
+     bfd *input_bfd;
+     asection *input_section;
+     Elf_Internal_Rela *relocation;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+  bfd_vma gp;
+  struct bfd_link_hash_entry *h;
+
+  h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true);
+
+  gp = (h->u.def.value
+        + h->u.def.section->output_section->vma
+        + h->u.def.section->output_offset);
+
+  value -= input_section->output_section->vma;
+  value -= (gp - input_section->output_section->vma);
+  value += relocation->r_addend;
+  value = ((value >> 16) & 0xffff);
+
+  if ((long) value > 0xffff || (long) value < -0x10000)
+    return bfd_reloc_overflow;
+
+  insn = bfd_get_32 (input_bfd, contents + relocation->r_offset);
+  insn = (insn & 0xffff0000) | value;
+
+  bfd_put_32 (input_bfd, insn, contents + relocation->r_offset);
+  return bfd_reloc_ok;
+}
+
+static bfd_reloc_status_type
+elf32_frv_relocate_gprello (info, input_bfd, input_section, relocation, contents, value)
+     struct bfd_link_info *info;
+     bfd *input_bfd;
+     asection *input_section;
+     Elf_Internal_Rela *relocation;
+     bfd_byte *contents;
+     bfd_vma value;
+{
+  bfd_vma insn;
+  bfd_vma gp;
+  struct bfd_link_hash_entry *h;
+
+  h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true);
+
+  gp = (h->u.def.value
+        + h->u.def.section->output_section->vma
+        + h->u.def.section->output_offset);
+
+  value -= input_section->output_section->vma;
+  value -= (gp - input_section->output_section->vma);
+  value += relocation->r_addend;
+  value = value & 0xffff;
+
+  if ((long) value > 0xffff || (long) value < -0x10000)
+    return bfd_reloc_overflow;
+
+  insn = bfd_get_32 (input_bfd, contents + relocation->r_offset);
+  insn = (insn & 0xffff0000) | value;
+
+  bfd_put_32 (input_bfd, insn, contents + relocation->r_offset);
+
+ return bfd_reloc_ok;
+}
+
+static reloc_howto_type *
+frv_reloc_type_lookup (abfd, code)
+     bfd * abfd ATTRIBUTE_UNUSED;
+     bfd_reloc_code_real_type code;
+{
+  switch (code)
+    {
+    default:
+      break;
+
+    case BFD_RELOC_NONE:
+      return &elf32_frv_howto_table[ (int) R_FRV_NONE];
+  
+    case BFD_RELOC_32:
+    case BFD_RELOC_CTOR:
+      return &elf32_frv_howto_table[ (int) R_FRV_32];
+
+    case BFD_RELOC_FRV_LABEL16:
+      return &elf32_frv_howto_table[ (int) R_FRV_LABEL16];
+
+    case BFD_RELOC_FRV_LABEL24:
+      return &elf32_frv_howto_table[ (int) R_FRV_LABEL24];
+
+    case BFD_RELOC_FRV_LO16:
+      return &elf32_frv_howto_table[ (int) R_FRV_LO16];
+
+    case BFD_RELOC_FRV_HI16:
+      return &elf32_frv_howto_table[ (int) R_FRV_HI16];
+
+    case BFD_RELOC_FRV_GPREL12:
+      return &elf32_frv_howto_table[ (int) R_FRV_GPREL12];
+
+    case BFD_RELOC_FRV_GPRELU12:
+      return &elf32_frv_howto_table[ (int) R_FRV_GPRELU12];
+
+    case BFD_RELOC_FRV_GPREL32:
+      return &elf32_frv_howto_table[ (int) R_FRV_GPREL32];
+
+    case BFD_RELOC_FRV_GPRELHI:
+      return &elf32_frv_howto_table[ (int) R_FRV_GPRELHI];
+
+    case BFD_RELOC_FRV_GPRELLO:
+      return &elf32_frv_howto_table[ (int) R_FRV_GPRELLO];
+
+    case BFD_RELOC_VTABLE_INHERIT:
+      return &elf32_frv_vtinherit_howto;
+
+    case BFD_RELOC_VTABLE_ENTRY:
+      return &elf32_frv_vtentry_howto;
+    }
+
+  return NULL;
+}
+
+/* Set the howto pointer for an FRV ELF reloc.  */
+
+static void
+frv_info_to_howto_rela (abfd, cache_ptr, dst)
+     bfd * abfd ATTRIBUTE_UNUSED;
+     arelent * cache_ptr;
+     Elf32_Internal_Rela * dst;
+{
+  unsigned int r_type;
+
+  r_type = ELF32_R_TYPE (dst->r_info);
+  switch (r_type)
+    {
+    case R_FRV_GNU_VTINHERIT:
+      cache_ptr->howto = &elf32_frv_vtinherit_howto;
+      break;
+
+    case R_FRV_GNU_VTENTRY:
+      cache_ptr->howto = &elf32_frv_vtentry_howto;
+      break;
+
+    default:
+      cache_ptr->howto = & elf32_frv_howto_table [r_type];
+      break;
+    }
+}
+
+/* Perform a single relocation.  By default we use the standard BFD
+   routines, but a few relocs, we have to do them ourselves.  */
+
+static bfd_reloc_status_type
+frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation)
+     reloc_howto_type *  howto;
+     bfd *               input_bfd;
+     asection *          input_section;
+     bfd_byte *          contents;
+     Elf_Internal_Rela * rel;
+     bfd_vma             relocation;
+{
+  return _bfd_final_link_relocate (howto, input_bfd, input_section,
+				   contents, rel->r_offset, relocation,
+				   rel->r_addend);
+}
+
+
+/* Relocate an FRV ELF section.
+   There is some attempt to make this function usable for many architectures,
+   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
+   if only to serve as a learning tool.
+
+   The RELOCATE_SECTION function is called by the new ELF backend linker
+   to handle the relocations for a section.
+
+   The relocs are always passed as Rela structures; if the section
+   actually uses Rel structures, the r_addend field will always be
+   zero.
+
+   This function is responsible for adjusting the section contents as
+   necessary, and (if using Rela relocs and generating a relocateable
+   output file) adjusting the reloc addend as necessary.
+
+   This function does not have to worry about setting the reloc
+   address or the reloc symbol index.
+
+   LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+   LOCAL_SECTIONS is an array giving the section in the input file
+   corresponding to the st_shndx field of each local symbol.
+
+   The global hash table entry for the global symbols can be found
+   via elf_sym_hashes (input_bfd).
+
+   When generating relocateable output, this function must handle
+   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
+   going to be the section symbol corresponding to the output
+   section, which means that the addend must be adjusted
+   accordingly.  */
+
+static boolean
+elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section,
+			   contents, relocs, local_syms, local_sections)
+     bfd *                   output_bfd ATTRIBUTE_UNUSED;
+     struct bfd_link_info *  info;
+     bfd *                   input_bfd;
+     asection *              input_section;
+     bfd_byte *              contents;
+     Elf_Internal_Rela *     relocs;
+     Elf_Internal_Sym *      local_syms;
+     asection **             local_sections;
+{
+  Elf_Internal_Shdr *           symtab_hdr;
+  struct elf_link_hash_entry ** sym_hashes;
+  Elf_Internal_Rela *           rel;
+  Elf_Internal_Rela *           relend;
+
+  symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+  sym_hashes = elf_sym_hashes (input_bfd);
+  relend     = relocs + input_section->reloc_count;
+
+  for (rel = relocs; rel < relend; rel ++)
+    {
+      reloc_howto_type *           howto;
+      unsigned long                r_symndx;
+      Elf_Internal_Sym *           sym;
+      asection *                   sec;
+      struct elf_link_hash_entry * h;
+      bfd_vma                      relocation;
+      bfd_reloc_status_type        r;
+      const char *                 name = NULL;
+      int                          r_type;
+      
+      r_type = ELF32_R_TYPE (rel->r_info);
+      
+      if (   r_type == R_FRV_GNU_VTINHERIT
+	  || r_type == R_FRV_GNU_VTENTRY)
+	continue;
+      
+      r_symndx = ELF32_R_SYM (rel->r_info);
+
+      if (info->relocateable)
+	{
+	  /* This is a relocateable link.  We don't have to change
+             anything, unless the reloc is against a section symbol,
+             in which case we have to adjust according to where the
+             section symbol winds up in the output section.  */
+	  if (r_symndx < symtab_hdr->sh_info)
+	    {
+	      sym = local_syms + r_symndx;
+	      
+	      if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+		{
+		  sec = local_sections [r_symndx];
+		  rel->r_addend += sec->output_offset + sym->st_value;
+		}
+	    }
+
+	  continue;
+	}
+
+      /* This is a final link.  */
+      howto  = elf32_frv_howto_table + ELF32_R_TYPE (rel->r_info);
+      h      = NULL;
+      sym    = NULL;
+      sec    = NULL;
+      
+      if (r_symndx < symtab_hdr->sh_info)
+	{
+	  sym = local_syms + r_symndx;
+	  sec = local_sections [r_symndx];
+	  relocation = (sec->output_section->vma
+			+ sec->output_offset
+			+ sym->st_value);
+	  
+	  name = bfd_elf_string_from_elf_section
+	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
+	  name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
+	}
+      else
+	{
+	  h = sym_hashes [r_symndx - symtab_hdr->sh_info];
+	  
+	  while (h->root.type == bfd_link_hash_indirect
+		 || h->root.type == bfd_link_hash_warning)
+	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+	  name = h->root.root.string;
+	  
+	  if (h->root.type == bfd_link_hash_defined
+	      || h->root.type == bfd_link_hash_defweak)
+	    {
+	      sec = h->root.u.def.section;
+	      relocation = (h->root.u.def.value
+			    + sec->output_section->vma
+			    + sec->output_offset);
+	    }
+	  else if (h->root.type == bfd_link_hash_undefweak)
+	    {
+	      relocation = 0;
+	    }
+	  else
+	    {
+	      if (! ((*info->callbacks->undefined_symbol)
+		     (info, h->root.root.string, input_bfd,
+		      input_section, rel->r_offset, true)))
+		return false;
+	      relocation = 0;
+	    }
+	}
+      
+     if (r_type == R_FRV_HI16)
+       r = elf32_frv_relocate_hi16 (input_bfd, rel, contents, relocation);
+
+     else if (r_type == R_FRV_LO16)
+       r = elf32_frv_relocate_lo16 (input_bfd, rel, contents, relocation);
+
+     else if (r_type == R_FRV_LABEL24)
+       r = elf32_frv_relocate_label24 (input_bfd, input_section, rel, contents, relocation);
+
+     else if (r_type == R_FRV_GPREL12)
+       r = elf32_frv_relocate_gprel12 (info, input_bfd, input_section, rel, contents, relocation);
+
+     else if (r_type == R_FRV_GPRELU12)
+       r = elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, rel, contents, relocation);
+
+     else if (r_type == R_FRV_GPRELLO)
+       r = elf32_frv_relocate_gprello (info, input_bfd, input_section, rel, contents, relocation);
+
+     else if (r_type == R_FRV_GPRELHI)
+       r = elf32_frv_relocate_gprelhi (info, input_bfd, input_section, rel, contents, relocation);
+
+     else
+       r = frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation);
+
+      if (r != bfd_reloc_ok)
+	{
+	  const char * msg = (const char *) NULL;
+
+	  switch (r)
+	    {
+	    case bfd_reloc_overflow:
+	      r = info->callbacks->reloc_overflow
+		(info, name, howto->name, (bfd_vma) 0,
+		 input_bfd, input_section, rel->r_offset);
+	      break;
+	      
+	    case bfd_reloc_undefined:
+	      r = info->callbacks->undefined_symbol
+		(info, name, input_bfd, input_section, rel->r_offset, true);
+	      break;
+	      
+	    case bfd_reloc_outofrange:
+	      msg = _("internal error: out of range error");
+	      break;
+
+	    case bfd_reloc_notsupported:
+	      msg = _("internal error: unsupported relocation error");
+	      break;
+
+	    case bfd_reloc_dangerous:
+	      msg = _("internal error: dangerous relocation");
+	      break;
+
+	    default:
+	      msg = _("internal error: unknown error");
+	      break;
+	    }
+
+	  if (msg)
+	    r = info->callbacks->warning
+	      (info, msg, name, input_bfd, input_section, rel->r_offset);
+
+	  if (! r)
+	    return false;
+	}
+    }
+
+  return true;
+}
+
+/* Return the section that should be marked against GC for a given
+   relocation.  */
+
+static asection *
+elf32_frv_gc_mark_hook (abfd, info, rel, h, sym)
+     bfd *                        abfd;
+     struct bfd_link_info *       info ATTRIBUTE_UNUSED;
+     Elf_Internal_Rela *          rel;
+     struct elf_link_hash_entry * h;
+     Elf_Internal_Sym *           sym;
+{
+  if (h != NULL)
+    {
+      switch (ELF32_R_TYPE (rel->r_info))
+	{
+	case R_FRV_GNU_VTINHERIT:
+	case R_FRV_GNU_VTENTRY:
+	  break;
+
+	default:
+	  switch (h->root.type)
+	    {
+	    default:
+	      break;
+
+	    case bfd_link_hash_defined:
+	    case bfd_link_hash_defweak:
+	      return h->root.u.def.section;
+
+	    case bfd_link_hash_common:
+	      return h->root.u.c.p->section;
+	    }
+	}
+    }
+  else
+    {
+      if (!(elf_bad_symtab (abfd)
+	    && ELF_ST_BIND (sym->st_info) != STB_LOCAL)
+	  && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE)
+		&& sym->st_shndx != SHN_COMMON))
+	return bfd_section_from_elf_index (abfd, sym->st_shndx);
+    }
+
+  return NULL;
+}
+
+/* Update the got entry reference counts for the section being removed.  */
+
+static boolean
+elf32_frv_gc_sweep_hook (abfd, info, sec, relocs)
+     bfd *                     abfd ATTRIBUTE_UNUSED;
+     struct bfd_link_info *    info ATTRIBUTE_UNUSED;
+     asection *                sec ATTRIBUTE_UNUSED;
+     const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED;
+{
+  return true;
+}
+
+
+/* Hook called by the linker routine which adds symbols from an object
+   file.  We use it to put .comm items in .scomm, and not .comm.  */
+
+static boolean
+elf32_frv_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     const Elf_Internal_Sym *sym;
+     const char **namep ATTRIBUTE_UNUSED;
+     flagword *flagsp ATTRIBUTE_UNUSED;
+     asection **secp;
+     bfd_vma *valp;
+{
+  if (sym->st_shndx == SHN_COMMON
+      && !info->relocateable
+      && (int)sym->st_size <= (int)bfd_get_gp_size (abfd))
+    {
+      /* Common symbols less than or equal to -G nn bytes are
+	 automatically put into .sbss.  */
+
+      asection *scomm = bfd_get_section_by_name (abfd, ".scommon");
+
+      if (scomm == NULL)
+	{
+	  scomm = bfd_make_section (abfd, ".scommon");
+	  if (scomm == NULL
+	      || !bfd_set_section_flags (abfd, scomm, (SEC_ALLOC
+						       | SEC_IS_COMMON
+						       | SEC_LINKER_CREATED)))
+	    return false;
+	}
+
+      *secp = scomm;
+      *valp = sym->st_size;
+    }
+
+  return true;
+}
+/* Look through the relocs for a section during the first phase.
+   Since we don't do .gots or .plts, we just need to consider the
+   virtual table relocs for gc.  */
+ 
+static boolean
+elf32_frv_check_relocs (abfd, info, sec, relocs)
+     bfd *abfd;
+     struct bfd_link_info *info;
+     asection *sec;
+     const Elf_Internal_Rela *relocs;
+{
+  Elf_Internal_Shdr *symtab_hdr;
+  struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
+  const Elf_Internal_Rela *rel;
+  const Elf_Internal_Rela *rel_end;
+ 
+  if (info->relocateable)
+    return true;
+ 
+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+  sym_hashes = elf_sym_hashes (abfd);
+  sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym);
+  if (!elf_bad_symtab (abfd))
+    sym_hashes_end -= symtab_hdr->sh_info;
+ 
+  rel_end = relocs + sec->reloc_count;
+  for (rel = relocs; rel < rel_end; rel++)
+    {
+      struct elf_link_hash_entry *h;
+      unsigned long r_symndx;
+ 
+      r_symndx = ELF32_R_SYM (rel->r_info);
+      if (r_symndx < symtab_hdr->sh_info)
+        h = NULL;
+      else
+        h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ 
+      switch (ELF32_R_TYPE (rel->r_info))
+        {
+        /* This relocation describes the C++ object vtable hierarchy.
+           Reconstruct it for later use during GC.  */
+        case R_FRV_GNU_VTINHERIT:
+          if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
+            return false;
+          break;
+ 
+        /* This relocation describes which C++ vtable entries are actually
+           used.  Record for later use during GC.  */
+        case R_FRV_GNU_VTENTRY:
+          if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend))
+            return false;
+          break;
+        }
+    }
+ 
+  return true;
+}
+
+
+/* Return the machine subcode from the ELF e_flags header.  */
+
+static int
+elf32_frv_machine (abfd)
+     bfd *abfd;
+{
+  switch (elf_elfheader (abfd)->e_flags & EF_FRV_CPU_MASK)
+    {
+    default:		    break;
+    case EF_FRV_CPU_FR500:  return bfd_mach_fr500;
+    case EF_FRV_CPU_FR400:  return bfd_mach_fr400;
+    case EF_FRV_CPU_FR300:  return bfd_mach_fr300;
+    case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple;
+    case EF_FRV_CPU_TOMCAT: return bfd_mach_frvtomcat;
+    }
+
+  return bfd_mach_frv;
+}
+
+/* Set the right machine number for a FRV ELF file.  */
+
+static boolean
+elf32_frv_object_p (abfd)
+     bfd *abfd;
+{
+  bfd_default_set_arch_mach (abfd, bfd_arch_frv, elf32_frv_machine (abfd));
+  return true;
+}
+
+/* Function to set the ELF flag bits.  */
+
+static boolean
+frv_elf_set_private_flags (abfd, flags)
+     bfd *abfd;
+     flagword flags;
+{
+  elf_elfheader (abfd)->e_flags = flags;
+  elf_flags_init (abfd) = true;
+  return true;
+}
+
+/* Copy backend specific data from one object module to another.  */
+
+static boolean
+frv_elf_copy_private_bfd_data (ibfd, obfd)
+     bfd *ibfd;
+     bfd *obfd;
+{
+  if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+      || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+    return true;
+
+  BFD_ASSERT (!elf_flags_init (obfd)
+	      || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags);
+
+  elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
+  elf_flags_init (obfd) = true;
+  return true;
+}
+
+/* Merge backend specific data from an object file to the output
+   object file when linking.  */
+
+static boolean
+frv_elf_merge_private_bfd_data (ibfd, obfd)
+     bfd *ibfd;
+     bfd *obfd;
+{
+  flagword old_flags, old_partial;
+  flagword new_flags, new_partial;
+  boolean error = false;
+  char new_opt[80];
+  char old_opt[80];
+
+  new_opt[0] = old_opt[0] = '\0';
+  new_flags = elf_elfheader (ibfd)->e_flags;
+  old_flags = elf_elfheader (obfd)->e_flags;
+
+#ifdef DEBUG
+  (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s",
+			 old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no",
+			 bfd_get_filename (ibfd));
+#endif
+
+  if (!elf_flags_init (obfd))			/* First call, no flags set.  */
+    {
+      elf_flags_init (obfd) = true;
+      old_flags = new_flags;
+    }
+
+  else if (new_flags == old_flags)		/* Compatible flags are ok.  */
+    ;
+
+  else						/* Possibly incompatible flags.  */
+    {
+      /* Warn if different # of gprs are used.  Note, 0 means nothing is
+         said about the size of gprs.  */
+      new_partial = (new_flags & EF_FRV_GPR_MASK);
+      old_partial = (old_flags & EF_FRV_GPR_MASK);
+      if (new_partial == old_partial)
+	;
+
+      else if (new_partial == 0)
+	;
+
+      else if (old_partial == 0)
+	old_flags |= new_partial;
+
+      else
+	{
+	  switch (new_partial)
+	    {
+	    default:		strcat (new_opt, " -mgpr-??"); break;
+	    case EF_FRV_GPR_32: strcat (new_opt, " -mgpr-32"); break;
+	    case EF_FRV_GPR_64: strcat (new_opt, " -mgpr-64"); break;
+	    }
+
+	  switch (old_partial)
+	    {
+	    default:		strcat (old_opt, " -mgpr-??"); break;
+	    case EF_FRV_GPR_32: strcat (old_opt, " -mgpr-32"); break;
+	    case EF_FRV_GPR_64: strcat (old_opt, " -mgpr-64"); break;
+	    }
+	}
+
+      /* Warn if different # of fprs are used.  Note, 0 means nothing is
+         said about the size of fprs.  */
+      new_partial = (new_flags & EF_FRV_FPR_MASK);
+      old_partial = (old_flags & EF_FRV_FPR_MASK);
+      if (new_partial == old_partial)
+	;
+
+      else if (new_partial == 0)
+	;
+
+      else if (old_partial == 0)
+	old_flags |= new_partial;
+
+      else
+	{
+	  switch (new_partial)
+	    {
+	    default:		  strcat (new_opt, " -mfpr-?");      break;
+	    case EF_FRV_FPR_32:   strcat (new_opt, " -mfpr-32");     break;
+	    case EF_FRV_FPR_64:   strcat (new_opt, " -mfpr-64");     break;
+	    case EF_FRV_FPR_NONE: strcat (new_opt, " -msoft-float"); break;
+	    }
+
+	  switch (old_partial)
+	    {
+	    default:		  strcat (old_opt, " -mfpr-?");      break;
+	    case EF_FRV_FPR_32:   strcat (old_opt, " -mfpr-32");     break;
+	    case EF_FRV_FPR_64:   strcat (old_opt, " -mfpr-64");     break;
+	    case EF_FRV_FPR_NONE: strcat (old_opt, " -msoft-float"); break;
+	    }
+	}
+
+      /* Warn if different dword support was used.  Note, 0 means nothing is
+         said about the dword support.  */
+      new_partial = (new_flags & EF_FRV_DWORD_MASK);
+      old_partial = (old_flags & EF_FRV_DWORD_MASK);
+      if (new_partial == old_partial)
+	;
+
+      else if (new_partial == 0)
+	;
+
+      else if (old_partial == 0)
+	old_flags |= new_partial;
+
+      else
+	{
+	  switch (new_partial)
+	    {
+	    default:		   strcat (new_opt, " -mdword-?");  break;
+	    case EF_FRV_DWORD_YES: strcat (new_opt, " -mdword");    break;
+	    case EF_FRV_DWORD_NO:  strcat (new_opt, " -mno-dword"); break;
+	    }
+
+	  switch (old_partial)
+	    {
+	    default:		   strcat (old_opt, " -mdword-?");  break;
+	    case EF_FRV_DWORD_YES: strcat (old_opt, " -mdword");    break;
+	    case EF_FRV_DWORD_NO:  strcat (old_opt, " -mno-dword"); break;
+	    }
+	}
+
+      /* Or in flags that accumulate (ie, if one module uses it, mark that the
+	 feature is used.  */
+      old_flags |= new_flags & (EF_FRV_DOUBLE
+				| EF_FRV_MEDIA
+				| EF_FRV_MULADD
+				| EF_FRV_NON_PIC_RELOCS);
+
+      /* If any module was compiled without -G0, clear the G0 bit.  */
+      old_flags = ((old_flags & ~ EF_FRV_G0)
+		   | (old_flags & new_flags & EF_FRV_G0));
+
+      /* If any module was compiled without -mnopack, clear the mnopack bit.  */
+      old_flags = ((old_flags & ~ EF_FRV_NOPACK)
+		   | (old_flags & new_flags & EF_FRV_NOPACK));
+
+      /* We don't have to do anything if the pic flags are the same, or the new
+         module(s) were compiled with -mlibrary-pic.  */
+      new_partial = (new_flags & EF_FRV_PIC_FLAGS);
+      old_partial = (old_flags & EF_FRV_PIC_FLAGS);
+      if ((new_partial == old_partial) || ((new_partial & EF_FRV_LIBPIC) != 0))
+	;
+
+      /* If the old module(s) were compiled with -mlibrary-pic, copy in the pic
+         flags if any from the new module.  */
+      else if ((old_partial & EF_FRV_LIBPIC) != 0)
+	old_flags = (old_flags & ~ EF_FRV_PIC_FLAGS) | new_partial;
+
+      /* If we have mixtures of -fpic and -fPIC, or in both bits.  */
+      else if (new_partial != 0 && old_partial != 0)
+	old_flags |= new_partial;
+
+      /* One module was compiled for pic and the other was not, see if we have
+         had any relocations that are not pic-safe.  */
+      else
+	{
+	  if ((old_flags & EF_FRV_NON_PIC_RELOCS) == 0)
+	    old_flags |= new_partial;
+	  else
+	    {
+	      old_flags &= ~ EF_FRV_PIC_FLAGS;
+#ifndef FRV_NO_PIC_ERROR
+	      error = true;
+	      (*_bfd_error_handler)
+		(_("%s: compiled with %s and linked with modules that use non-pic relocations"),
+		 bfd_get_filename (ibfd),
+		 (new_flags & EF_FRV_BIGPIC) ? "-fPIC" : "-fpic");
+#endif
+	    }
+	}
+
+      /* Warn if different cpu is used (allow a specific cpu to override
+	 the generic cpu).  */
+      new_partial = (new_flags & EF_FRV_CPU_MASK);
+      old_partial = (old_flags & EF_FRV_CPU_MASK);
+      if (new_partial == old_partial)
+	;
+
+      else if (new_partial == EF_FRV_CPU_GENERIC)
+	;
+
+      else if (old_partial == EF_FRV_CPU_GENERIC)
+	old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial;
+
+      else
+	{
+	  switch (new_partial)
+	    {
+	    default:		     strcat (new_opt, " -mcpu=?");      break;
+	    case EF_FRV_CPU_GENERIC: strcat (new_opt, " -mcpu=frv");    break;
+	    case EF_FRV_CPU_SIMPLE:  strcat (new_opt, " -mcpu=simple"); break;
+	    case EF_FRV_CPU_FR500:   strcat (new_opt, " -mcpu=fr500");  break;
+	    case EF_FRV_CPU_FR400:   strcat (new_opt, " -mcpu=fr400");  break;
+	    case EF_FRV_CPU_FR300:   strcat (new_opt, " -mcpu=fr300");  break;
+	    case EF_FRV_CPU_TOMCAT:  strcat (new_opt, " -mcpu=tomcat"); break;
+	    }
+
+	  switch (old_partial)
+	    {
+	    default:		     strcat (old_opt, " -mcpu=?");      break;
+	    case EF_FRV_CPU_GENERIC: strcat (old_opt, " -mcpu=frv");    break;
+	    case EF_FRV_CPU_SIMPLE:  strcat (old_opt, " -mcpu=simple"); break;
+	    case EF_FRV_CPU_FR500:   strcat (old_opt, " -mcpu=fr500");  break;
+	    case EF_FRV_CPU_FR400:   strcat (old_opt, " -mcpu=fr400");  break;
+	    case EF_FRV_CPU_FR300:   strcat (old_opt, " -mcpu=fr300");  break;
+	    case EF_FRV_CPU_TOMCAT:  strcat (old_opt, " -mcpu=tomcat"); break;
+	    }
+	}
+      
+      /* Print out any mismatches from above.  */
+      if (new_opt[0])
+	{
+	  error = true;
+	  (*_bfd_error_handler)
+	    (_("%s: compiled with %s and linked with modules compiled with %s"),
+	     bfd_get_filename (ibfd), new_opt, old_opt);
+	}
+
+      /* Warn about any other mismatches */
+      new_partial = (new_flags & ~ EF_FRV_ALL_FLAGS);
+      old_partial = (old_flags & ~ EF_FRV_ALL_FLAGS);
+      if (new_partial != old_partial)
+	{
+	  old_flags |= new_partial;
+	  error = true;
+	  (*_bfd_error_handler)
+	    (_("%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"),
+	     bfd_get_filename (ibfd), (long)new_partial, (long)old_partial);
+	}
+    }
+
+  /* If the cpu is -mcpu=simple, then set the -mnopack bit.  */
+  if ((old_flags & EF_FRV_CPU_MASK) == EF_FRV_CPU_SIMPLE)
+    old_flags |= EF_FRV_NOPACK;
+
+  /* Update the old flags now with changes made above.  */
+  old_partial = elf_elfheader (obfd)->e_flags & EF_FRV_CPU_MASK;
+  elf_elfheader (obfd)->e_flags = old_flags;
+  if (old_partial != (old_flags & EF_FRV_CPU_MASK))
+    bfd_default_set_arch_mach (obfd, bfd_arch_frv, elf32_frv_machine (obfd));
+
+  if (error)
+    bfd_set_error (bfd_error_bad_value);
+
+  return !error;
+}
+
+
+boolean
+frv_elf_print_private_bfd_data (abfd, ptr)
+     bfd *abfd;
+     PTR ptr;
+{
+  FILE *file = (FILE *) ptr;
+  flagword flags;
+
+  BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+  /* Print normal ELF private data.  */
+  _bfd_elf_print_private_bfd_data (abfd, ptr);
+
+  flags = elf_elfheader (abfd)->e_flags;
+  fprintf (file, _("private flags = 0x%lx:"), (long)flags);
+
+  switch (flags & EF_FRV_CPU_MASK)
+    {
+    default:							break;
+    case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple");	break;
+    case EF_FRV_CPU_FR500:  fprintf (file, " -mcpu=fr500");	break;
+    case EF_FRV_CPU_FR400:  fprintf (file, " -mcpu=fr400");	break;
+    case EF_FRV_CPU_FR300:  fprintf (file, " -mcpu=fr300");	break;
+    case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat");	break;
+    }
+
+  switch (flags & EF_FRV_GPR_MASK)
+    {
+    default:							break;
+    case EF_FRV_GPR_32: fprintf (file, " -mgpr-32");		break;
+    case EF_FRV_GPR_64: fprintf (file, " -mgpr-64");		break;
+    }
+
+  switch (flags & EF_FRV_FPR_MASK)
+    {
+    default:							break;
+    case EF_FRV_FPR_32:   fprintf (file, " -mfpr-32");		break;
+    case EF_FRV_FPR_64:   fprintf (file, " -mfpr-64");		break;
+    case EF_FRV_FPR_NONE: fprintf (file, " -msoft-float");	break;
+    }
+
+  switch (flags & EF_FRV_DWORD_MASK)
+    {
+    default:							break;
+    case EF_FRV_DWORD_YES: fprintf (file, " -mdword");		break;
+    case EF_FRV_DWORD_NO:  fprintf (file, " -mno-dword");	break;
+    }
+
+  if (flags & EF_FRV_DOUBLE)
+    fprintf (file, " -mdouble");
+
+  if (flags & EF_FRV_MEDIA)
+    fprintf (file, " -mmedia");
+
+  if (flags & EF_FRV_MULADD)
+    fprintf (file, " -mmuladd");
+
+  if (flags & EF_FRV_PIC)
+    fprintf (file, " -fpic");
+
+  if (flags & EF_FRV_BIGPIC)
+    fprintf (file, " -fPIC");
+
+  if (flags & EF_FRV_NON_PIC_RELOCS)
+    fprintf (file, " non-pic relocations");
+
+  if (flags & EF_FRV_G0)
+    fprintf (file, " -G0");
+
+  fputc ('\n', file);
+  return true;
+}
+
+
+#define ELF_ARCH		bfd_arch_frv
+#define ELF_MACHINE_CODE	EM_CYGNUS_FRV
+#define ELF_MAXPAGESIZE		0x1000
+
+#define TARGET_BIG_SYM          bfd_elf32_frv_vec
+#define TARGET_BIG_NAME		"elf32-frv"
+
+#define elf_info_to_howto_rel			NULL
+#define elf_info_to_howto			frv_info_to_howto_rela
+#define elf_backend_relocate_section		elf32_frv_relocate_section
+#define elf_backend_gc_mark_hook		elf32_frv_gc_mark_hook
+#define elf_backend_gc_sweep_hook		elf32_frv_gc_sweep_hook
+#define elf_backend_check_relocs                elf32_frv_check_relocs
+#define elf_backend_object_p			elf32_frv_object_p
+#define elf_backend_add_symbol_hook             elf32_frv_add_symbol_hook
+
+#define elf_backend_can_gc_sections		1
+
+#define bfd_elf32_bfd_reloc_type_lookup		frv_reloc_type_lookup
+#define bfd_elf32_bfd_set_private_flags		frv_elf_set_private_flags
+#define bfd_elf32_bfd_copy_private_bfd_data	frv_elf_copy_private_bfd_data
+#define bfd_elf32_bfd_merge_private_bfd_data	frv_elf_merge_private_bfd_data
+#define bfd_elf32_bfd_print_private_bfd_data	frv_elf_print_private_bfd_data
+
+#include "elf32-target.h"

--- /dev/null
+++ b/include/elf/frv.h
@@ -0,0 +1,95 @@
+/* FRV ELF support for BFD.
+   Copyright (C) 2002 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _ELF_FRV_H
+#define _ELF_FRV_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_frv_reloc_type)
+  RELOC_NUMBER (R_FRV_NONE, 0)
+  RELOC_NUMBER (R_FRV_32, 1)
+  RELOC_NUMBER (R_FRV_LABEL16, 2)
+  RELOC_NUMBER (R_FRV_LABEL24, 3)
+  RELOC_NUMBER (R_FRV_LO16, 4)
+  RELOC_NUMBER (R_FRV_HI16, 5)
+  RELOC_NUMBER (R_FRV_GPREL12, 6)
+  RELOC_NUMBER (R_FRV_GPRELU12, 7)
+  RELOC_NUMBER (R_FRV_GPREL32, 8)
+  RELOC_NUMBER (R_FRV_GPRELHI, 9)
+  RELOC_NUMBER (R_FRV_GPRELLO, 10)
+  RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200)
+  RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201)
+END_RELOC_NUMBERS(R_FRV_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+						/* gpr support */
+#define EF_FRV_GPR_MASK		0x00000003	/* mask for # of gprs */
+#define EF_FRV_GPR_32		0x00000001	/* -mgpr-32 */
+#define EF_FRV_GPR_64		0x00000002	/* -mgpr-64 */
+
+						/* fpr support */
+#define EF_FRV_FPR_MASK		0x0000000c	/* mask for # of fprs */
+#define EF_FRV_FPR_32		0x00000004	/* -mfpr-32 */
+#define EF_FRV_FPR_64		0x00000008	/* -mfpr-64 */
+#define EF_FRV_FPR_NONE		0x0000000c	/* -msoft-float */
+
+						/* double word support */
+#define EF_FRV_DWORD_MASK	0x00000030	/* mask for dword support */
+#define EF_FRV_DWORD_YES	0x00000010	/* use double word insns */
+#define EF_FRV_DWORD_NO		0x00000020	/* don't use double word insn*/
+
+#define EF_FRV_DOUBLE		0x00000040	/* -mdouble */
+#define EF_FRV_MEDIA		0x00000080	/* -mmedia */
+
+#define EF_FRV_PIC		0x00000100	/* -fpic */
+#define EF_FRV_NON_PIC_RELOCS	0x00000200	/* used non pic safe relocs */
+
+#define EF_FRV_MULADD		0x00000400	/* -mmuladd */
+#define EF_FRV_BIGPIC		0x00000800	/* -fPIC */
+#define	EF_FRV_LIBPIC		0x00001000	/* -mlibrary-pic */
+#define EF_FRV_G0		0x00002000	/* -G 0, no small data ptr */
+#define EF_FRV_NOPACK		0x00004000	/* -mnopack */
+
+#define	EF_FRV_CPU_MASK		0xff000000	/* specific cpu bits */
+#define EF_FRV_CPU_GENERIC	0x00000000	/* generic FRV */
+#define EF_FRV_CPU_FR500	0x01000000	/* FRV500 */
+#define EF_FRV_CPU_FR300	0x02000000	/* FRV300 */
+#define EF_FRV_CPU_SIMPLE	0x03000000	/* SIMPLE */
+#define EF_FRV_CPU_TOMCAT	0x04000000	/* Tomcat, FR500 prototype */
+#define EF_FRV_CPU_FR400	0x05000000	/* FRV400 */
+
+						/* Mask of PIC related bits */
+#define	EF_FRV_PIC_FLAGS	(EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC)
+
+						/* Mask of all flags */
+#define EF_FRV_ALL_FLAGS	(EF_FRV_GPR_MASK | \
+				 EF_FRV_FPR_MASK | \
+				 EF_FRV_DWORD_MASK | \
+				 EF_FRV_DOUBLE | \
+				 EF_FRV_MEDIA | \
+				 EF_FRV_PIC_FLAGS | \
+				 EF_FRV_NON_PIC_RELOCS | \
+				 EF_FRV_MULADD | \
+				 EF_FRV_G0 | \
+				 EF_FRV_NOPACK | \
+				 EF_FRV_CPU_MASK)
+
+#endif /* _ELF_FRV_H */

--- /dev/null
+++ b/opcodes/frv-asm.c
@@ -0,0 +1,1023 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-asm.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+
+/* -- assembler routines inserted here.  */
+
+/* -- asm.c */
+static const char * parse_ulo16
+  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_uslo16
+  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_uhi16
+  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static long parse_register_number
+  PARAMS ((const char **));
+static const char * parse_spr
+  PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
+static const char * parse_d12
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_s12
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_u12
+  PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+
+static const char *
+parse_ulo16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+	{
+	  *strp += 4;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing `)'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      if (strncasecmp (*strp + 1, "gprello(", 8) == 0)
+	{
+	  *strp += 9;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+    }
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_uslo16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "lo(", 3) == 0)
+	{
+	  *strp += 4;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing `)'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gprello(", 8) == 0)
+	{
+	  *strp += 9;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value &= 0xffff;
+	  *valuep = value;
+	  return errmsg;
+	}
+    }
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_uhi16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "hi(", 3) == 0)
+	{
+	  *strp += 4;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing `)'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+      else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0)
+	{
+	  *strp += 9;
+	  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI,
+				       &result_type, &value);
+	  if (**strp != ')')
+	    return "missing ')'";
+	  ++*strp;
+	  if (errmsg == NULL
+	      && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	    value >>= 16;
+	  *valuep = value;
+	  return errmsg;
+	}
+    }
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+static long
+parse_register_number (strp)
+     const char **strp;
+{
+  int regno;
+  if (**strp < '0' || **strp > '9')
+    return -1; /* error */
+
+  regno = **strp - '0';
+  for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp)
+    regno = regno * 10 + (**strp - '0');
+
+  return regno;
+}
+
+static const char *
+parse_spr (cd, strp, table, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     CGEN_KEYWORD * table;
+     long *valuep;
+{
+  const char *save_strp;
+  long regno;
+
+  /* Check for spr index notation.  */
+  if (strncasecmp (*strp, "spr[", 4) == 0)
+    {
+      *strp += 4;
+      regno = parse_register_number (strp);
+      if (**strp != ']')
+        return "missing `]'";
+      ++*strp;
+      if (! spr_valid (regno))
+	return "Special purpose register number is out of range";
+      *valuep = regno;
+      return NULL;
+    }
+
+  save_strp = *strp;
+  regno = parse_register_number (strp);
+  if (regno != -1)
+    {
+      if (! spr_valid (regno))
+	return "Special purpose register number is out of range";
+      *valuep = regno;
+      return NULL;
+    }
+
+  *strp = save_strp;
+  return cgen_parse_keyword (cd, strp, table, valuep);
+}
+
+static const char *
+parse_d12 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if (**strp == '#' || **strp == '%')
+    {
+      if (strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+        {
+          *strp += 9;
+          errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12,
+                                       &result_type, &value);
+          if (**strp != ')')
+            return "missing `)'";
+          ++*strp;
+          *valuep = value;
+          return errmsg;
+        }
+    }
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+static const char *
+parse_s12 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if ((**strp == '#' || **strp == '%')
+      && strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+    {
+      *strp += 9;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12,
+                                    &result_type, &value);
+      if (**strp != ')')
+        return "missing `)'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else
+    {
+      if (**strp == '#')
+        ++*strp;
+      return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+    }
+}
+
+static const char *
+parse_u12 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+ 
+  /* Check for small data reference.  */
+  if ((**strp == '#' || **strp == '%')
+      && strncasecmp (*strp + 1, "gprel12(", 8) == 0)
+    {
+      *strp += 9;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12,
+                                    &result_type, &value);
+      if (**strp != ')')
+        return "missing `)'";
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+  else
+    {
+      if (**strp == '#')
+        ++*strp;
+      return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+    }
+}
+
+/* -- */
+
+const char * frv_cgen_parse_operand
+  PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  */
+
+const char *
+frv_cgen_parse_operand (cd, opindex, strp, fields)
+     CGEN_CPU_DESC cd;
+     int opindex;
+     const char ** strp;
+     CGEN_FIELDS * fields;
+{
+  const char * errmsg = NULL;
+  /* Used by scalar operands that still need to be parsed.  */
+  long junk ATTRIBUTE_UNUSED;
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A);
+      break;
+    case FRV_OPERAND_ACC40SI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si);
+      break;
+    case FRV_OPERAND_ACC40SK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Sk);
+      break;
+    case FRV_OPERAND_ACC40UI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Ui);
+      break;
+    case FRV_OPERAND_ACC40UK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Uk);
+      break;
+    case FRV_OPERAND_ACCGI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGi);
+      break;
+    case FRV_OPERAND_ACCGK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGk);
+      break;
+    case FRV_OPERAND_CCI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CCi);
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk);
+      break;
+    case FRV_OPERAND_CPRI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRi);
+      break;
+    case FRV_OPERAND_CPRJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRj);
+      break;
+    case FRV_OPERAND_CPRK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk);
+      break;
+    case FRV_OPERAND_CRI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRi);
+      break;
+    case FRV_OPERAND_CRJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj);
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_float);
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_int);
+      break;
+    case FRV_OPERAND_CRK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRk);
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_1);
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_2);
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_3);
+      break;
+    case FRV_OPERAND_FCCK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCk);
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRINTI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRINTJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRINTK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRKHI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRKLO :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRi);
+      break;
+    case FRV_OPERAND_GRJ :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRj);
+      break;
+    case FRV_OPERAND_GRK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRKHI :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRKLO :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_1);
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_2);
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_3);
+      break;
+    case FRV_OPERAND_LI :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI);
+      break;
+    case FRV_OPERAND_AE :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae);
+      break;
+    case FRV_OPERAND_CCOND :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_CCOND, &fields->f_ccond);
+      break;
+    case FRV_OPERAND_COND :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_COND, &fields->f_cond);
+      break;
+    case FRV_OPERAND_D12 :
+      errmsg = parse_d12 (cd, strp, FRV_OPERAND_D12, &fields->f_d12);
+      break;
+    case FRV_OPERAND_DEBUG :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_DEBUG, &fields->f_debug);
+      break;
+    case FRV_OPERAND_EIR :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_EIR, &fields->f_eir);
+      break;
+    case FRV_OPERAND_HINT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_HINT, &fields->f_hint);
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_not_taken, & fields->f_hint);
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_taken, & fields->f_hint);
+      break;
+    case FRV_OPERAND_LABEL16 :
+      {
+        bfd_vma value;
+        errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL,  & value);
+        fields->f_label16 = value;
+      }
+      break;
+    case FRV_OPERAND_LABEL24 :
+      {
+        bfd_vma value;
+        errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL24, 0, NULL,  & value);
+        fields->f_label24 = value;
+      }
+      break;
+    case FRV_OPERAND_LOCK :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LOCK, &fields->f_lock);
+      break;
+    case FRV_OPERAND_PACK :
+      errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_pack, & fields->f_pack);
+      break;
+    case FRV_OPERAND_S10 :
+      errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S10, &fields->f_s10);
+      break;
+    case FRV_OPERAND_S12 :
+      errmsg = parse_s12 (cd, strp, FRV_OPERAND_S12, &fields->f_d12);
+      break;
+    case FRV_OPERAND_S16 :
+      errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S16, &fields->f_s16);
+      break;
+    case FRV_OPERAND_S5 :
+      errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S5, &fields->f_s5);
+      break;
+    case FRV_OPERAND_S6 :
+      errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6, &fields->f_s6);
+      break;
+    case FRV_OPERAND_S6_1 :
+      errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6_1, &fields->f_s6_1);
+      break;
+    case FRV_OPERAND_SLO16 :
+      errmsg = parse_uslo16 (cd, strp, FRV_OPERAND_SLO16, &fields->f_s16);
+      break;
+    case FRV_OPERAND_SPR :
+      errmsg = parse_spr (cd, strp, & frv_cgen_opval_spr_names, & fields->f_spr);
+      break;
+    case FRV_OPERAND_U12 :
+      errmsg = parse_u12 (cd, strp, FRV_OPERAND_U12, &fields->f_u12);
+      break;
+    case FRV_OPERAND_U16 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U16, &fields->f_u16);
+      break;
+    case FRV_OPERAND_U6 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U6, &fields->f_u6);
+      break;
+    case FRV_OPERAND_UHI16 :
+      errmsg = parse_uhi16 (cd, strp, FRV_OPERAND_UHI16, &fields->f_u16);
+      break;
+    case FRV_OPERAND_ULO16 :
+      errmsg = parse_ulo16 (cd, strp, FRV_OPERAND_ULO16, &fields->f_u16);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * const frv_cgen_parse_handlers[] = 
+{
+  parse_insn_normal,
+};
+
+void
+frv_cgen_init_asm (cd)
+     CGEN_CPU_DESC cd;
+{
+  frv_cgen_init_opcode_table (cd);
+  frv_cgen_init_ibld_table (cd);
+  cd->parse_handlers = & frv_cgen_parse_handlers[0];
+  cd->parse_operand = frv_cgen_parse_operand;
+}
+
+
+
+/* Regex construction routine.
+
+   This translates an opcode syntax string into a regex string,
+   by replacing any non-character syntax element (such as an
+   opcode) with the pattern '.*'
+
+   It then compiles the regex and stores it in the opcode, for
+   later use by frv_cgen_assemble_insn
+
+   Returns NULL for success, an error message for failure.  */
+
+char * 
+frv_cgen_build_insn_regex (insn)
+     CGEN_INSN *insn;
+{  
+  CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+  const char *mnem = CGEN_INSN_MNEMONIC (insn);
+  char rxbuf[CGEN_MAX_RX_ELEMENTS];
+  char *rx = rxbuf;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+  int reg_err;
+
+  syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+  /* Mnemonics come first in the syntax string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    return _("missing mnemonic in syntax string");
+  ++syn;
+
+  /* Generate a case sensitive regular expression that emulates case
+     insensitive matching in the "C" locale.  We cannot generate a case
+     insensitive regular expression because in Turkish locales, 'i' and 'I'
+     are not equal modulo case conversion.  */
+
+  /* Copy the literal mnemonic out of the insn.  */
+  for (; *mnem; mnem++)
+    {
+      char c = *mnem;
+
+      if (ISALPHA (c))
+	{
+	  *rx++ = '[';
+	  *rx++ = TOLOWER (c);
+	  *rx++ = TOUPPER (c);
+	  *rx++ = ']';
+	}
+      else
+	*rx++ = c;
+    }
+
+  /* Copy any remaining literals from the syntax string into the rx.  */
+  for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+    {
+      if (CGEN_SYNTAX_CHAR_P (* syn)) 
+	{
+	  char c = CGEN_SYNTAX_CHAR (* syn);
+
+	  switch (c) 
+	    {
+	      /* Escape any regex metacharacters in the syntax.  */
+	    case '.': case '[': case '\\': 
+	    case '*': case '^': case '$': 
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+	    case '?': case '{': case '}': 
+	    case '(': case ')': case '*':
+	    case '|': case '+': case ']':
+#endif
+	      *rx++ = '\\';
+	      *rx++ = c;
+	      break;
+
+	    default:
+	      if (ISALPHA (c))
+		{
+		  *rx++ = '[';
+		  *rx++ = TOLOWER (c);
+		  *rx++ = TOUPPER (c);
+		  *rx++ = ']';
+		}
+	      else
+		*rx++ = c;
+	      break;
+	    }
+	}
+      else
+	{
+	  /* Replace non-syntax fields with globs.  */
+	  *rx++ = '.';
+	  *rx++ = '*';
+	}
+    }
+
+  /* Trailing whitespace ok.  */
+  * rx++ = '['; 
+  * rx++ = ' '; 
+  * rx++ = '\t'; 
+  * rx++ = ']'; 
+  * rx++ = '*'; 
+
+  /* But anchor it after that.  */
+  * rx++ = '$'; 
+  * rx = '\0';
+
+  CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+  reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+  if (reg_err == 0) 
+    return NULL;
+  else
+    {
+      static char msg[80];
+
+      regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+      regfree ((regex_t *) CGEN_INSN_RX (insn));
+      free (CGEN_INSN_RX (insn));
+      (CGEN_INSN_RX (insn)) = NULL;
+      return msg;
+    }
+}
+
+
+/* Default insn parser.
+
+   The syntax string is scanned and operands are parsed and stored in FIELDS.
+   Relocs are queued as we go via other callbacks.
+
+   ??? Note that this is currently an all-or-nothing parser.  If we fail to
+   parse the instruction, we return 0 and the caller will start over from
+   the beginning.  Backtracking will be necessary in parsing subexpressions,
+   but that can be handled there.  Not handling backtracking here may get
+   expensive in the case of the m68k.  Deal with later.
+
+   Returns NULL for success, an error message for failure.  */
+
+static const char *
+parse_insn_normal (cd, insn, strp, fields)
+     CGEN_CPU_DESC cd;
+     const CGEN_INSN *insn;
+     const char **strp;
+     CGEN_FIELDS *fields;
+{
+  /* ??? Runtime added insns not handled yet.  */
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const char *str = *strp;
+  const char *errmsg;
+  const char *p;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+  /* FIXME: wip */
+  int past_opcode_p;
+#endif
+
+  /* For now we assume the mnemonic is first (there are no leading operands).
+     We can parse it without needing to set up operand parsing.
+     GAS's input scrubber will ensure mnemonics are lowercase, but we may
+     not be called from GAS.  */
+  p = CGEN_INSN_MNEMONIC (insn);
+  while (*p && TOLOWER (*p) == TOLOWER (*str))
+    ++p, ++str;
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && ! ISSPACE (* str))
+    return _("unrecognized instruction");
+#endif
+
+  CGEN_INIT_PARSE (cd);
+  cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+  past_opcode_p = 0;
+#endif
+
+  /* We don't check for (*str != '\0') here because we want to parse
+     any trailing fake arguments in the syntax string.  */
+  syn = CGEN_SYNTAX_STRING (syntax);
+
+  /* Mnemonics come first for now, ensure valid string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    abort ();
+
+  ++syn;
+
+  while (* syn != 0)
+    {
+      /* Non operand chars must match exactly.  */
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
+	  if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+	    {
+#ifdef CGEN_MNEMONIC_OPERANDS
+	      if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+		past_opcode_p = 1;
+#endif
+	      ++ syn;
+	      ++ str;
+	    }
+	  else if (*str)
+	    {
+	      /* Syntax char didn't match.  Can't be this insn.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+		       CGEN_SYNTAX_CHAR(*syn), *str);
+	      return msg;
+	    }
+	  else
+	    {
+	      /* Ran out of input.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+		       CGEN_SYNTAX_CHAR(*syn));
+	      return msg;
+	    }
+	  continue;
+	}
+
+      /* We have an operand of some sort.  */
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+					  &str, fields);
+      if (errmsg)
+	return errmsg;
+
+      /* Done with this operand, continue with next one.  */
+      ++ syn;
+    }
+
+  /* If we're at the end of the syntax string, we're done.  */
+  if (* syn == 0)
+    {
+      /* FIXME: For the moment we assume a valid `str' can only contain
+	 blanks now.  IE: We needn't try again with a longer version of
+	 the insn and it is assumed that longer versions of insns appear
+	 before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+      while (ISSPACE (* str))
+	++ str;
+
+      if (* str != '\0')
+	return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+      return NULL;
+    }
+
+  /* We couldn't parse it.  */
+  return _("unrecognized instruction");
+}
+
+/* Main entry point.
+   This routine is called for each instruction to be assembled.
+   STR points to the insn to be assembled.
+   We assume all necessary tables have been initialized.
+   The assembled instruction, less any fixups, is stored in BUF.
+   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+   still needs to be converted to target byte order, otherwise BUF is an array
+   of bytes in target byte order.
+   The result is a pointer to the insn's entry in the opcode table,
+   or NULL if an error occured (an error message will have already been
+   printed).
+
+   Note that when processing (non-alias) macro-insns,
+   this function recurses.
+
+   ??? It's possible to make this cpu-independent.
+   One would have to deal with a few minor things.
+   At this point in time doing so would be more of a curiosity than useful
+   [for example this file isn't _that_ big], but keeping the possibility in
+   mind helps keep the design clean.  */
+
+const CGEN_INSN *
+frv_cgen_assemble_insn (cd, str, fields, buf, errmsg)
+     CGEN_CPU_DESC cd;
+     const char *str;
+     CGEN_FIELDS *fields;
+     CGEN_INSN_BYTES_PTR buf;
+     char **errmsg;
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *parse_errmsg = NULL;
+  const char *insert_errmsg = NULL;
+  int recognized_mnemonic = 0;
+
+  /* Skip leading white space.  */
+  while (ISSPACE (* str))
+    ++ str;
+
+  /* The instructions are stored in hashed lists.
+     Get the first in the list.  */
+  ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+  /* Keep looking until we find a match.  */
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not usually needed as unsupported opcodes
+	 shouldn't be in the hash lists.  */
+      /* Is this insn supported by the selected cpu?  */
+      if (! frv_cgen_insn_supported (cd, insn))
+	continue;
+#endif
+      /* If the RELAX attribute is set, this is an insn that shouldn't be
+	 chosen immediately.  Instead, it is used during assembler/linker
+	 relaxation if possible.  */
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+	continue;
+
+      str = start;
+
+      /* Skip this insn if str doesn't look right lexically.  */
+      if (CGEN_INSN_RX (insn) != NULL &&
+	  regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	continue;
+
+      /* Allow parse/insert handlers to obtain length of insn.  */
+      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+      parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+      if (parse_errmsg != NULL)
+	continue;
+
+      /* ??? 0 is passed for `pc'.  */
+      insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+						 (bfd_vma) 0);
+      if (insert_errmsg != NULL)
+        continue;
+
+      /* It is up to the caller to actually output the insn and any
+         queued relocs.  */
+      return insn;
+    }
+
+  {
+    static char errbuf[150];
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+    const char *tmp_errmsg;
+
+    /* If requesting verbose error messages, use insert_errmsg.
+       Failing that, use parse_errmsg.  */
+    tmp_errmsg = (insert_errmsg ? insert_errmsg :
+		  parse_errmsg ? parse_errmsg :
+		  recognized_mnemonic ?
+		  _("unrecognized form of instruction") :
+		  _("unrecognized instruction"));
+
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+      
+    *errmsg = errbuf;
+    return NULL;
+  }
+}
+
+#if 0 /* This calls back to GAS which we can't do without care.  */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+   This lets GAS parse registers for us.
+   ??? Interesting idea but not currently used.  */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+   FIXME: Not currently used.  */
+
+void
+frv_cgen_asm_hash_keywords (cd, opvals)
+     CGEN_CPU_DESC cd;
+     CGEN_KEYWORD *opvals;
+{
+  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
+  const CGEN_KEYWORD_ENTRY * ke;
+
+  while ((ke = cgen_keyword_search_next (& search)) != NULL)
+    {
+#if 0 /* Unnecessary, should be done in the search routine.  */
+      if (! frv_cgen_opval_supported (ke))
+	continue;
+#endif
+      cgen_asm_record_register (cd, ke->name, ke->value);
+    }
+}
+
+#endif /* 0 */

--- /dev/null
+++ b/opcodes/frv-desc.c
@@ -0,0 +1,6311 @@
+/* CPU data for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+  { "#f", 0 },
+  { "#t", 1 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+  { "base", MACH_BASE },
+  { "frv", MACH_FRV },
+  { "fr500", MACH_FR500 },
+  { "fr400", MACH_FR400 },
+  { "tomcat", MACH_TOMCAT },
+  { "simple", MACH_SIMPLE },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+  { "frv", ISA_FRV },
+  { "max", ISA_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY UNIT_attr[] =
+{
+  { "NIL", UNIT_NIL },
+  { "I0", UNIT_I0 },
+  { "I1", UNIT_I1 },
+  { "I01", UNIT_I01 },
+  { "FM0", UNIT_FM0 },
+  { "FM1", UNIT_FM1 },
+  { "FM01", UNIT_FM01 },
+  { "B0", UNIT_B0 },
+  { "B1", UNIT_B1 },
+  { "B01", UNIT_B01 },
+  { "C", UNIT_C },
+  { "MULT_DIV", UNIT_MULT_DIV },
+  { "LOAD", UNIT_LOAD },
+  { "NUM_UNITS", UNIT_NUM_UNITS },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] =
+{
+  { "NONE", FR400_MAJOR_NONE },
+  { "I_1", FR400_MAJOR_I_1 },
+  { "I_2", FR400_MAJOR_I_2 },
+  { "I_3", FR400_MAJOR_I_3 },
+  { "I_4", FR400_MAJOR_I_4 },
+  { "I_5", FR400_MAJOR_I_5 },
+  { "B_1", FR400_MAJOR_B_1 },
+  { "B_2", FR400_MAJOR_B_2 },
+  { "B_3", FR400_MAJOR_B_3 },
+  { "B_4", FR400_MAJOR_B_4 },
+  { "B_5", FR400_MAJOR_B_5 },
+  { "B_6", FR400_MAJOR_B_6 },
+  { "C_1", FR400_MAJOR_C_1 },
+  { "C_2", FR400_MAJOR_C_2 },
+  { "M_1", FR400_MAJOR_M_1 },
+  { "M_2", FR400_MAJOR_M_2 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
+{
+  { "NONE", FR500_MAJOR_NONE },
+  { "I_1", FR500_MAJOR_I_1 },
+  { "I_2", FR500_MAJOR_I_2 },
+  { "I_3", FR500_MAJOR_I_3 },
+  { "I_4", FR500_MAJOR_I_4 },
+  { "I_5", FR500_MAJOR_I_5 },
+  { "I_6", FR500_MAJOR_I_6 },
+  { "B_1", FR500_MAJOR_B_1 },
+  { "B_2", FR500_MAJOR_B_2 },
+  { "B_3", FR500_MAJOR_B_3 },
+  { "B_4", FR500_MAJOR_B_4 },
+  { "B_5", FR500_MAJOR_B_5 },
+  { "B_6", FR500_MAJOR_B_6 },
+  { "C_1", FR500_MAJOR_C_1 },
+  { "C_2", FR500_MAJOR_C_2 },
+  { "F_1", FR500_MAJOR_F_1 },
+  { "F_2", FR500_MAJOR_F_2 },
+  { "F_3", FR500_MAJOR_F_3 },
+  { "F_4", FR500_MAJOR_F_4 },
+  { "F_5", FR500_MAJOR_F_5 },
+  { "F_6", FR500_MAJOR_F_6 },
+  { "F_7", FR500_MAJOR_F_7 },
+  { "F_8", FR500_MAJOR_F_8 },
+  { "M_1", FR500_MAJOR_M_1 },
+  { "M_2", FR500_MAJOR_M_2 },
+  { "M_3", FR500_MAJOR_M_3 },
+  { "M_4", FR500_MAJOR_M_4 },
+  { "M_5", FR500_MAJOR_M_5 },
+  { "M_6", FR500_MAJOR_M_6 },
+  { "M_7", FR500_MAJOR_M_7 },
+  { "M_8", FR500_MAJOR_M_8 },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "RESERVED", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "PC", &bool_attr[0], &bool_attr[0] },
+  { "PROFILE", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
+  { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
+  { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
+  { "ALIAS", &bool_attr[0], &bool_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+  { "PBB", &bool_attr[0], &bool_attr[0] },
+  { "PRIVILEGED", &bool_attr[0], &bool_attr[0] },
+  { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] },
+  { "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
+  { "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
+  { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+/* Instruction set variants.  */
+
+static const CGEN_ISA frv_cgen_isa_table[] = {
+  { "frv", 32, 32, 32, 32 },
+  { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants.  */
+
+static const CGEN_MACH frv_cgen_mach_table[] = {
+  { "frv", "frv", MACH_FRV, 0 },
+  { "fr500", "fr500", MACH_FR500, 0 },
+  { "tomcat", "tomcat", MACH_TOMCAT, 0 },
+  { "fr400", "fr400", MACH_FR400, 0 },
+  { "simple", "simple", MACH_SIMPLE, 0 },
+  { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
+{
+  { "sp", 1, {0, {0}}, 0, 0 },
+  { "fp", 2, {0, {0}}, 0, 0 },
+  { "gr0", 0, {0, {0}}, 0, 0 },
+  { "gr1", 1, {0, {0}}, 0, 0 },
+  { "gr2", 2, {0, {0}}, 0, 0 },
+  { "gr3", 3, {0, {0}}, 0, 0 },
+  { "gr4", 4, {0, {0}}, 0, 0 },
+  { "gr5", 5, {0, {0}}, 0, 0 },
+  { "gr6", 6, {0, {0}}, 0, 0 },
+  { "gr7", 7, {0, {0}}, 0, 0 },
+  { "gr8", 8, {0, {0}}, 0, 0 },
+  { "gr9", 9, {0, {0}}, 0, 0 },
+  { "gr10", 10, {0, {0}}, 0, 0 },
+  { "gr11", 11, {0, {0}}, 0, 0 },
+  { "gr12", 12, {0, {0}}, 0, 0 },
+  { "gr13", 13, {0, {0}}, 0, 0 },
+  { "gr14", 14, {0, {0}}, 0, 0 },
+  { "gr15", 15, {0, {0}}, 0, 0 },
+  { "gr16", 16, {0, {0}}, 0, 0 },
+  { "gr17", 17, {0, {0}}, 0, 0 },
+  { "gr18", 18, {0, {0}}, 0, 0 },
+  { "gr19", 19, {0, {0}}, 0, 0 },
+  { "gr20", 20, {0, {0}}, 0, 0 },
+  { "gr21", 21, {0, {0}}, 0, 0 },
+  { "gr22", 22, {0, {0}}, 0, 0 },
+  { "gr23", 23, {0, {0}}, 0, 0 },
+  { "gr24", 24, {0, {0}}, 0, 0 },
+  { "gr25", 25, {0, {0}}, 0, 0 },
+  { "gr26", 26, {0, {0}}, 0, 0 },
+  { "gr27", 27, {0, {0}}, 0, 0 },
+  { "gr28", 28, {0, {0}}, 0, 0 },
+  { "gr29", 29, {0, {0}}, 0, 0 },
+  { "gr30", 30, {0, {0}}, 0, 0 },
+  { "gr31", 31, {0, {0}}, 0, 0 },
+  { "gr32", 32, {0, {0}}, 0, 0 },
+  { "gr33", 33, {0, {0}}, 0, 0 },
+  { "gr34", 34, {0, {0}}, 0, 0 },
+  { "gr35", 35, {0, {0}}, 0, 0 },
+  { "gr36", 36, {0, {0}}, 0, 0 },
+  { "gr37", 37, {0, {0}}, 0, 0 },
+  { "gr38", 38, {0, {0}}, 0, 0 },
+  { "gr39", 39, {0, {0}}, 0, 0 },
+  { "gr40", 40, {0, {0}}, 0, 0 },
+  { "gr41", 41, {0, {0}}, 0, 0 },
+  { "gr42", 42, {0, {0}}, 0, 0 },
+  { "gr43", 43, {0, {0}}, 0, 0 },
+  { "gr44", 44, {0, {0}}, 0, 0 },
+  { "gr45", 45, {0, {0}}, 0, 0 },
+  { "gr46", 46, {0, {0}}, 0, 0 },
+  { "gr47", 47, {0, {0}}, 0, 0 },
+  { "gr48", 48, {0, {0}}, 0, 0 },
+  { "gr49", 49, {0, {0}}, 0, 0 },
+  { "gr50", 50, {0, {0}}, 0, 0 },
+  { "gr51", 51, {0, {0}}, 0, 0 },
+  { "gr52", 52, {0, {0}}, 0, 0 },
+  { "gr53", 53, {0, {0}}, 0, 0 },
+  { "gr54", 54, {0, {0}}, 0, 0 },
+  { "gr55", 55, {0, {0}}, 0, 0 },
+  { "gr56", 56, {0, {0}}, 0, 0 },
+  { "gr57", 57, {0, {0}}, 0, 0 },
+  { "gr58", 58, {0, {0}}, 0, 0 },
+  { "gr59", 59, {0, {0}}, 0, 0 },
+  { "gr60", 60, {0, {0}}, 0, 0 },
+  { "gr61", 61, {0, {0}}, 0, 0 },
+  { "gr62", 62, {0, {0}}, 0, 0 },
+  { "gr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_gr_names =
+{
+  & frv_cgen_opval_gr_names_entries[0],
+  66,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] =
+{
+  { "fr0", 0, {0, {0}}, 0, 0 },
+  { "fr1", 1, {0, {0}}, 0, 0 },
+  { "fr2", 2, {0, {0}}, 0, 0 },
+  { "fr3", 3, {0, {0}}, 0, 0 },
+  { "fr4", 4, {0, {0}}, 0, 0 },
+  { "fr5", 5, {0, {0}}, 0, 0 },
+  { "fr6", 6, {0, {0}}, 0, 0 },
+  { "fr7", 7, {0, {0}}, 0, 0 },
+  { "fr8", 8, {0, {0}}, 0, 0 },
+  { "fr9", 9, {0, {0}}, 0, 0 },
+  { "fr10", 10, {0, {0}}, 0, 0 },
+  { "fr11", 11, {0, {0}}, 0, 0 },
+  { "fr12", 12, {0, {0}}, 0, 0 },
+  { "fr13", 13, {0, {0}}, 0, 0 },
+  { "fr14", 14, {0, {0}}, 0, 0 },
+  { "fr15", 15, {0, {0}}, 0, 0 },
+  { "fr16", 16, {0, {0}}, 0, 0 },
+  { "fr17", 17, {0, {0}}, 0, 0 },
+  { "fr18", 18, {0, {0}}, 0, 0 },
+  { "fr19", 19, {0, {0}}, 0, 0 },
+  { "fr20", 20, {0, {0}}, 0, 0 },
+  { "fr21", 21, {0, {0}}, 0, 0 },
+  { "fr22", 22, {0, {0}}, 0, 0 },
+  { "fr23", 23, {0, {0}}, 0, 0 },
+  { "fr24", 24, {0, {0}}, 0, 0 },
+  { "fr25", 25, {0, {0}}, 0, 0 },
+  { "fr26", 26, {0, {0}}, 0, 0 },
+  { "fr27", 27, {0, {0}}, 0, 0 },
+  { "fr28", 28, {0, {0}}, 0, 0 },
+  { "fr29", 29, {0, {0}}, 0, 0 },
+  { "fr30", 30, {0, {0}}, 0, 0 },
+  { "fr31", 31, {0, {0}}, 0, 0 },
+  { "fr32", 32, {0, {0}}, 0, 0 },
+  { "fr33", 33, {0, {0}}, 0, 0 },
+  { "fr34", 34, {0, {0}}, 0, 0 },
+  { "fr35", 35, {0, {0}}, 0, 0 },
+  { "fr36", 36, {0, {0}}, 0, 0 },
+  { "fr37", 37, {0, {0}}, 0, 0 },
+  { "fr38", 38, {0, {0}}, 0, 0 },
+  { "fr39", 39, {0, {0}}, 0, 0 },
+  { "fr40", 40, {0, {0}}, 0, 0 },
+  { "fr41", 41, {0, {0}}, 0, 0 },
+  { "fr42", 42, {0, {0}}, 0, 0 },
+  { "fr43", 43, {0, {0}}, 0, 0 },
+  { "fr44", 44, {0, {0}}, 0, 0 },
+  { "fr45", 45, {0, {0}}, 0, 0 },
+  { "fr46", 46, {0, {0}}, 0, 0 },
+  { "fr47", 47, {0, {0}}, 0, 0 },
+  { "fr48", 48, {0, {0}}, 0, 0 },
+  { "fr49", 49, {0, {0}}, 0, 0 },
+  { "fr50", 50, {0, {0}}, 0, 0 },
+  { "fr51", 51, {0, {0}}, 0, 0 },
+  { "fr52", 52, {0, {0}}, 0, 0 },
+  { "fr53", 53, {0, {0}}, 0, 0 },
+  { "fr54", 54, {0, {0}}, 0, 0 },
+  { "fr55", 55, {0, {0}}, 0, 0 },
+  { "fr56", 56, {0, {0}}, 0, 0 },
+  { "fr57", 57, {0, {0}}, 0, 0 },
+  { "fr58", 58, {0, {0}}, 0, 0 },
+  { "fr59", 59, {0, {0}}, 0, 0 },
+  { "fr60", 60, {0, {0}}, 0, 0 },
+  { "fr61", 61, {0, {0}}, 0, 0 },
+  { "fr62", 62, {0, {0}}, 0, 0 },
+  { "fr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_fr_names =
+{
+  & frv_cgen_opval_fr_names_entries[0],
+  64,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] =
+{
+  { "cpr0", 0, {0, {0}}, 0, 0 },
+  { "cpr1", 1, {0, {0}}, 0, 0 },
+  { "cpr2", 2, {0, {0}}, 0, 0 },
+  { "cpr3", 3, {0, {0}}, 0, 0 },
+  { "cpr4", 4, {0, {0}}, 0, 0 },
+  { "cpr5", 5, {0, {0}}, 0, 0 },
+  { "cpr6", 6, {0, {0}}, 0, 0 },
+  { "cpr7", 7, {0, {0}}, 0, 0 },
+  { "cpr8", 8, {0, {0}}, 0, 0 },
+  { "cpr9", 9, {0, {0}}, 0, 0 },
+  { "cpr10", 10, {0, {0}}, 0, 0 },
+  { "cpr11", 11, {0, {0}}, 0, 0 },
+  { "cpr12", 12, {0, {0}}, 0, 0 },
+  { "cpr13", 13, {0, {0}}, 0, 0 },
+  { "cpr14", 14, {0, {0}}, 0, 0 },
+  { "cpr15", 15, {0, {0}}, 0, 0 },
+  { "cpr16", 16, {0, {0}}, 0, 0 },
+  { "cpr17", 17, {0, {0}}, 0, 0 },
+  { "cpr18", 18, {0, {0}}, 0, 0 },
+  { "cpr19", 19, {0, {0}}, 0, 0 },
+  { "cpr20", 20, {0, {0}}, 0, 0 },
+  { "cpr21", 21, {0, {0}}, 0, 0 },
+  { "cpr22", 22, {0, {0}}, 0, 0 },
+  { "cpr23", 23, {0, {0}}, 0, 0 },
+  { "cpr24", 24, {0, {0}}, 0, 0 },
+  { "cpr25", 25, {0, {0}}, 0, 0 },
+  { "cpr26", 26, {0, {0}}, 0, 0 },
+  { "cpr27", 27, {0, {0}}, 0, 0 },
+  { "cpr28", 28, {0, {0}}, 0, 0 },
+  { "cpr29", 29, {0, {0}}, 0, 0 },
+  { "cpr30", 30, {0, {0}}, 0, 0 },
+  { "cpr31", 31, {0, {0}}, 0, 0 },
+  { "cpr32", 32, {0, {0}}, 0, 0 },
+  { "cpr33", 33, {0, {0}}, 0, 0 },
+  { "cpr34", 34, {0, {0}}, 0, 0 },
+  { "cpr35", 35, {0, {0}}, 0, 0 },
+  { "cpr36", 36, {0, {0}}, 0, 0 },
+  { "cpr37", 37, {0, {0}}, 0, 0 },
+  { "cpr38", 38, {0, {0}}, 0, 0 },
+  { "cpr39", 39, {0, {0}}, 0, 0 },
+  { "cpr40", 40, {0, {0}}, 0, 0 },
+  { "cpr41", 41, {0, {0}}, 0, 0 },
+  { "cpr42", 42, {0, {0}}, 0, 0 },
+  { "cpr43", 43, {0, {0}}, 0, 0 },
+  { "cpr44", 44, {0, {0}}, 0, 0 },
+  { "cpr45", 45, {0, {0}}, 0, 0 },
+  { "cpr46", 46, {0, {0}}, 0, 0 },
+  { "cpr47", 47, {0, {0}}, 0, 0 },
+  { "cpr48", 48, {0, {0}}, 0, 0 },
+  { "cpr49", 49, {0, {0}}, 0, 0 },
+  { "cpr50", 50, {0, {0}}, 0, 0 },
+  { "cpr51", 51, {0, {0}}, 0, 0 },
+  { "cpr52", 52, {0, {0}}, 0, 0 },
+  { "cpr53", 53, {0, {0}}, 0, 0 },
+  { "cpr54", 54, {0, {0}}, 0, 0 },
+  { "cpr55", 55, {0, {0}}, 0, 0 },
+  { "cpr56", 56, {0, {0}}, 0, 0 },
+  { "cpr57", 57, {0, {0}}, 0, 0 },
+  { "cpr58", 58, {0, {0}}, 0, 0 },
+  { "cpr59", 59, {0, {0}}, 0, 0 },
+  { "cpr60", 60, {0, {0}}, 0, 0 },
+  { "cpr61", 61, {0, {0}}, 0, 0 },
+  { "cpr62", 62, {0, {0}}, 0, 0 },
+  { "cpr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_cpr_names =
+{
+  & frv_cgen_opval_cpr_names_entries[0],
+  64,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] =
+{
+  { "psr", 0, {0, {0}}, 0, 0 },
+  { "pcsr", 1, {0, {0}}, 0, 0 },
+  { "bpcsr", 2, {0, {0}}, 0, 0 },
+  { "tbr", 3, {0, {0}}, 0, 0 },
+  { "bpsr", 4, {0, {0}}, 0, 0 },
+  { "hsr0", 16, {0, {0}}, 0, 0 },
+  { "hsr1", 17, {0, {0}}, 0, 0 },
+  { "hsr2", 18, {0, {0}}, 0, 0 },
+  { "hsr3", 19, {0, {0}}, 0, 0 },
+  { "hsr4", 20, {0, {0}}, 0, 0 },
+  { "hsr5", 21, {0, {0}}, 0, 0 },
+  { "hsr6", 22, {0, {0}}, 0, 0 },
+  { "hsr7", 23, {0, {0}}, 0, 0 },
+  { "hsr8", 24, {0, {0}}, 0, 0 },
+  { "hsr9", 25, {0, {0}}, 0, 0 },
+  { "hsr10", 26, {0, {0}}, 0, 0 },
+  { "hsr11", 27, {0, {0}}, 0, 0 },
+  { "hsr12", 28, {0, {0}}, 0, 0 },
+  { "hsr13", 29, {0, {0}}, 0, 0 },
+  { "hsr14", 30, {0, {0}}, 0, 0 },
+  { "hsr15", 31, {0, {0}}, 0, 0 },
+  { "hsr16", 32, {0, {0}}, 0, 0 },
+  { "hsr17", 33, {0, {0}}, 0, 0 },
+  { "hsr18", 34, {0, {0}}, 0, 0 },
+  { "hsr19", 35, {0, {0}}, 0, 0 },
+  { "hsr20", 36, {0, {0}}, 0, 0 },
+  { "hsr21", 37, {0, {0}}, 0, 0 },
+  { "hsr22", 38, {0, {0}}, 0, 0 },
+  { "hsr23", 39, {0, {0}}, 0, 0 },
+  { "hsr24", 40, {0, {0}}, 0, 0 },
+  { "hsr25", 41, {0, {0}}, 0, 0 },
+  { "hsr26", 42, {0, {0}}, 0, 0 },
+  { "hsr27", 43, {0, {0}}, 0, 0 },
+  { "hsr28", 44, {0, {0}}, 0, 0 },
+  { "hsr29", 45, {0, {0}}, 0, 0 },
+  { "hsr30", 46, {0, {0}}, 0, 0 },
+  { "hsr31", 47, {0, {0}}, 0, 0 },
+  { "hsr32", 48, {0, {0}}, 0, 0 },
+  { "hsr33", 49, {0, {0}}, 0, 0 },
+  { "hsr34", 50, {0, {0}}, 0, 0 },
+  { "hsr35", 51, {0, {0}}, 0, 0 },
+  { "hsr36", 52, {0, {0}}, 0, 0 },
+  { "hsr37", 53, {0, {0}}, 0, 0 },
+  { "hsr38", 54, {0, {0}}, 0, 0 },
+  { "hsr39", 55, {0, {0}}, 0, 0 },
+  { "hsr40", 56, {0, {0}}, 0, 0 },
+  { "hsr41", 57, {0, {0}}, 0, 0 },
+  { "hsr42", 58, {0, {0}}, 0, 0 },
+  { "hsr43", 59, {0, {0}}, 0, 0 },
+  { "hsr44", 60, {0, {0}}, 0, 0 },
+  { "hsr45", 61, {0, {0}}, 0, 0 },
+  { "hsr46", 62, {0, {0}}, 0, 0 },
+  { "hsr47", 63, {0, {0}}, 0, 0 },
+  { "hsr48", 64, {0, {0}}, 0, 0 },
+  { "hsr49", 65, {0, {0}}, 0, 0 },
+  { "hsr50", 66, {0, {0}}, 0, 0 },
+  { "hsr51", 67, {0, {0}}, 0, 0 },
+  { "hsr52", 68, {0, {0}}, 0, 0 },
+  { "hsr53", 69, {0, {0}}, 0, 0 },
+  { "hsr54", 70, {0, {0}}, 0, 0 },
+  { "hsr55", 71, {0, {0}}, 0, 0 },
+  { "hsr56", 72, {0, {0}}, 0, 0 },
+  { "hsr57", 73, {0, {0}}, 0, 0 },
+  { "hsr58", 74, {0, {0}}, 0, 0 },
+  { "hsr59", 75, {0, {0}}, 0, 0 },
+  { "hsr60", 76, {0, {0}}, 0, 0 },
+  { "hsr61", 77, {0, {0}}, 0, 0 },
+  { "hsr62", 78, {0, {0}}, 0, 0 },
+  { "hsr63", 79, {0, {0}}, 0, 0 },
+  { "ccr", 256, {0, {0}}, 0, 0 },
+  { "cccr", 263, {0, {0}}, 0, 0 },
+  { "lr", 272, {0, {0}}, 0, 0 },
+  { "lcr", 273, {0, {0}}, 0, 0 },
+  { "isr", 288, {0, {0}}, 0, 0 },
+  { "neear0", 352, {0, {0}}, 0, 0 },
+  { "neear1", 353, {0, {0}}, 0, 0 },
+  { "neear2", 354, {0, {0}}, 0, 0 },
+  { "neear3", 355, {0, {0}}, 0, 0 },
+  { "neear4", 356, {0, {0}}, 0, 0 },
+  { "neear5", 357, {0, {0}}, 0, 0 },
+  { "neear6", 358, {0, {0}}, 0, 0 },
+  { "neear7", 359, {0, {0}}, 0, 0 },
+  { "neear8", 360, {0, {0}}, 0, 0 },
+  { "neear9", 361, {0, {0}}, 0, 0 },
+  { "neear10", 362, {0, {0}}, 0, 0 },
+  { "neear11", 363, {0, {0}}, 0, 0 },
+  { "neear12", 364, {0, {0}}, 0, 0 },
+  { "neear13", 365, {0, {0}}, 0, 0 },
+  { "neear14", 366, {0, {0}}, 0, 0 },
+  { "neear15", 367, {0, {0}}, 0, 0 },
+  { "neear16", 368, {0, {0}}, 0, 0 },
+  { "neear17", 369, {0, {0}}, 0, 0 },
+  { "neear18", 370, {0, {0}}, 0, 0 },
+  { "neear19", 371, {0, {0}}, 0, 0 },
+  { "neear20", 372, {0, {0}}, 0, 0 },
+  { "neear21", 373, {0, {0}}, 0, 0 },
+  { "neear22", 374, {0, {0}}, 0, 0 },
+  { "neear23", 375, {0, {0}}, 0, 0 },
+  { "neear24", 376, {0, {0}}, 0, 0 },
+  { "neear25", 377, {0, {0}}, 0, 0 },
+  { "neear26", 378, {0, {0}}, 0, 0 },
+  { "neear27", 379, {0, {0}}, 0, 0 },
+  { "neear28", 380, {0, {0}}, 0, 0 },
+  { "neear29", 381, {0, {0}}, 0, 0 },
+  { "neear30", 382, {0, {0}}, 0, 0 },
+  { "neear31", 383, {0, {0}}, 0, 0 },
+  { "nesr0", 384, {0, {0}}, 0, 0 },
+  { "nesr1", 385, {0, {0}}, 0, 0 },
+  { "nesr2", 386, {0, {0}}, 0, 0 },
+  { "nesr3", 387, {0, {0}}, 0, 0 },
+  { "nesr4", 388, {0, {0}}, 0, 0 },
+  { "nesr5", 389, {0, {0}}, 0, 0 },
+  { "nesr6", 390, {0, {0}}, 0, 0 },
+  { "nesr7", 391, {0, {0}}, 0, 0 },
+  { "nesr8", 392, {0, {0}}, 0, 0 },
+  { "nesr9", 393, {0, {0}}, 0, 0 },
+  { "nesr10", 394, {0, {0}}, 0, 0 },
+  { "nesr11", 395, {0, {0}}, 0, 0 },
+  { "nesr12", 396, {0, {0}}, 0, 0 },
+  { "nesr13", 397, {0, {0}}, 0, 0 },
+  { "nesr14", 398, {0, {0}}, 0, 0 },
+  { "nesr15", 399, {0, {0}}, 0, 0 },
+  { "nesr16", 400, {0, {0}}, 0, 0 },
+  { "nesr17", 401, {0, {0}}, 0, 0 },
+  { "nesr18", 402, {0, {0}}, 0, 0 },
+  { "nesr19", 403, {0, {0}}, 0, 0 },
+  { "nesr20", 404, {0, {0}}, 0, 0 },
+  { "nesr21", 405, {0, {0}}, 0, 0 },
+  { "nesr22", 406, {0, {0}}, 0, 0 },
+  { "nesr23", 407, {0, {0}}, 0, 0 },
+  { "nesr24", 408, {0, {0}}, 0, 0 },
+  { "nesr25", 409, {0, {0}}, 0, 0 },
+  { "nesr26", 410, {0, {0}}, 0, 0 },
+  { "nesr27", 411, {0, {0}}, 0, 0 },
+  { "nesr28", 412, {0, {0}}, 0, 0 },
+  { "nesr29", 413, {0, {0}}, 0, 0 },
+  { "nesr30", 414, {0, {0}}, 0, 0 },
+  { "nesr31", 415, {0, {0}}, 0, 0 },
+  { "necr", 416, {0, {0}}, 0, 0 },
+  { "gner0", 432, {0, {0}}, 0, 0 },
+  { "gner1", 433, {0, {0}}, 0, 0 },
+  { "fner0", 434, {0, {0}}, 0, 0 },
+  { "fner1", 435, {0, {0}}, 0, 0 },
+  { "epcr0", 512, {0, {0}}, 0, 0 },
+  { "epcr1", 513, {0, {0}}, 0, 0 },
+  { "epcr2", 514, {0, {0}}, 0, 0 },
+  { "epcr3", 515, {0, {0}}, 0, 0 },
+  { "epcr4", 516, {0, {0}}, 0, 0 },
+  { "epcr5", 517, {0, {0}}, 0, 0 },
+  { "epcr6", 518, {0, {0}}, 0, 0 },
+  { "epcr7", 519, {0, {0}}, 0, 0 },
+  { "epcr8", 520, {0, {0}}, 0, 0 },
+  { "epcr9", 521, {0, {0}}, 0, 0 },
+  { "epcr10", 522, {0, {0}}, 0, 0 },
+  { "epcr11", 523, {0, {0}}, 0, 0 },
+  { "epcr12", 524, {0, {0}}, 0, 0 },
+  { "epcr13", 525, {0, {0}}, 0, 0 },
+  { "epcr14", 526, {0, {0}}, 0, 0 },
+  { "epcr15", 527, {0, {0}}, 0, 0 },
+  { "epcr16", 528, {0, {0}}, 0, 0 },
+  { "epcr17", 529, {0, {0}}, 0, 0 },
+  { "epcr18", 530, {0, {0}}, 0, 0 },
+  { "epcr19", 531, {0, {0}}, 0, 0 },
+  { "epcr20", 532, {0, {0}}, 0, 0 },
+  { "epcr21", 533, {0, {0}}, 0, 0 },
+  { "epcr22", 534, {0, {0}}, 0, 0 },
+  { "epcr23", 535, {0, {0}}, 0, 0 },
+  { "epcr24", 536, {0, {0}}, 0, 0 },
+  { "epcr25", 537, {0, {0}}, 0, 0 },
+  { "epcr26", 538, {0, {0}}, 0, 0 },
+  { "epcr27", 539, {0, {0}}, 0, 0 },
+  { "epcr28", 540, {0, {0}}, 0, 0 },
+  { "epcr29", 541, {0, {0}}, 0, 0 },
+  { "epcr30", 542, {0, {0}}, 0, 0 },
+  { "epcr31", 543, {0, {0}}, 0, 0 },
+  { "epcr32", 544, {0, {0}}, 0, 0 },
+  { "epcr33", 545, {0, {0}}, 0, 0 },
+  { "epcr34", 546, {0, {0}}, 0, 0 },
+  { "epcr35", 547, {0, {0}}, 0, 0 },
+  { "epcr36", 548, {0, {0}}, 0, 0 },
+  { "epcr37", 549, {0, {0}}, 0, 0 },
+  { "epcr38", 550, {0, {0}}, 0, 0 },
+  { "epcr39", 551, {0, {0}}, 0, 0 },
+  { "epcr40", 552, {0, {0}}, 0, 0 },
+  { "epcr41", 553, {0, {0}}, 0, 0 },
+  { "epcr42", 554, {0, {0}}, 0, 0 },
+  { "epcr43", 555, {0, {0}}, 0, 0 },
+  { "epcr44", 556, {0, {0}}, 0, 0 },
+  { "epcr45", 557, {0, {0}}, 0, 0 },
+  { "epcr46", 558, {0, {0}}, 0, 0 },
+  { "epcr47", 559, {0, {0}}, 0, 0 },
+  { "epcr48", 560, {0, {0}}, 0, 0 },
+  { "epcr49", 561, {0, {0}}, 0, 0 },
+  { "epcr50", 562, {0, {0}}, 0, 0 },
+  { "epcr51", 563, {0, {0}}, 0, 0 },
+  { "epcr52", 564, {0, {0}}, 0, 0 },
+  { "epcr53", 565, {0, {0}}, 0, 0 },
+  { "epcr54", 566, {0, {0}}, 0, 0 },
+  { "epcr55", 567, {0, {0}}, 0, 0 },
+  { "epcr56", 568, {0, {0}}, 0, 0 },
+  { "epcr57", 569, {0, {0}}, 0, 0 },
+  { "epcr58", 570, {0, {0}}, 0, 0 },
+  { "epcr59", 571, {0, {0}}, 0, 0 },
+  { "epcr60", 572, {0, {0}}, 0, 0 },
+  { "epcr61", 573, {0, {0}}, 0, 0 },
+  { "epcr62", 574, {0, {0}}, 0, 0 },
+  { "epcr63", 575, {0, {0}}, 0, 0 },
+  { "esr0", 576, {0, {0}}, 0, 0 },
+  { "esr1", 577, {0, {0}}, 0, 0 },
+  { "esr2", 578, {0, {0}}, 0, 0 },
+  { "esr3", 579, {0, {0}}, 0, 0 },
+  { "esr4", 580, {0, {0}}, 0, 0 },
+  { "esr5", 581, {0, {0}}, 0, 0 },
+  { "esr6", 582, {0, {0}}, 0, 0 },
+  { "esr7", 583, {0, {0}}, 0, 0 },
+  { "esr8", 584, {0, {0}}, 0, 0 },
+  { "esr9", 585, {0, {0}}, 0, 0 },
+  { "esr10", 586, {0, {0}}, 0, 0 },
+  { "esr11", 587, {0, {0}}, 0, 0 },
+  { "esr12", 588, {0, {0}}, 0, 0 },
+  { "esr13", 589, {0, {0}}, 0, 0 },
+  { "esr14", 590, {0, {0}}, 0, 0 },
+  { "esr15", 591, {0, {0}}, 0, 0 },
+  { "esr16", 592, {0, {0}}, 0, 0 },
+  { "esr17", 593, {0, {0}}, 0, 0 },
+  { "esr18", 594, {0, {0}}, 0, 0 },
+  { "esr19", 595, {0, {0}}, 0, 0 },
+  { "esr20", 596, {0, {0}}, 0, 0 },
+  { "esr21", 597, {0, {0}}, 0, 0 },
+  { "esr22", 598, {0, {0}}, 0, 0 },
+  { "esr23", 599, {0, {0}}, 0, 0 },
+  { "esr24", 600, {0, {0}}, 0, 0 },
+  { "esr25", 601, {0, {0}}, 0, 0 },
+  { "esr26", 602, {0, {0}}, 0, 0 },
+  { "esr27", 603, {0, {0}}, 0, 0 },
+  { "esr28", 604, {0, {0}}, 0, 0 },
+  { "esr29", 605, {0, {0}}, 0, 0 },
+  { "esr30", 606, {0, {0}}, 0, 0 },
+  { "esr31", 607, {0, {0}}, 0, 0 },
+  { "esr32", 608, {0, {0}}, 0, 0 },
+  { "esr33", 609, {0, {0}}, 0, 0 },
+  { "esr34", 610, {0, {0}}, 0, 0 },
+  { "esr35", 611, {0, {0}}, 0, 0 },
+  { "esr36", 612, {0, {0}}, 0, 0 },
+  { "esr37", 613, {0, {0}}, 0, 0 },
+  { "esr38", 614, {0, {0}}, 0, 0 },
+  { "esr39", 615, {0, {0}}, 0, 0 },
+  { "esr40", 616, {0, {0}}, 0, 0 },
+  { "esr41", 617, {0, {0}}, 0, 0 },
+  { "esr42", 618, {0, {0}}, 0, 0 },
+  { "esr43", 619, {0, {0}}, 0, 0 },
+  { "esr44", 620, {0, {0}}, 0, 0 },
+  { "esr45", 621, {0, {0}}, 0, 0 },
+  { "esr46", 622, {0, {0}}, 0, 0 },
+  { "esr47", 623, {0, {0}}, 0, 0 },
+  { "esr48", 624, {0, {0}}, 0, 0 },
+  { "esr49", 625, {0, {0}}, 0, 0 },
+  { "esr50", 626, {0, {0}}, 0, 0 },
+  { "esr51", 627, {0, {0}}, 0, 0 },
+  { "esr52", 628, {0, {0}}, 0, 0 },
+  { "esr53", 629, {0, {0}}, 0, 0 },
+  { "esr54", 630, {0, {0}}, 0, 0 },
+  { "esr55", 631, {0, {0}}, 0, 0 },
+  { "esr56", 632, {0, {0}}, 0, 0 },
+  { "esr57", 633, {0, {0}}, 0, 0 },
+  { "esr58", 634, {0, {0}}, 0, 0 },
+  { "esr59", 635, {0, {0}}, 0, 0 },
+  { "esr60", 636, {0, {0}}, 0, 0 },
+  { "esr61", 637, {0, {0}}, 0, 0 },
+  { "esr62", 638, {0, {0}}, 0, 0 },
+  { "esr63", 639, {0, {0}}, 0, 0 },
+  { "eir0", 640, {0, {0}}, 0, 0 },
+  { "eir1", 641, {0, {0}}, 0, 0 },
+  { "eir2", 642, {0, {0}}, 0, 0 },
+  { "eir3", 643, {0, {0}}, 0, 0 },
+  { "eir4", 644, {0, {0}}, 0, 0 },
+  { "eir5", 645, {0, {0}}, 0, 0 },
+  { "eir6", 646, {0, {0}}, 0, 0 },
+  { "eir7", 647, {0, {0}}, 0, 0 },
+  { "eir8", 648, {0, {0}}, 0, 0 },
+  { "eir9", 649, {0, {0}}, 0, 0 },
+  { "eir10", 650, {0, {0}}, 0, 0 },
+  { "eir11", 651, {0, {0}}, 0, 0 },
+  { "eir12", 652, {0, {0}}, 0, 0 },
+  { "eir13", 653, {0, {0}}, 0, 0 },
+  { "eir14", 654, {0, {0}}, 0, 0 },
+  { "eir15", 655, {0, {0}}, 0, 0 },
+  { "eir16", 656, {0, {0}}, 0, 0 },
+  { "eir17", 657, {0, {0}}, 0, 0 },
+  { "eir18", 658, {0, {0}}, 0, 0 },
+  { "eir19", 659, {0, {0}}, 0, 0 },
+  { "eir20", 660, {0, {0}}, 0, 0 },
+  { "eir21", 661, {0, {0}}, 0, 0 },
+  { "eir22", 662, {0, {0}}, 0, 0 },
+  { "eir23", 663, {0, {0}}, 0, 0 },
+  { "eir24", 664, {0, {0}}, 0, 0 },
+  { "eir25", 665, {0, {0}}, 0, 0 },
+  { "eir26", 666, {0, {0}}, 0, 0 },
+  { "eir27", 667, {0, {0}}, 0, 0 },
+  { "eir28", 668, {0, {0}}, 0, 0 },
+  { "eir29", 669, {0, {0}}, 0, 0 },
+  { "eir30", 670, {0, {0}}, 0, 0 },
+  { "eir31", 671, {0, {0}}, 0, 0 },
+  { "esfr0", 672, {0, {0}}, 0, 0 },
+  { "esfr1", 673, {0, {0}}, 0, 0 },
+  { "sr0", 768, {0, {0}}, 0, 0 },
+  { "sr1", 769, {0, {0}}, 0, 0 },
+  { "sr2", 770, {0, {0}}, 0, 0 },
+  { "sr3", 771, {0, {0}}, 0, 0 },
+  { "fsr0", 1024, {0, {0}}, 0, 0 },
+  { "fsr1", 1025, {0, {0}}, 0, 0 },
+  { "fsr2", 1026, {0, {0}}, 0, 0 },
+  { "fsr3", 1027, {0, {0}}, 0, 0 },
+  { "fsr4", 1028, {0, {0}}, 0, 0 },
+  { "fsr5", 1029, {0, {0}}, 0, 0 },
+  { "fsr6", 1030, {0, {0}}, 0, 0 },
+  { "fsr7", 1031, {0, {0}}, 0, 0 },
+  { "fsr8", 1032, {0, {0}}, 0, 0 },
+  { "fsr9", 1033, {0, {0}}, 0, 0 },
+  { "fsr10", 1034, {0, {0}}, 0, 0 },
+  { "fsr11", 1035, {0, {0}}, 0, 0 },
+  { "fsr12", 1036, {0, {0}}, 0, 0 },
+  { "fsr13", 1037, {0, {0}}, 0, 0 },
+  { "fsr14", 1038, {0, {0}}, 0, 0 },
+  { "fsr15", 1039, {0, {0}}, 0, 0 },
+  { "fsr16", 1040, {0, {0}}, 0, 0 },
+  { "fsr17", 1041, {0, {0}}, 0, 0 },
+  { "fsr18", 1042, {0, {0}}, 0, 0 },
+  { "fsr19", 1043, {0, {0}}, 0, 0 },
+  { "fsr20", 1044, {0, {0}}, 0, 0 },
+  { "fsr21", 1045, {0, {0}}, 0, 0 },
+  { "fsr22", 1046, {0, {0}}, 0, 0 },
+  { "fsr23", 1047, {0, {0}}, 0, 0 },
+  { "fsr24", 1048, {0, {0}}, 0, 0 },
+  { "fsr25", 1049, {0, {0}}, 0, 0 },
+  { "fsr26", 1050, {0, {0}}, 0, 0 },
+  { "fsr27", 1051, {0, {0}}, 0, 0 },
+  { "fsr28", 1052, {0, {0}}, 0, 0 },
+  { "fsr29", 1053, {0, {0}}, 0, 0 },
+  { "fsr30", 1054, {0, {0}}, 0, 0 },
+  { "fsr31", 1055, {0, {0}}, 0, 0 },
+  { "fsr32", 1056, {0, {0}}, 0, 0 },
+  { "fsr33", 1057, {0, {0}}, 0, 0 },
+  { "fsr34", 1058, {0, {0}}, 0, 0 },
+  { "fsr35", 1059, {0, {0}}, 0, 0 },
+  { "fsr36", 1060, {0, {0}}, 0, 0 },
+  { "fsr37", 1061, {0, {0}}, 0, 0 },
+  { "fsr38", 1062, {0, {0}}, 0, 0 },
+  { "fsr39", 1063, {0, {0}}, 0, 0 },
+  { "fsr40", 1064, {0, {0}}, 0, 0 },
+  { "fsr41", 1065, {0, {0}}, 0, 0 },
+  { "fsr42", 1066, {0, {0}}, 0, 0 },
+  { "fsr43", 1067, {0, {0}}, 0, 0 },
+  { "fsr44", 1068, {0, {0}}, 0, 0 },
+  { "fsr45", 1069, {0, {0}}, 0, 0 },
+  { "fsr46", 1070, {0, {0}}, 0, 0 },
+  { "fsr47", 1071, {0, {0}}, 0, 0 },
+  { "fsr48", 1072, {0, {0}}, 0, 0 },
+  { "fsr49", 1073, {0, {0}}, 0, 0 },
+  { "fsr50", 1074, {0, {0}}, 0, 0 },
+  { "fsr51", 1075, {0, {0}}, 0, 0 },
+  { "fsr52", 1076, {0, {0}}, 0, 0 },
+  { "fsr53", 1077, {0, {0}}, 0, 0 },
+  { "fsr54", 1078, {0, {0}}, 0, 0 },
+  { "fsr55", 1079, {0, {0}}, 0, 0 },
+  { "fsr56", 1080, {0, {0}}, 0, 0 },
+  { "fsr57", 1081, {0, {0}}, 0, 0 },
+  { "fsr58", 1082, {0, {0}}, 0, 0 },
+  { "fsr59", 1083, {0, {0}}, 0, 0 },
+  { "fsr60", 1084, {0, {0}}, 0, 0 },
+  { "fsr61", 1085, {0, {0}}, 0, 0 },
+  { "fsr62", 1086, {0, {0}}, 0, 0 },
+  { "fsr63", 1087, {0, {0}}, 0, 0 },
+  { "fqop0", 1088, {0, {0}}, 0, 0 },
+  { "fqop1", 1090, {0, {0}}, 0, 0 },
+  { "fqop2", 1092, {0, {0}}, 0, 0 },
+  { "fqop3", 1094, {0, {0}}, 0, 0 },
+  { "fqop4", 1096, {0, {0}}, 0, 0 },
+  { "fqop5", 1098, {0, {0}}, 0, 0 },
+  { "fqop6", 1100, {0, {0}}, 0, 0 },
+  { "fqop7", 1102, {0, {0}}, 0, 0 },
+  { "fqop8", 1104, {0, {0}}, 0, 0 },
+  { "fqop9", 1106, {0, {0}}, 0, 0 },
+  { "fqop10", 1108, {0, {0}}, 0, 0 },
+  { "fqop11", 1110, {0, {0}}, 0, 0 },
+  { "fqop12", 1112, {0, {0}}, 0, 0 },
+  { "fqop13", 1114, {0, {0}}, 0, 0 },
+  { "fqop14", 1116, {0, {0}}, 0, 0 },
+  { "fqop15", 1118, {0, {0}}, 0, 0 },
+  { "fqop16", 1120, {0, {0}}, 0, 0 },
+  { "fqop17", 1122, {0, {0}}, 0, 0 },
+  { "fqop18", 1124, {0, {0}}, 0, 0 },
+  { "fqop19", 1126, {0, {0}}, 0, 0 },
+  { "fqop20", 1128, {0, {0}}, 0, 0 },
+  { "fqop21", 1130, {0, {0}}, 0, 0 },
+  { "fqop22", 1132, {0, {0}}, 0, 0 },
+  { "fqop23", 1134, {0, {0}}, 0, 0 },
+  { "fqop24", 1136, {0, {0}}, 0, 0 },
+  { "fqop25", 1138, {0, {0}}, 0, 0 },
+  { "fqop26", 1140, {0, {0}}, 0, 0 },
+  { "fqop27", 1142, {0, {0}}, 0, 0 },
+  { "fqop28", 1144, {0, {0}}, 0, 0 },
+  { "fqop29", 1146, {0, {0}}, 0, 0 },
+  { "fqop30", 1148, {0, {0}}, 0, 0 },
+  { "fqop31", 1150, {0, {0}}, 0, 0 },
+  { "fqst0", 1089, {0, {0}}, 0, 0 },
+  { "fqst1", 1091, {0, {0}}, 0, 0 },
+  { "fqst2", 1093, {0, {0}}, 0, 0 },
+  { "fqst3", 1095, {0, {0}}, 0, 0 },
+  { "fqst4", 1097, {0, {0}}, 0, 0 },
+  { "fqst5", 1099, {0, {0}}, 0, 0 },
+  { "fqst6", 1101, {0, {0}}, 0, 0 },
+  { "fqst7", 1103, {0, {0}}, 0, 0 },
+  { "fqst8", 1105, {0, {0}}, 0, 0 },
+  { "fqst9", 1107, {0, {0}}, 0, 0 },
+  { "fqst10", 1109, {0, {0}}, 0, 0 },
+  { "fqst11", 1111, {0, {0}}, 0, 0 },
+  { "fqst12", 1113, {0, {0}}, 0, 0 },
+  { "fqst13", 1115, {0, {0}}, 0, 0 },
+  { "fqst14", 1117, {0, {0}}, 0, 0 },
+  { "fqst15", 1119, {0, {0}}, 0, 0 },
+  { "fqst16", 1121, {0, {0}}, 0, 0 },
+  { "fqst17", 1123, {0, {0}}, 0, 0 },
+  { "fqst18", 1125, {0, {0}}, 0, 0 },
+  { "fqst19", 1127, {0, {0}}, 0, 0 },
+  { "fqst20", 1129, {0, {0}}, 0, 0 },
+  { "fqst21", 1131, {0, {0}}, 0, 0 },
+  { "fqst22", 1133, {0, {0}}, 0, 0 },
+  { "fqst23", 1135, {0, {0}}, 0, 0 },
+  { "fqst24", 1137, {0, {0}}, 0, 0 },
+  { "fqst25", 1139, {0, {0}}, 0, 0 },
+  { "fqst26", 1141, {0, {0}}, 0, 0 },
+  { "fqst27", 1143, {0, {0}}, 0, 0 },
+  { "fqst28", 1145, {0, {0}}, 0, 0 },
+  { "fqst29", 1147, {0, {0}}, 0, 0 },
+  { "fqst30", 1149, {0, {0}}, 0, 0 },
+  { "fqst31", 1151, {0, {0}}, 0, 0 },
+  { "mcilr0", 1272, {0, {0}}, 0, 0 },
+  { "mcilr1", 1273, {0, {0}}, 0, 0 },
+  { "msr0", 1280, {0, {0}}, 0, 0 },
+  { "msr1", 1281, {0, {0}}, 0, 0 },
+  { "msr2", 1282, {0, {0}}, 0, 0 },
+  { "msr3", 1283, {0, {0}}, 0, 0 },
+  { "msr4", 1284, {0, {0}}, 0, 0 },
+  { "msr5", 1285, {0, {0}}, 0, 0 },
+  { "msr6", 1286, {0, {0}}, 0, 0 },
+  { "msr7", 1287, {0, {0}}, 0, 0 },
+  { "msr8", 1288, {0, {0}}, 0, 0 },
+  { "msr9", 1289, {0, {0}}, 0, 0 },
+  { "msr10", 1290, {0, {0}}, 0, 0 },
+  { "msr11", 1291, {0, {0}}, 0, 0 },
+  { "msr12", 1292, {0, {0}}, 0, 0 },
+  { "msr13", 1293, {0, {0}}, 0, 0 },
+  { "msr14", 1294, {0, {0}}, 0, 0 },
+  { "msr15", 1295, {0, {0}}, 0, 0 },
+  { "msr16", 1296, {0, {0}}, 0, 0 },
+  { "msr17", 1297, {0, {0}}, 0, 0 },
+  { "msr18", 1298, {0, {0}}, 0, 0 },
+  { "msr19", 1299, {0, {0}}, 0, 0 },
+  { "msr20", 1300, {0, {0}}, 0, 0 },
+  { "msr21", 1301, {0, {0}}, 0, 0 },
+  { "msr22", 1302, {0, {0}}, 0, 0 },
+  { "msr23", 1303, {0, {0}}, 0, 0 },
+  { "msr24", 1304, {0, {0}}, 0, 0 },
+  { "msr25", 1305, {0, {0}}, 0, 0 },
+  { "msr26", 1306, {0, {0}}, 0, 0 },
+  { "msr27", 1307, {0, {0}}, 0, 0 },
+  { "msr28", 1308, {0, {0}}, 0, 0 },
+  { "msr29", 1309, {0, {0}}, 0, 0 },
+  { "msr30", 1310, {0, {0}}, 0, 0 },
+  { "msr31", 1311, {0, {0}}, 0, 0 },
+  { "msr32", 1312, {0, {0}}, 0, 0 },
+  { "msr33", 1313, {0, {0}}, 0, 0 },
+  { "msr34", 1314, {0, {0}}, 0, 0 },
+  { "msr35", 1315, {0, {0}}, 0, 0 },
+  { "msr36", 1316, {0, {0}}, 0, 0 },
+  { "msr37", 1317, {0, {0}}, 0, 0 },
+  { "msr38", 1318, {0, {0}}, 0, 0 },
+  { "msr39", 1319, {0, {0}}, 0, 0 },
+  { "msr40", 1320, {0, {0}}, 0, 0 },
+  { "msr41", 1321, {0, {0}}, 0, 0 },
+  { "msr42", 1322, {0, {0}}, 0, 0 },
+  { "msr43", 1323, {0, {0}}, 0, 0 },
+  { "msr44", 1324, {0, {0}}, 0, 0 },
+  { "msr45", 1325, {0, {0}}, 0, 0 },
+  { "msr46", 1326, {0, {0}}, 0, 0 },
+  { "msr47", 1327, {0, {0}}, 0, 0 },
+  { "msr48", 1328, {0, {0}}, 0, 0 },
+  { "msr49", 1329, {0, {0}}, 0, 0 },
+  { "msr50", 1330, {0, {0}}, 0, 0 },
+  { "msr51", 1331, {0, {0}}, 0, 0 },
+  { "msr52", 1332, {0, {0}}, 0, 0 },
+  { "msr53", 1333, {0, {0}}, 0, 0 },
+  { "msr54", 1334, {0, {0}}, 0, 0 },
+  { "msr55", 1335, {0, {0}}, 0, 0 },
+  { "msr56", 1336, {0, {0}}, 0, 0 },
+  { "msr57", 1337, {0, {0}}, 0, 0 },
+  { "msr58", 1338, {0, {0}}, 0, 0 },
+  { "msr59", 1339, {0, {0}}, 0, 0 },
+  { "msr60", 1340, {0, {0}}, 0, 0 },
+  { "msr61", 1341, {0, {0}}, 0, 0 },
+  { "msr62", 1342, {0, {0}}, 0, 0 },
+  { "msr63", 1343, {0, {0}}, 0, 0 },
+  { "mqop0", 1344, {0, {0}}, 0, 0 },
+  { "mqop1", 1346, {0, {0}}, 0, 0 },
+  { "mqop2", 1348, {0, {0}}, 0, 0 },
+  { "mqop3", 1350, {0, {0}}, 0, 0 },
+  { "mqop4", 1352, {0, {0}}, 0, 0 },
+  { "mqop5", 1354, {0, {0}}, 0, 0 },
+  { "mqop6", 1356, {0, {0}}, 0, 0 },
+  { "mqop7", 1358, {0, {0}}, 0, 0 },
+  { "mqop8", 1360, {0, {0}}, 0, 0 },
+  { "mqop9", 1362, {0, {0}}, 0, 0 },
+  { "mqop10", 1364, {0, {0}}, 0, 0 },
+  { "mqop11", 1366, {0, {0}}, 0, 0 },
+  { "mqop12", 1368, {0, {0}}, 0, 0 },
+  { "mqop13", 1370, {0, {0}}, 0, 0 },
+  { "mqop14", 1372, {0, {0}}, 0, 0 },
+  { "mqop15", 1374, {0, {0}}, 0, 0 },
+  { "mqop16", 1376, {0, {0}}, 0, 0 },
+  { "mqop17", 1378, {0, {0}}, 0, 0 },
+  { "mqop18", 1380, {0, {0}}, 0, 0 },
+  { "mqop19", 1382, {0, {0}}, 0, 0 },
+  { "mqop20", 1384, {0, {0}}, 0, 0 },
+  { "mqop21", 1386, {0, {0}}, 0, 0 },
+  { "mqop22", 1388, {0, {0}}, 0, 0 },
+  { "mqop23", 1390, {0, {0}}, 0, 0 },
+  { "mqop24", 1392, {0, {0}}, 0, 0 },
+  { "mqop25", 1394, {0, {0}}, 0, 0 },
+  { "mqop26", 1396, {0, {0}}, 0, 0 },
+  { "mqop27", 1398, {0, {0}}, 0, 0 },
+  { "mqop28", 1400, {0, {0}}, 0, 0 },
+  { "mqop29", 1402, {0, {0}}, 0, 0 },
+  { "mqop30", 1404, {0, {0}}, 0, 0 },
+  { "mqop31", 1406, {0, {0}}, 0, 0 },
+  { "mqst0", 1345, {0, {0}}, 0, 0 },
+  { "mqst1", 1347, {0, {0}}, 0, 0 },
+  { "mqst2", 1349, {0, {0}}, 0, 0 },
+  { "mqst3", 1351, {0, {0}}, 0, 0 },
+  { "mqst4", 1353, {0, {0}}, 0, 0 },
+  { "mqst5", 1355, {0, {0}}, 0, 0 },
+  { "mqst6", 1357, {0, {0}}, 0, 0 },
+  { "mqst7", 1359, {0, {0}}, 0, 0 },
+  { "mqst8", 1361, {0, {0}}, 0, 0 },
+  { "mqst9", 1363, {0, {0}}, 0, 0 },
+  { "mqst10", 1365, {0, {0}}, 0, 0 },
+  { "mqst11", 1367, {0, {0}}, 0, 0 },
+  { "mqst12", 1369, {0, {0}}, 0, 0 },
+  { "mqst13", 1371, {0, {0}}, 0, 0 },
+  { "mqst14", 1373, {0, {0}}, 0, 0 },
+  { "mqst15", 1375, {0, {0}}, 0, 0 },
+  { "mqst16", 1377, {0, {0}}, 0, 0 },
+  { "mqst17", 1379, {0, {0}}, 0, 0 },
+  { "mqst18", 1381, {0, {0}}, 0, 0 },
+  { "mqst19", 1383, {0, {0}}, 0, 0 },
+  { "mqst20", 1385, {0, {0}}, 0, 0 },
+  { "mqst21", 1387, {0, {0}}, 0, 0 },
+  { "mqst22", 1389, {0, {0}}, 0, 0 },
+  { "mqst23", 1391, {0, {0}}, 0, 0 },
+  { "mqst24", 1393, {0, {0}}, 0, 0 },
+  { "mqst25", 1395, {0, {0}}, 0, 0 },
+  { "mqst26", 1397, {0, {0}}, 0, 0 },
+  { "mqst27", 1399, {0, {0}}, 0, 0 },
+  { "mqst28", 1401, {0, {0}}, 0, 0 },
+  { "mqst29", 1403, {0, {0}}, 0, 0 },
+  { "mqst30", 1405, {0, {0}}, 0, 0 },
+  { "mqst31", 1407, {0, {0}}, 0, 0 },
+  { "ear0", 1536, {0, {0}}, 0, 0 },
+  { "ear1", 1537, {0, {0}}, 0, 0 },
+  { "ear2", 1538, {0, {0}}, 0, 0 },
+  { "ear3", 1539, {0, {0}}, 0, 0 },
+  { "ear4", 1540, {0, {0}}, 0, 0 },
+  { "ear5", 1541, {0, {0}}, 0, 0 },
+  { "ear6", 1542, {0, {0}}, 0, 0 },
+  { "ear7", 1543, {0, {0}}, 0, 0 },
+  { "ear8", 1544, {0, {0}}, 0, 0 },
+  { "ear9", 1545, {0, {0}}, 0, 0 },
+  { "ear10", 1546, {0, {0}}, 0, 0 },
+  { "ear11", 1547, {0, {0}}, 0, 0 },
+  { "ear12", 1548, {0, {0}}, 0, 0 },
+  { "ear13", 1549, {0, {0}}, 0, 0 },
+  { "ear14", 1550, {0, {0}}, 0, 0 },
+  { "ear15", 1551, {0, {0}}, 0, 0 },
+  { "ear16", 1552, {0, {0}}, 0, 0 },
+  { "ear17", 1553, {0, {0}}, 0, 0 },
+  { "ear18", 1554, {0, {0}}, 0, 0 },
+  { "ear19", 1555, {0, {0}}, 0, 0 },
+  { "ear20", 1556, {0, {0}}, 0, 0 },
+  { "ear21", 1557, {0, {0}}, 0, 0 },
+  { "ear22", 1558, {0, {0}}, 0, 0 },
+  { "ear23", 1559, {0, {0}}, 0, 0 },
+  { "ear24", 1560, {0, {0}}, 0, 0 },
+  { "ear25", 1561, {0, {0}}, 0, 0 },
+  { "ear26", 1562, {0, {0}}, 0, 0 },
+  { "ear27", 1563, {0, {0}}, 0, 0 },
+  { "ear28", 1564, {0, {0}}, 0, 0 },
+  { "ear29", 1565, {0, {0}}, 0, 0 },
+  { "ear30", 1566, {0, {0}}, 0, 0 },
+  { "ear31", 1567, {0, {0}}, 0, 0 },
+  { "ear32", 1568, {0, {0}}, 0, 0 },
+  { "ear33", 1569, {0, {0}}, 0, 0 },
+  { "ear34", 1570, {0, {0}}, 0, 0 },
+  { "ear35", 1571, {0, {0}}, 0, 0 },
+  { "ear36", 1572, {0, {0}}, 0, 0 },
+  { "ear37", 1573, {0, {0}}, 0, 0 },
+  { "ear38", 1574, {0, {0}}, 0, 0 },
+  { "ear39", 1575, {0, {0}}, 0, 0 },
+  { "ear40", 1576, {0, {0}}, 0, 0 },
+  { "ear41", 1577, {0, {0}}, 0, 0 },
+  { "ear42", 1578, {0, {0}}, 0, 0 },
+  { "ear43", 1579, {0, {0}}, 0, 0 },
+  { "ear44", 1580, {0, {0}}, 0, 0 },
+  { "ear45", 1581, {0, {0}}, 0, 0 },
+  { "ear46", 1582, {0, {0}}, 0, 0 },
+  { "ear47", 1583, {0, {0}}, 0, 0 },
+  { "ear48", 1584, {0, {0}}, 0, 0 },
+  { "ear49", 1585, {0, {0}}, 0, 0 },
+  { "ear50", 1586, {0, {0}}, 0, 0 },
+  { "ear51", 1587, {0, {0}}, 0, 0 },
+  { "ear52", 1588, {0, {0}}, 0, 0 },
+  { "ear53", 1589, {0, {0}}, 0, 0 },
+  { "ear54", 1590, {0, {0}}, 0, 0 },
+  { "ear55", 1591, {0, {0}}, 0, 0 },
+  { "ear56", 1592, {0, {0}}, 0, 0 },
+  { "ear57", 1593, {0, {0}}, 0, 0 },
+  { "ear58", 1594, {0, {0}}, 0, 0 },
+  { "ear59", 1595, {0, {0}}, 0, 0 },
+  { "ear60", 1596, {0, {0}}, 0, 0 },
+  { "ear61", 1597, {0, {0}}, 0, 0 },
+  { "ear62", 1598, {0, {0}}, 0, 0 },
+  { "ear63", 1599, {0, {0}}, 0, 0 },
+  { "edr0", 1600, {0, {0}}, 0, 0 },
+  { "edr1", 1601, {0, {0}}, 0, 0 },
+  { "edr2", 1602, {0, {0}}, 0, 0 },
+  { "edr3", 1603, {0, {0}}, 0, 0 },
+  { "edr4", 1604, {0, {0}}, 0, 0 },
+  { "edr5", 1605, {0, {0}}, 0, 0 },
+  { "edr6", 1606, {0, {0}}, 0, 0 },
+  { "edr7", 1607, {0, {0}}, 0, 0 },
+  { "edr8", 1608, {0, {0}}, 0, 0 },
+  { "edr9", 1609, {0, {0}}, 0, 0 },
+  { "edr10", 1610, {0, {0}}, 0, 0 },
+  { "edr11", 1611, {0, {0}}, 0, 0 },
+  { "edr12", 1612, {0, {0}}, 0, 0 },
+  { "edr13", 1613, {0, {0}}, 0, 0 },
+  { "edr14", 1614, {0, {0}}, 0, 0 },
+  { "edr15", 1615, {0, {0}}, 0, 0 },
+  { "edr16", 1616, {0, {0}}, 0, 0 },
+  { "edr17", 1617, {0, {0}}, 0, 0 },
+  { "edr18", 1618, {0, {0}}, 0, 0 },
+  { "edr19", 1619, {0, {0}}, 0, 0 },
+  { "edr20", 1620, {0, {0}}, 0, 0 },
+  { "edr21", 1621, {0, {0}}, 0, 0 },
+  { "edr22", 1622, {0, {0}}, 0, 0 },
+  { "edr23", 1623, {0, {0}}, 0, 0 },
+  { "edr24", 1624, {0, {0}}, 0, 0 },
+  { "edr25", 1625, {0, {0}}, 0, 0 },
+  { "edr26", 1626, {0, {0}}, 0, 0 },
+  { "edr27", 1627, {0, {0}}, 0, 0 },
+  { "edr28", 1628, {0, {0}}, 0, 0 },
+  { "edr29", 1629, {0, {0}}, 0, 0 },
+  { "edr30", 1630, {0, {0}}, 0, 0 },
+  { "edr31", 1631, {0, {0}}, 0, 0 },
+  { "edr32", 1632, {0, {0}}, 0, 0 },
+  { "edr33", 1636, {0, {0}}, 0, 0 },
+  { "edr34", 1634, {0, {0}}, 0, 0 },
+  { "edr35", 1635, {0, {0}}, 0, 0 },
+  { "edr36", 1636, {0, {0}}, 0, 0 },
+  { "edr37", 1637, {0, {0}}, 0, 0 },
+  { "edr38", 1638, {0, {0}}, 0, 0 },
+  { "edr39", 1639, {0, {0}}, 0, 0 },
+  { "edr40", 1640, {0, {0}}, 0, 0 },
+  { "edr41", 1641, {0, {0}}, 0, 0 },
+  { "edr42", 1642, {0, {0}}, 0, 0 },
+  { "edr43", 1643, {0, {0}}, 0, 0 },
+  { "edr44", 1644, {0, {0}}, 0, 0 },
+  { "edr45", 1645, {0, {0}}, 0, 0 },
+  { "edr46", 1646, {0, {0}}, 0, 0 },
+  { "edr47", 1647, {0, {0}}, 0, 0 },
+  { "edr48", 1648, {0, {0}}, 0, 0 },
+  { "edr49", 1649, {0, {0}}, 0, 0 },
+  { "edr50", 1650, {0, {0}}, 0, 0 },
+  { "edr51", 1651, {0, {0}}, 0, 0 },
+  { "edr52", 1652, {0, {0}}, 0, 0 },
+  { "edr53", 1653, {0, {0}}, 0, 0 },
+  { "edr54", 1654, {0, {0}}, 0, 0 },
+  { "edr55", 1655, {0, {0}}, 0, 0 },
+  { "edr56", 1656, {0, {0}}, 0, 0 },
+  { "edr57", 1657, {0, {0}}, 0, 0 },
+  { "edr58", 1658, {0, {0}}, 0, 0 },
+  { "edr59", 1659, {0, {0}}, 0, 0 },
+  { "edr60", 1660, {0, {0}}, 0, 0 },
+  { "edr61", 1661, {0, {0}}, 0, 0 },
+  { "edr62", 1662, {0, {0}}, 0, 0 },
+  { "edr63", 1663, {0, {0}}, 0, 0 },
+  { "iamlr0", 1664, {0, {0}}, 0, 0 },
+  { "iamlr1", 1665, {0, {0}}, 0, 0 },
+  { "iamlr2", 1666, {0, {0}}, 0, 0 },
+  { "iamlr3", 1667, {0, {0}}, 0, 0 },
+  { "iamlr4", 1668, {0, {0}}, 0, 0 },
+  { "iamlr5", 1669, {0, {0}}, 0, 0 },
+  { "iamlr6", 1670, {0, {0}}, 0, 0 },
+  { "iamlr7", 1671, {0, {0}}, 0, 0 },
+  { "iamlr8", 1672, {0, {0}}, 0, 0 },
+  { "iamlr9", 1673, {0, {0}}, 0, 0 },
+  { "iamlr10", 1674, {0, {0}}, 0, 0 },
+  { "iamlr11", 1675, {0, {0}}, 0, 0 },
+  { "iamlr12", 1676, {0, {0}}, 0, 0 },
+  { "iamlr13", 1677, {0, {0}}, 0, 0 },
+  { "iamlr14", 1678, {0, {0}}, 0, 0 },
+  { "iamlr15", 1679, {0, {0}}, 0, 0 },
+  { "iamlr16", 1680, {0, {0}}, 0, 0 },
+  { "iamlr17", 1681, {0, {0}}, 0, 0 },
+  { "iamlr18", 1682, {0, {0}}, 0, 0 },
+  { "iamlr19", 1683, {0, {0}}, 0, 0 },
+  { "iamlr20", 1684, {0, {0}}, 0, 0 },
+  { "iamlr21", 1685, {0, {0}}, 0, 0 },
+  { "iamlr22", 1686, {0, {0}}, 0, 0 },
+  { "iamlr23", 1687, {0, {0}}, 0, 0 },
+  { "iamlr24", 1688, {0, {0}}, 0, 0 },
+  { "iamlr25", 1689, {0, {0}}, 0, 0 },
+  { "iamlr26", 1690, {0, {0}}, 0, 0 },
+  { "iamlr27", 1691, {0, {0}}, 0, 0 },
+  { "iamlr28", 1692, {0, {0}}, 0, 0 },
+  { "iamlr29", 1693, {0, {0}}, 0, 0 },
+  { "iamlr30", 1694, {0, {0}}, 0, 0 },
+  { "iamlr31", 1695, {0, {0}}, 0, 0 },
+  { "iamlr32", 1696, {0, {0}}, 0, 0 },
+  { "iamlr33", 1697, {0, {0}}, 0, 0 },
+  { "iamlr34", 1698, {0, {0}}, 0, 0 },
+  { "iamlr35", 1699, {0, {0}}, 0, 0 },
+  { "iamlr36", 1700, {0, {0}}, 0, 0 },
+  { "iamlr37", 1701, {0, {0}}, 0, 0 },
+  { "iamlr38", 1702, {0, {0}}, 0, 0 },
+  { "iamlr39", 1703, {0, {0}}, 0, 0 },
+  { "iamlr40", 1704, {0, {0}}, 0, 0 },
+  { "iamlr41", 1705, {0, {0}}, 0, 0 },
+  { "iamlr42", 1706, {0, {0}}, 0, 0 },
+  { "iamlr43", 1707, {0, {0}}, 0, 0 },
+  { "iamlr44", 1708, {0, {0}}, 0, 0 },
+  { "iamlr45", 1709, {0, {0}}, 0, 0 },
+  { "iamlr46", 1710, {0, {0}}, 0, 0 },
+  { "iamlr47", 1711, {0, {0}}, 0, 0 },
+  { "iamlr48", 1712, {0, {0}}, 0, 0 },
+  { "iamlr49", 1713, {0, {0}}, 0, 0 },
+  { "iamlr50", 1714, {0, {0}}, 0, 0 },
+  { "iamlr51", 1715, {0, {0}}, 0, 0 },
+  { "iamlr52", 1716, {0, {0}}, 0, 0 },
+  { "iamlr53", 1717, {0, {0}}, 0, 0 },
+  { "iamlr54", 1718, {0, {0}}, 0, 0 },
+  { "iamlr55", 1719, {0, {0}}, 0, 0 },
+  { "iamlr56", 1720, {0, {0}}, 0, 0 },
+  { "iamlr57", 1721, {0, {0}}, 0, 0 },
+  { "iamlr58", 1722, {0, {0}}, 0, 0 },
+  { "iamlr59", 1723, {0, {0}}, 0, 0 },
+  { "iamlr60", 1724, {0, {0}}, 0, 0 },
+  { "iamlr61", 1725, {0, {0}}, 0, 0 },
+  { "iamlr62", 1726, {0, {0}}, 0, 0 },
+  { "iamlr63", 1727, {0, {0}}, 0, 0 },
+  { "iampr0", 1728, {0, {0}}, 0, 0 },
+  { "iampr1", 1729, {0, {0}}, 0, 0 },
+  { "iampr2", 1730, {0, {0}}, 0, 0 },
+  { "iampr3", 1731, {0, {0}}, 0, 0 },
+  { "iampr4", 1732, {0, {0}}, 0, 0 },
+  { "iampr5", 1733, {0, {0}}, 0, 0 },
+  { "iampr6", 1734, {0, {0}}, 0, 0 },
+  { "iampr7", 1735, {0, {0}}, 0, 0 },
+  { "iampr8", 1736, {0, {0}}, 0, 0 },
+  { "iampr9", 1737, {0, {0}}, 0, 0 },
+  { "iampr10", 1738, {0, {0}}, 0, 0 },
+  { "iampr11", 1739, {0, {0}}, 0, 0 },
+  { "iampr12", 1740, {0, {0}}, 0, 0 },
+  { "iampr13", 1741, {0, {0}}, 0, 0 },
+  { "iampr14", 1742, {0, {0}}, 0, 0 },
+  { "iampr15", 1743, {0, {0}}, 0, 0 },
+  { "iampr16", 1744, {0, {0}}, 0, 0 },
+  { "iampr17", 1745, {0, {0}}, 0, 0 },
+  { "iampr18", 1746, {0, {0}}, 0, 0 },
+  { "iampr19", 1747, {0, {0}}, 0, 0 },
+  { "iampr20", 1748, {0, {0}}, 0, 0 },
+  { "iampr21", 1749, {0, {0}}, 0, 0 },
+  { "iampr22", 1750, {0, {0}}, 0, 0 },
+  { "iampr23", 1751, {0, {0}}, 0, 0 },
+  { "iampr24", 1752, {0, {0}}, 0, 0 },
+  { "iampr25", 1753, {0, {0}}, 0, 0 },
+  { "iampr26", 1754, {0, {0}}, 0, 0 },
+  { "iampr27", 1755, {0, {0}}, 0, 0 },
+  { "iampr28", 1756, {0, {0}}, 0, 0 },
+  { "iampr29", 1757, {0, {0}}, 0, 0 },
+  { "iampr30", 1758, {0, {0}}, 0, 0 },
+  { "iampr31", 1759, {0, {0}}, 0, 0 },
+  { "iampr32", 1760, {0, {0}}, 0, 0 },
+  { "iampr33", 1761, {0, {0}}, 0, 0 },
+  { "iampr34", 1762, {0, {0}}, 0, 0 },
+  { "iampr35", 1763, {0, {0}}, 0, 0 },
+  { "iampr36", 1764, {0, {0}}, 0, 0 },
+  { "iampr37", 1765, {0, {0}}, 0, 0 },
+  { "iampr38", 1766, {0, {0}}, 0, 0 },
+  { "iampr39", 1767, {0, {0}}, 0, 0 },
+  { "iampr40", 1768, {0, {0}}, 0, 0 },
+  { "iampr41", 1769, {0, {0}}, 0, 0 },
+  { "iampr42", 1770, {0, {0}}, 0, 0 },
+  { "iampr43", 1771, {0, {0}}, 0, 0 },
+  { "iampr44", 1772, {0, {0}}, 0, 0 },
+  { "iampr45", 1773, {0, {0}}, 0, 0 },
+  { "iampr46", 1774, {0, {0}}, 0, 0 },
+  { "iampr47", 1775, {0, {0}}, 0, 0 },
+  { "iampr48", 1776, {0, {0}}, 0, 0 },
+  { "iampr49", 1777, {0, {0}}, 0, 0 },
+  { "iampr50", 1778, {0, {0}}, 0, 0 },
+  { "iampr51", 1779, {0, {0}}, 0, 0 },
+  { "iampr52", 1780, {0, {0}}, 0, 0 },
+  { "iampr53", 1781, {0, {0}}, 0, 0 },
+  { "iampr54", 1782, {0, {0}}, 0, 0 },
+  { "iampr55", 1783, {0, {0}}, 0, 0 },
+  { "iampr56", 1784, {0, {0}}, 0, 0 },
+  { "iampr57", 1785, {0, {0}}, 0, 0 },
+  { "iampr58", 1786, {0, {0}}, 0, 0 },
+  { "iampr59", 1787, {0, {0}}, 0, 0 },
+  { "iampr60", 1788, {0, {0}}, 0, 0 },
+  { "iampr61", 1789, {0, {0}}, 0, 0 },
+  { "iampr62", 1790, {0, {0}}, 0, 0 },
+  { "iampr63", 1791, {0, {0}}, 0, 0 },
+  { "damlr0", 1792, {0, {0}}, 0, 0 },
+  { "damlr1", 1793, {0, {0}}, 0, 0 },
+  { "damlr2", 1794, {0, {0}}, 0, 0 },
+  { "damlr3", 1795, {0, {0}}, 0, 0 },
+  { "damlr4", 1796, {0, {0}}, 0, 0 },
+  { "damlr5", 1797, {0, {0}}, 0, 0 },
+  { "damlr6", 1798, {0, {0}}, 0, 0 },
+  { "damlr7", 1799, {0, {0}}, 0, 0 },
+  { "damlr8", 1800, {0, {0}}, 0, 0 },
+  { "damlr9", 1801, {0, {0}}, 0, 0 },
+  { "damlr10", 1802, {0, {0}}, 0, 0 },
+  { "damlr11", 1803, {0, {0}}, 0, 0 },
+  { "damlr12", 1804, {0, {0}}, 0, 0 },
+  { "damlr13", 1805, {0, {0}}, 0, 0 },
+  { "damlr14", 1806, {0, {0}}, 0, 0 },
+  { "damlr15", 1807, {0, {0}}, 0, 0 },
+  { "damlr16", 1808, {0, {0}}, 0, 0 },
+  { "damlr17", 1809, {0, {0}}, 0, 0 },
+  { "damlr18", 1810, {0, {0}}, 0, 0 },
+  { "damlr19", 1811, {0, {0}}, 0, 0 },
+  { "damlr20", 1812, {0, {0}}, 0, 0 },
+  { "damlr21", 1813, {0, {0}}, 0, 0 },
+  { "damlr22", 1814, {0, {0}}, 0, 0 },
+  { "damlr23", 1815, {0, {0}}, 0, 0 },
+  { "damlr24", 1816, {0, {0}}, 0, 0 },
+  { "damlr25", 1817, {0, {0}}, 0, 0 },
+  { "damlr26", 1818, {0, {0}}, 0, 0 },
+  { "damlr27", 1819, {0, {0}}, 0, 0 },
+  { "damlr28", 1820, {0, {0}}, 0, 0 },
+  { "damlr29", 1821, {0, {0}}, 0, 0 },
+  { "damlr30", 1822, {0, {0}}, 0, 0 },
+  { "damlr31", 1823, {0, {0}}, 0, 0 },
+  { "damlr32", 1824, {0, {0}}, 0, 0 },
+  { "damlr33", 1825, {0, {0}}, 0, 0 },
+  { "damlr34", 1826, {0, {0}}, 0, 0 },
+  { "damlr35", 1827, {0, {0}}, 0, 0 },
+  { "damlr36", 1828, {0, {0}}, 0, 0 },
+  { "damlr37", 1829, {0, {0}}, 0, 0 },
+  { "damlr38", 1830, {0, {0}}, 0, 0 },
+  { "damlr39", 1831, {0, {0}}, 0, 0 },
+  { "damlr40", 1832, {0, {0}}, 0, 0 },
+  { "damlr41", 1833, {0, {0}}, 0, 0 },
+  { "damlr42", 1834, {0, {0}}, 0, 0 },
+  { "damlr43", 1835, {0, {0}}, 0, 0 },
+  { "damlr44", 1836, {0, {0}}, 0, 0 },
+  { "damlr45", 1837, {0, {0}}, 0, 0 },
+  { "damlr46", 1838, {0, {0}}, 0, 0 },
+  { "damlr47", 1839, {0, {0}}, 0, 0 },
+  { "damlr48", 1840, {0, {0}}, 0, 0 },
+  { "damlr49", 1841, {0, {0}}, 0, 0 },
+  { "damlr50", 1842, {0, {0}}, 0, 0 },
+  { "damlr51", 1843, {0, {0}}, 0, 0 },
+  { "damlr52", 1844, {0, {0}}, 0, 0 },
+  { "damlr53", 1845, {0, {0}}, 0, 0 },
+  { "damlr54", 1846, {0, {0}}, 0, 0 },
+  { "damlr55", 1847, {0, {0}}, 0, 0 },
+  { "damlr56", 1848, {0, {0}}, 0, 0 },
+  { "damlr57", 1849, {0, {0}}, 0, 0 },
+  { "damlr58", 1850, {0, {0}}, 0, 0 },
+  { "damlr59", 1851, {0, {0}}, 0, 0 },
+  { "damlr60", 1852, {0, {0}}, 0, 0 },
+  { "damlr61", 1853, {0, {0}}, 0, 0 },
+  { "damlr62", 1854, {0, {0}}, 0, 0 },
+  { "damlr63", 1855, {0, {0}}, 0, 0 },
+  { "dampr0", 1856, {0, {0}}, 0, 0 },
+  { "dampr1", 1857, {0, {0}}, 0, 0 },
+  { "dampr2", 1858, {0, {0}}, 0, 0 },
+  { "dampr3", 1859, {0, {0}}, 0, 0 },
+  { "dampr4", 1860, {0, {0}}, 0, 0 },
+  { "dampr5", 1861, {0, {0}}, 0, 0 },
+  { "dampr6", 1862, {0, {0}}, 0, 0 },
+  { "dampr7", 1863, {0, {0}}, 0, 0 },
+  { "dampr8", 1864, {0, {0}}, 0, 0 },
+  { "dampr9", 1865, {0, {0}}, 0, 0 },
+  { "dampr10", 1866, {0, {0}}, 0, 0 },
+  { "dampr11", 1867, {0, {0}}, 0, 0 },
+  { "dampr12", 1868, {0, {0}}, 0, 0 },
+  { "dampr13", 1869, {0, {0}}, 0, 0 },
+  { "dampr14", 1870, {0, {0}}, 0, 0 },
+  { "dampr15", 1871, {0, {0}}, 0, 0 },
+  { "dampr16", 1872, {0, {0}}, 0, 0 },
+  { "dampr17", 1873, {0, {0}}, 0, 0 },
+  { "dampr18", 1874, {0, {0}}, 0, 0 },
+  { "dampr19", 1875, {0, {0}}, 0, 0 },
+  { "dampr20", 1876, {0, {0}}, 0, 0 },
+  { "dampr21", 1877, {0, {0}}, 0, 0 },
+  { "dampr22", 1878, {0, {0}}, 0, 0 },
+  { "dampr23", 1879, {0, {0}}, 0, 0 },
+  { "dampr24", 1880, {0, {0}}, 0, 0 },
+  { "dampr25", 1881, {0, {0}}, 0, 0 },
+  { "dampr26", 1882, {0, {0}}, 0, 0 },
+  { "dampr27", 1883, {0, {0}}, 0, 0 },
+  { "dampr28", 1884, {0, {0}}, 0, 0 },
+  { "dampr29", 1885, {0, {0}}, 0, 0 },
+  { "dampr30", 1886, {0, {0}}, 0, 0 },
+  { "dampr31", 1887, {0, {0}}, 0, 0 },
+  { "dampr32", 1888, {0, {0}}, 0, 0 },
+  { "dampr33", 1889, {0, {0}}, 0, 0 },
+  { "dampr34", 1890, {0, {0}}, 0, 0 },
+  { "dampr35", 1891, {0, {0}}, 0, 0 },
+  { "dampr36", 1892, {0, {0}}, 0, 0 },
+  { "dampr37", 1893, {0, {0}}, 0, 0 },
+  { "dampr38", 1894, {0, {0}}, 0, 0 },
+  { "dampr39", 1895, {0, {0}}, 0, 0 },
+  { "dampr40", 1896, {0, {0}}, 0, 0 },
+  { "dampr41", 1897, {0, {0}}, 0, 0 },
+  { "dampr42", 1898, {0, {0}}, 0, 0 },
+  { "dampr43", 1899, {0, {0}}, 0, 0 },
+  { "dampr44", 1900, {0, {0}}, 0, 0 },
+  { "dampr45", 1901, {0, {0}}, 0, 0 },
+  { "dampr46", 1902, {0, {0}}, 0, 0 },
+  { "dampr47", 1903, {0, {0}}, 0, 0 },
+  { "dampr48", 1904, {0, {0}}, 0, 0 },
+  { "dampr49", 1905, {0, {0}}, 0, 0 },
+  { "dampr50", 1906, {0, {0}}, 0, 0 },
+  { "dampr51", 1907, {0, {0}}, 0, 0 },
+  { "dampr52", 1908, {0, {0}}, 0, 0 },
+  { "dampr53", 1909, {0, {0}}, 0, 0 },
+  { "dampr54", 1910, {0, {0}}, 0, 0 },
+  { "dampr55", 1911, {0, {0}}, 0, 0 },
+  { "dampr56", 1912, {0, {0}}, 0, 0 },
+  { "dampr57", 1913, {0, {0}}, 0, 0 },
+  { "dampr58", 1914, {0, {0}}, 0, 0 },
+  { "dampr59", 1915, {0, {0}}, 0, 0 },
+  { "dampr60", 1916, {0, {0}}, 0, 0 },
+  { "dampr61", 1917, {0, {0}}, 0, 0 },
+  { "dampr62", 1918, {0, {0}}, 0, 0 },
+  { "dampr63", 1919, {0, {0}}, 0, 0 },
+  { "amcr", 1920, {0, {0}}, 0, 0 },
+  { "stbar", 1921, {0, {0}}, 0, 0 },
+  { "mmcr", 1922, {0, {0}}, 0, 0 },
+  { "dcr", 2048, {0, {0}}, 0, 0 },
+  { "brr", 2049, {0, {0}}, 0, 0 },
+  { "nmar", 2050, {0, {0}}, 0, 0 },
+  { "ibar0", 2052, {0, {0}}, 0, 0 },
+  { "ibar1", 2053, {0, {0}}, 0, 0 },
+  { "ibar2", 2054, {0, {0}}, 0, 0 },
+  { "ibar3", 2055, {0, {0}}, 0, 0 },
+  { "dbar0", 2056, {0, {0}}, 0, 0 },
+  { "dbar1", 2057, {0, {0}}, 0, 0 },
+  { "dbar2", 2058, {0, {0}}, 0, 0 },
+  { "dbar3", 2059, {0, {0}}, 0, 0 },
+  { "dbdr00", 2060, {0, {0}}, 0, 0 },
+  { "dbdr01", 2061, {0, {0}}, 0, 0 },
+  { "dbdr02", 2062, {0, {0}}, 0, 0 },
+  { "dbdr03", 2063, {0, {0}}, 0, 0 },
+  { "dbdr10", 2064, {0, {0}}, 0, 0 },
+  { "dbdr11", 2065, {0, {0}}, 0, 0 },
+  { "dbdr12", 2066, {0, {0}}, 0, 0 },
+  { "dbdr13", 2067, {0, {0}}, 0, 0 },
+  { "dbdr20", 2068, {0, {0}}, 0, 0 },
+  { "dbdr21", 2069, {0, {0}}, 0, 0 },
+  { "dbdr22", 2070, {0, {0}}, 0, 0 },
+  { "dbdr23", 2071, {0, {0}}, 0, 0 },
+  { "dbdr30", 2072, {0, {0}}, 0, 0 },
+  { "dbdr31", 2073, {0, {0}}, 0, 0 },
+  { "dbdr32", 2074, {0, {0}}, 0, 0 },
+  { "dbdr33", 2075, {0, {0}}, 0, 0 },
+  { "dbmr00", 2076, {0, {0}}, 0, 0 },
+  { "dbmr01", 2077, {0, {0}}, 0, 0 },
+  { "dbmr02", 2078, {0, {0}}, 0, 0 },
+  { "dbmr03", 2079, {0, {0}}, 0, 0 },
+  { "dbmr10", 2080, {0, {0}}, 0, 0 },
+  { "dbmr11", 2081, {0, {0}}, 0, 0 },
+  { "dbmr12", 2082, {0, {0}}, 0, 0 },
+  { "dbmr13", 2083, {0, {0}}, 0, 0 },
+  { "dbmr20", 2084, {0, {0}}, 0, 0 },
+  { "dbmr21", 2085, {0, {0}}, 0, 0 },
+  { "dbmr22", 2086, {0, {0}}, 0, 0 },
+  { "dbmr23", 2087, {0, {0}}, 0, 0 },
+  { "dbmr30", 2088, {0, {0}}, 0, 0 },
+  { "dbmr31", 2089, {0, {0}}, 0, 0 },
+  { "dbmr32", 2090, {0, {0}}, 0, 0 },
+  { "dbmr33", 2091, {0, {0}}, 0, 0 },
+  { "cpcfr", 2092, {0, {0}}, 0, 0 },
+  { "cpcr", 2093, {0, {0}}, 0, 0 },
+  { "cpsr", 2094, {0, {0}}, 0, 0 },
+  { "cpesr0", 2096, {0, {0}}, 0, 0 },
+  { "cpesr1", 2097, {0, {0}}, 0, 0 },
+  { "cpemr0", 2098, {0, {0}}, 0, 0 },
+  { "cpemr1", 2099, {0, {0}}, 0, 0 },
+  { "ihsr8", 3848, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_spr_names =
+{
+  & frv_cgen_opval_spr_names_entries[0],
+  1005,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] =
+{
+  { "accg0", 0, {0, {0}}, 0, 0 },
+  { "accg1", 1, {0, {0}}, 0, 0 },
+  { "accg2", 2, {0, {0}}, 0, 0 },
+  { "accg3", 3, {0, {0}}, 0, 0 },
+  { "accg4", 4, {0, {0}}, 0, 0 },
+  { "accg5", 5, {0, {0}}, 0, 0 },
+  { "accg6", 6, {0, {0}}, 0, 0 },
+  { "accg7", 7, {0, {0}}, 0, 0 },
+  { "accg8", 8, {0, {0}}, 0, 0 },
+  { "accg9", 9, {0, {0}}, 0, 0 },
+  { "accg10", 10, {0, {0}}, 0, 0 },
+  { "accg11", 11, {0, {0}}, 0, 0 },
+  { "accg12", 12, {0, {0}}, 0, 0 },
+  { "accg13", 13, {0, {0}}, 0, 0 },
+  { "accg14", 14, {0, {0}}, 0, 0 },
+  { "accg15", 15, {0, {0}}, 0, 0 },
+  { "accg16", 16, {0, {0}}, 0, 0 },
+  { "accg17", 17, {0, {0}}, 0, 0 },
+  { "accg18", 18, {0, {0}}, 0, 0 },
+  { "accg19", 19, {0, {0}}, 0, 0 },
+  { "accg20", 20, {0, {0}}, 0, 0 },
+  { "accg21", 21, {0, {0}}, 0, 0 },
+  { "accg22", 22, {0, {0}}, 0, 0 },
+  { "accg23", 23, {0, {0}}, 0, 0 },
+  { "accg24", 24, {0, {0}}, 0, 0 },
+  { "accg25", 25, {0, {0}}, 0, 0 },
+  { "accg26", 26, {0, {0}}, 0, 0 },
+  { "accg27", 27, {0, {0}}, 0, 0 },
+  { "accg28", 28, {0, {0}}, 0, 0 },
+  { "accg29", 29, {0, {0}}, 0, 0 },
+  { "accg30", 30, {0, {0}}, 0, 0 },
+  { "accg31", 31, {0, {0}}, 0, 0 },
+  { "accg32", 32, {0, {0}}, 0, 0 },
+  { "accg33", 33, {0, {0}}, 0, 0 },
+  { "accg34", 34, {0, {0}}, 0, 0 },
+  { "accg35", 35, {0, {0}}, 0, 0 },
+  { "accg36", 36, {0, {0}}, 0, 0 },
+  { "accg37", 37, {0, {0}}, 0, 0 },
+  { "accg38", 38, {0, {0}}, 0, 0 },
+  { "accg39", 39, {0, {0}}, 0, 0 },
+  { "accg40", 40, {0, {0}}, 0, 0 },
+  { "accg41", 41, {0, {0}}, 0, 0 },
+  { "accg42", 42, {0, {0}}, 0, 0 },
+  { "accg43", 43, {0, {0}}, 0, 0 },
+  { "accg44", 44, {0, {0}}, 0, 0 },
+  { "accg45", 45, {0, {0}}, 0, 0 },
+  { "accg46", 46, {0, {0}}, 0, 0 },
+  { "accg47", 47, {0, {0}}, 0, 0 },
+  { "accg48", 48, {0, {0}}, 0, 0 },
+  { "accg49", 49, {0, {0}}, 0, 0 },
+  { "accg50", 50, {0, {0}}, 0, 0 },
+  { "accg51", 51, {0, {0}}, 0, 0 },
+  { "accg52", 52, {0, {0}}, 0, 0 },
+  { "accg53", 53, {0, {0}}, 0, 0 },
+  { "accg54", 54, {0, {0}}, 0, 0 },
+  { "accg55", 55, {0, {0}}, 0, 0 },
+  { "accg56", 56, {0, {0}}, 0, 0 },
+  { "accg57", 57, {0, {0}}, 0, 0 },
+  { "accg58", 58, {0, {0}}, 0, 0 },
+  { "accg59", 59, {0, {0}}, 0, 0 },
+  { "accg60", 60, {0, {0}}, 0, 0 },
+  { "accg61", 61, {0, {0}}, 0, 0 },
+  { "accg62", 62, {0, {0}}, 0, 0 },
+  { "accg63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_accg_names =
+{
+  & frv_cgen_opval_accg_names_entries[0],
+  64,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] =
+{
+  { "acc0", 0, {0, {0}}, 0, 0 },
+  { "acc1", 1, {0, {0}}, 0, 0 },
+  { "acc2", 2, {0, {0}}, 0, 0 },
+  { "acc3", 3, {0, {0}}, 0, 0 },
+  { "acc4", 4, {0, {0}}, 0, 0 },
+  { "acc5", 5, {0, {0}}, 0, 0 },
+  { "acc6", 6, {0, {0}}, 0, 0 },
+  { "acc7", 7, {0, {0}}, 0, 0 },
+  { "acc8", 8, {0, {0}}, 0, 0 },
+  { "acc9", 9, {0, {0}}, 0, 0 },
+  { "acc10", 10, {0, {0}}, 0, 0 },
+  { "acc11", 11, {0, {0}}, 0, 0 },
+  { "acc12", 12, {0, {0}}, 0, 0 },
+  { "acc13", 13, {0, {0}}, 0, 0 },
+  { "acc14", 14, {0, {0}}, 0, 0 },
+  { "acc15", 15, {0, {0}}, 0, 0 },
+  { "acc16", 16, {0, {0}}, 0, 0 },
+  { "acc17", 17, {0, {0}}, 0, 0 },
+  { "acc18", 18, {0, {0}}, 0, 0 },
+  { "acc19", 19, {0, {0}}, 0, 0 },
+  { "acc20", 20, {0, {0}}, 0, 0 },
+  { "acc21", 21, {0, {0}}, 0, 0 },
+  { "acc22", 22, {0, {0}}, 0, 0 },
+  { "acc23", 23, {0, {0}}, 0, 0 },
+  { "acc24", 24, {0, {0}}, 0, 0 },
+  { "acc25", 25, {0, {0}}, 0, 0 },
+  { "acc26", 26, {0, {0}}, 0, 0 },
+  { "acc27", 27, {0, {0}}, 0, 0 },
+  { "acc28", 28, {0, {0}}, 0, 0 },
+  { "acc29", 29, {0, {0}}, 0, 0 },
+  { "acc30", 30, {0, {0}}, 0, 0 },
+  { "acc31", 31, {0, {0}}, 0, 0 },
+  { "acc32", 32, {0, {0}}, 0, 0 },
+  { "acc33", 33, {0, {0}}, 0, 0 },
+  { "acc34", 34, {0, {0}}, 0, 0 },
+  { "acc35", 35, {0, {0}}, 0, 0 },
+  { "acc36", 36, {0, {0}}, 0, 0 },
+  { "acc37", 37, {0, {0}}, 0, 0 },
+  { "acc38", 38, {0, {0}}, 0, 0 },
+  { "acc39", 39, {0, {0}}, 0, 0 },
+  { "acc40", 40, {0, {0}}, 0, 0 },
+  { "acc41", 41, {0, {0}}, 0, 0 },
+  { "acc42", 42, {0, {0}}, 0, 0 },
+  { "acc43", 43, {0, {0}}, 0, 0 },
+  { "acc44", 44, {0, {0}}, 0, 0 },
+  { "acc45", 45, {0, {0}}, 0, 0 },
+  { "acc46", 46, {0, {0}}, 0, 0 },
+  { "acc47", 47, {0, {0}}, 0, 0 },
+  { "acc48", 48, {0, {0}}, 0, 0 },
+  { "acc49", 49, {0, {0}}, 0, 0 },
+  { "acc50", 50, {0, {0}}, 0, 0 },
+  { "acc51", 51, {0, {0}}, 0, 0 },
+  { "acc52", 52, {0, {0}}, 0, 0 },
+  { "acc53", 53, {0, {0}}, 0, 0 },
+  { "acc54", 54, {0, {0}}, 0, 0 },
+  { "acc55", 55, {0, {0}}, 0, 0 },
+  { "acc56", 56, {0, {0}}, 0, 0 },
+  { "acc57", 57, {0, {0}}, 0, 0 },
+  { "acc58", 58, {0, {0}}, 0, 0 },
+  { "acc59", 59, {0, {0}}, 0, 0 },
+  { "acc60", 60, {0, {0}}, 0, 0 },
+  { "acc61", 61, {0, {0}}, 0, 0 },
+  { "acc62", 62, {0, {0}}, 0, 0 },
+  { "acc63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_acc_names =
+{
+  & frv_cgen_opval_acc_names_entries[0],
+  64,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] =
+{
+  { "icc0", 0, {0, {0}}, 0, 0 },
+  { "icc1", 1, {0, {0}}, 0, 0 },
+  { "icc2", 2, {0, {0}}, 0, 0 },
+  { "icc3", 3, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_iccr_names =
+{
+  & frv_cgen_opval_iccr_names_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] =
+{
+  { "fcc0", 0, {0, {0}}, 0, 0 },
+  { "fcc1", 1, {0, {0}}, 0, 0 },
+  { "fcc2", 2, {0, {0}}, 0, 0 },
+  { "fcc3", 3, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_fccr_names =
+{
+  & frv_cgen_opval_fccr_names_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] =
+{
+  { "cc0", 0, {0, {0}}, 0, 0 },
+  { "cc1", 1, {0, {0}}, 0, 0 },
+  { "cc2", 2, {0, {0}}, 0, 0 },
+  { "cc3", 3, {0, {0}}, 0, 0 },
+  { "cc4", 4, {0, {0}}, 0, 0 },
+  { "cc5", 5, {0, {0}}, 0, 0 },
+  { "cc6", 6, {0, {0}}, 0, 0 },
+  { "cc7", 7, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_cccr_names =
+{
+  & frv_cgen_opval_cccr_names_entries[0],
+  8,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] =
+{
+  { "", 1, {0, {0}}, 0, 0 },
+  { ".p", 0, {0, {0}}, 0, 0 },
+  { ".P", 0, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_h_pack =
+{
+  & frv_cgen_opval_h_pack_entries[0],
+  3,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] =
+{
+  { "", 2, {0, {0}}, 0, 0 },
+  { "", 0, {0, {0}}, 0, 0 },
+  { "", 1, {0, {0}}, 0, 0 },
+  { "", 3, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_h_hint_taken =
+{
+  & frv_cgen_opval_h_hint_taken_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] =
+{
+  { "", 0, {0, {0}}, 0, 0 },
+  { "", 1, {0, {0}}, 0, 0 },
+  { "", 2, {0, {0}}, 0, 0 },
+  { "", 3, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken =
+{
+  & frv_cgen_opval_h_hint_not_taken_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+
+/* The hardware table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY frv_cgen_hw_table[] =
+{
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
+  { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } },
+  { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } },
+  { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
+  { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } },
+  { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } },
+  { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } },
+  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction field table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD frv_cgen_ifld_table[] =
+{
+  { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+  { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
+  { 0, 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] =
+{
+    { 0, &(frv_cgen_ifld_table[46]) },
+    { 0, &(frv_cgen_ifld_table[47]) },
+    {0,0}
+};
+const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] =
+{
+    { 0, &(frv_cgen_ifld_table[58]) },
+    { 0, &(frv_cgen_ifld_table[59]) },
+    {0,0}
+};
+const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] =
+{
+    { 0, &(frv_cgen_ifld_table[61]) },
+    { 0, &(frv_cgen_ifld_table[62]) },
+    {0,0}
+};
+
+/* The operand table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) FRV_OPERAND_##op
+#else
+#define OPERAND(op) FRV_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND frv_cgen_operand_table[] =
+{
+/* pc: program counter */
+  { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
+    { 0, &(frv_cgen_ifld_table[0]) }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* pack: packing bit */
+  { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
+    { 0, &(frv_cgen_ifld_table[2]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRi: source register 1 */
+  { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
+    { 0, &(frv_cgen_ifld_table[8]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRj: source register 2 */
+  { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
+    { 0, &(frv_cgen_ifld_table[9]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRk: destination register */
+  { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
+    { 0, &(frv_cgen_ifld_table[10]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRkhi: destination register */
+  { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
+    { 0, &(frv_cgen_ifld_table[10]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRklo: destination register */
+  { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
+    { 0, &(frv_cgen_ifld_table[10]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* GRdoublek: destination register */
+  { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
+    { 0, &(frv_cgen_ifld_table[10]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACC40Si: signed accumulator */
+  { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
+    { 0, &(frv_cgen_ifld_table[19]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACC40Ui: unsigned accumulator */
+  { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
+    { 0, &(frv_cgen_ifld_table[20]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACC40Sk: target accumulator */
+  { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
+    { 0, &(frv_cgen_ifld_table[21]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACC40Uk: target accumulator */
+  { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
+    { 0, &(frv_cgen_ifld_table[22]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACCGi: source register */
+  { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
+    { 0, &(frv_cgen_ifld_table[17]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ACCGk: target register */
+  { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
+    { 0, &(frv_cgen_ifld_table[18]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CPRi: source register */
+  { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
+    { 0, &(frv_cgen_ifld_table[14]) }, 
+    { 0, { (1<<MACH_FRV) } }  },
+/* CPRj: source register */
+  { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
+    { 0, &(frv_cgen_ifld_table[15]) }, 
+    { 0, { (1<<MACH_FRV) } }  },
+/* CPRk: destination register */
+  { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
+    { 0, &(frv_cgen_ifld_table[16]) }, 
+    { 0, { (1<<MACH_FRV) } }  },
+/* CPRdoublek: destination register */
+  { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
+    { 0, &(frv_cgen_ifld_table[16]) }, 
+    { 0, { (1<<MACH_FRV) } }  },
+/* FRinti: source register 1 */
+  { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
+    { 0, &(frv_cgen_ifld_table[11]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRintj: source register 2 */
+  { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
+    { 0, &(frv_cgen_ifld_table[12]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRintk: target register */
+  { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
+    { 0, &(frv_cgen_ifld_table[13]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRi: source register 1 */
+  { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
+    { 0, &(frv_cgen_ifld_table[11]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRj: source register 2 */
+  { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
+    { 0, &(frv_cgen_ifld_table[12]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRk: destination register */
+  { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
+    { 0, &(frv_cgen_ifld_table[13]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRkhi: destination register */
+  { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
+    { 0, &(frv_cgen_ifld_table[13]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRklo: destination register */
+  { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
+    { 0, &(frv_cgen_ifld_table[13]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRdoublei: source register 1 */
+  { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
+    { 0, &(frv_cgen_ifld_table[11]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRdoublej: source register 2 */
+  { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
+    { 0, &(frv_cgen_ifld_table[12]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FRdoublek: target register */
+  { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
+    { 0, &(frv_cgen_ifld_table[13]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CRi: source register 1 */
+  { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
+    { 0, &(frv_cgen_ifld_table[23]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CRj: source register 2 */
+  { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
+    { 0, &(frv_cgen_ifld_table[24]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CRj_int: destination register */
+  { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
+    { 0, &(frv_cgen_ifld_table[27]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CRj_float: destination register */
+  { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
+    { 0, &(frv_cgen_ifld_table[28]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CRk: destination register */
+  { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
+    { 0, &(frv_cgen_ifld_table[25]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* CCi: condition   register */
+  { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
+    { 0, &(frv_cgen_ifld_table[26]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ICCi_1: condition   register */
+  { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
+    { 0, &(frv_cgen_ifld_table[29]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ICCi_2: condition   register */
+  { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
+    { 0, &(frv_cgen_ifld_table[30]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* ICCi_3: condition   register */
+  { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
+    { 0, &(frv_cgen_ifld_table[31]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FCCi_1: condition   register */
+  { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
+    { 0, &(frv_cgen_ifld_table[32]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FCCi_2: condition   register */
+  { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
+    { 0, &(frv_cgen_ifld_table[33]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FCCi_3: condition   register */
+  { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
+    { 0, &(frv_cgen_ifld_table[34]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* FCCk: condition   register */
+  { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
+    { 0, &(frv_cgen_ifld_table[35]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* eir: exception insn reg */
+  { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
+    { 0, &(frv_cgen_ifld_table[36]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* s10: 10 bit signed immediate */
+  { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
+    { 0, &(frv_cgen_ifld_table[37]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* u16: 16 bit unsigned immediate */
+  { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
+    { 0, &(frv_cgen_ifld_table[40]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* s16: 16 bit signed   immediate */
+  { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
+    { 0, &(frv_cgen_ifld_table[41]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* s6: 6  bit signed   immediate */
+  { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
+    { 0, &(frv_cgen_ifld_table[42]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* s6_1: 6  bit signed   immediate */
+  { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
+    { 0, &(frv_cgen_ifld_table[43]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* u6: 6  bit unsigned immediate */
+  { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
+    { 0, &(frv_cgen_ifld_table[44]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* s5: 5  bit signed   immediate */
+  { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
+    { 0, &(frv_cgen_ifld_table[45]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* cond: conditional arithmetic */
+  { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
+    { 0, &(frv_cgen_ifld_table[50]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* ccond: lr branch condition */
+  { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
+    { 0, &(frv_cgen_ifld_table[51]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* hint: 2 bit branch predictor */
+  { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
+    { 0, &(frv_cgen_ifld_table[52]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* hint_taken: 2 bit branch predictor */
+  { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
+    { 0, &(frv_cgen_ifld_table[52]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* hint_not_taken: 2 bit branch predictor */
+  { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
+    { 0, &(frv_cgen_ifld_table[52]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* LI: link indicator */
+  { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
+    { 0, &(frv_cgen_ifld_table[53]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* lock: cache lock indicator */
+  { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
+    { 0, &(frv_cgen_ifld_table[54]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* debug: debug mode indicator */
+  { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
+    { 0, &(frv_cgen_ifld_table[55]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* A: all accumulator indicator */
+  { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1,
+    { 0, &(frv_cgen_ifld_table[56]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* ae: all entries indicator */
+  { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
+    { 0, &(frv_cgen_ifld_table[57]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* label16: 18 bit pc relative address */
+  { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
+    { 0, &(frv_cgen_ifld_table[60]) }, 
+    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
+/* label24: 26 bit pc relative address */
+  { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
+    { 2, &(FRV_F_LABEL24_MULTI_IFIELD[0]) }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+/* d12: 12 bit signed immediate */
+  { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
+    { 0, &(frv_cgen_ifld_table[39]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* s12: 12 bit signed immediate */
+  { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
+    { 0, &(frv_cgen_ifld_table[39]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* u12: 12 bit signed immediate */
+  { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
+    { 2, &(FRV_F_U12_MULTI_IFIELD[0]) }, 
+    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+/* spr: special purpose register */
+  { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
+    { 2, &(FRV_F_SPR_MULTI_IFIELD[0]) }, 
+    { 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
+/* ulo16: 16 bit unsigned immediate, for #lo() */
+  { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
+    { 0, &(frv_cgen_ifld_table[40]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* slo16: 16 bit unsigned immediate, for #lo() */
+  { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
+    { 0, &(frv_cgen_ifld_table[41]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* uhi16: 16 bit unsigned immediate, for #hi() */
+  { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
+    { 0, &(frv_cgen_ifld_table[40]) }, 
+    { 0, { (1<<MACH_BASE) } }  },
+/* psr_esr: PSR.ESR bit */
+  { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* psr_s: PSR.S   bit */
+  { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* psr_ps: PSR.PS  bit */
+  { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* psr_et: PSR.ET  bit */
+  { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* bpsr_bs: BPSR.BS  bit */
+  { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* bpsr_bet: BPSR.BET bit */
+  { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* tbr_tba: TBR.TBA */
+  { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+/* tbr_tt: TBR.TT */
+  { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
+    { 0, 0 }, 
+    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
+  { 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction table.  */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { 0, 0, 0, 0, {0, {0}} },
+/* add$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_ADD, "add", "add", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sub$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SUB, "sub", "sub", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* and$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_AND, "and", "and", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* or$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_OR, "or", "or", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* xor$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_XOR, "xor", "xor", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* not$pack $GRj,$GRk */
+  {
+    FRV_INSN_NOT, "not", "not", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sdiv$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SDIV, "sdiv", "sdiv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* nsdiv$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+  },
+/* udiv$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_UDIV, "udiv", "udiv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* nudiv$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+  },
+/* smul$pack $GRi,$GRj,$GRdoublek */
+  {
+    FRV_INSN_SMUL, "smul", "smul", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* umul$pack $GRi,$GRj,$GRdoublek */
+  {
+    FRV_INSN_UMUL, "umul", "umul", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sll$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SLL, "sll", "sll", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* srl$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SRL, "srl", "srl", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sra$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SRA, "sra", "sra", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* scan$pack $GRi,$GRj,$GRk */
+  {
+    FRV_INSN_SCAN, "scan", "scan", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CADD, "cadd", "cadd", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSUB, "csub", "csub", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CAND, "cand", "cand", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_COR, "cor", "cor", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CXOR, "cxor", "cxor", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cnot$pack $GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CNOT, "cnot", "cnot", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CSMUL, "csmul", "csmul", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSLL, "csll", "csll", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSRL, "csrl", "csrl", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSRA, "csra", "csra", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSCAN, "cscan", "cscan", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDCC, "addcc", "addcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBCC, "subcc", "subcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ANDCC, "andcc", "andcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ORCC, "orcc", "orcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_XORCC, "xorcc", "xorcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SRACC, "sracc", "sracc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+  {
+    FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+  {
+    FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CANDCC, "candcc", "candcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CORCC, "corcc", "corcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSRACC, "csracc", "csracc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDX, "addx", "addx", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBX, "subx", "subx", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_ADDI, "addi", "addi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SUBI, "subi", "subi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* andi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_ANDI, "andi", "andi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* ori$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_ORI, "ori", "ori", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* xori$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_XORI, "xori", "xori", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sdivi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* nsdivi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+  },
+/* udivi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_UDIVI, "udivi", "udivi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* nudivi$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } }
+  },
+/* smuli$pack $GRi,$s12,$GRdoublek */
+  {
+    FRV_INSN_SMULI, "smuli", "smuli", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* umuli$pack $GRi,$s12,$GRdoublek */
+  {
+    FRV_INSN_UMULI, "umuli", "umuli", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* slli$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SLLI, "slli", "slli", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* srli$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SRLI, "srli", "srli", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* srai$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SRAI, "srai", "srai", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* scani$pack $GRi,$s12,$GRk */
+  {
+    FRV_INSN_SCANI, "scani", "scani", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDICC, "addicc", "addicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBICC, "subicc", "subicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ANDICC, "andicc", "andicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ORICC, "oricc", "oricc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_XORICC, "xoricc", "xoricc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+  {
+    FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+  {
+    FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDXI, "addxi", "addxi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBXI, "subxi", "subxi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* cmpb$pack $GRi,$GRj,$ICCi_1 */
+  {
+    FRV_INSN_CMPB, "cmpb", "cmpb", 32,
+    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
+  },
+/* cmpba$pack $GRi,$GRj,$ICCi_1 */
+  {
+    FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
+    { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } }
+  },
+/* setlo$pack $ulo16,$GRklo */
+  {
+    FRV_INSN_SETLO, "setlo", "setlo", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* sethi$pack $uhi16,$GRkhi */
+  {
+    FRV_INSN_SETHI, "sethi", "sethi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* setlos$pack $slo16,$GRk */
+  {
+    FRV_INSN_SETLOS, "setlos", "setlos", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } }
+  },
+/* ldsb$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDSB, "ldsb", "ldsb", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldub$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDUB, "ldub", "ldub", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldsh$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDSH, "ldsh", "ldsh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lduh$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDUH, "lduh", "lduh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ld$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LD, "ld", "ld", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldbf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDBF, "ldbf", "ldbf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldhf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDHF, "ldhf", "ldhf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDF, "ldf", "ldf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldc$pack @($GRi,$GRj),$CPRk */
+  {
+    FRV_INSN_LDC, "ldc", "ldc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldsb$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldub$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDUB, "nldub", "nldub", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldsh$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nlduh$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nld$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLD, "nld", "nld", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldbf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldhf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDF, "nldf", "nldf", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldd$pack @($GRi,$GRj),$GRdoublek */
+  {
+    FRV_INSN_LDD, "ldd", "ldd", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lddf$pack @($GRi,$GRj),$FRdoublek */
+  {
+    FRV_INSN_LDDF, "lddf", "lddf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lddc$pack @($GRi,$GRj),$CPRdoublek */
+  {
+    FRV_INSN_LDDC, "lddc", "lddc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nldd$pack @($GRi,$GRj),$GRdoublek */
+  {
+    FRV_INSN_NLDD, "nldd", "nldd", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nlddf$pack @($GRi,$GRj),$FRdoublek */
+  {
+    FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldq$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDQ, "ldq", "ldq", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDQF, "ldqf", "ldqf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqc$pack @($GRi,$GRj),$CPRk */
+  {
+    FRV_INSN_LDQC, "ldqc", "ldqc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldq$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDQ, "nldq", "nldq", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldqf$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldsbu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldubu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldshu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lduhu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDU, "ldu", "ldu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nldsbu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldubu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldshu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nlduhu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDU, "nldu", "nldu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldbfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldhfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDFU, "ldfu", "ldfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldcu$pack @($GRi,$GRj),$CPRk */
+  {
+    FRV_INSN_LDCU, "ldcu", "ldcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldbfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldhfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* lddu$pack @($GRi,$GRj),$GRdoublek */
+  {
+    FRV_INSN_LDDU, "lddu", "lddu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nlddu$pack @($GRi,$GRj),$GRdoublek */
+  {
+    FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* lddfu$pack @($GRi,$GRj),$FRdoublek */
+  {
+    FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lddcu$pack @($GRi,$GRj),$CPRdoublek */
+  {
+    FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nlddfu$pack @($GRi,$GRj),$FRdoublek */
+  {
+    FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_LDQU, "ldqu", "ldqu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldqu$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqcu$pack @($GRi,$GRj),$CPRk */
+  {
+    FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldqfu$pack @($GRi,$GRj),$FRintk */
+  {
+    FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldsbi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldshi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDI, "ldi", "ldi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldubi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lduhi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldbfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldhfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* ldfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_LDFI, "ldfi", "ldfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nldsbi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldubi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldshi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nlduhi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDI, "nldi", "nldi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldbfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldhfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* lddi$pack @($GRi,$d12),$GRdoublek */
+  {
+    FRV_INSN_LDDI, "lddi", "lddi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* lddfi$pack @($GRi,$d12),$FRdoublek */
+  {
+    FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* nlddi$pack @($GRi,$d12),$GRdoublek */
+  {
+    FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nlddfi$pack @($GRi,$d12),$FRdoublek */
+  {
+    FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_LDQI, "ldqi", "ldqi", 32,
+    { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* ldqfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldqi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* nldqfi$pack @($GRi,$d12),$FRintk */
+  {
+    FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
+    { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* stb$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STB, "stb", "stb", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sth$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STH, "sth", "sth", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* st$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_ST, "st", "st", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stbf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STBF, "stbf", "stbf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sthf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STHF, "sthf", "sthf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STF, "stf", "stf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stc$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STC, "stc", "stc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* rstb$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTB, "rstb", "rstb", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rsth$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTH, "rsth", "rsth", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rst$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RST, "rst", "rst", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rstbf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTBF, "rstbf", "rstbf", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rsthf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTHF, "rsthf", "rsthf", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rstf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTF, "rstf", "rstf", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* std$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STD, "std", "std", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdf$pack $FRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STDF, "stdf", "stdf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdc$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STDC, "stdc", "stdc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* rstd$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTD, "rstd", "rstd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rstdf$pack $FRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTDF, "rstdf", "rstdf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stq$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQ, "stq", "stq", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stqf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQF, "stqf", "stqf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stqc$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQC, "stqc", "stqc", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rstq$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTQ, "rstq", "rstq", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* rstqf$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_RSTQF, "rstqf", "rstqf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stbu$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STBU, "stbu", "stbu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sthu$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STHU, "sthu", "sthu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stu$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STU, "stu", "stu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stbfu$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STBFU, "stbfu", "stbfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sthfu$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STHFU, "sthfu", "sthfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stfu$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STFU, "stfu", "stfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stcu$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STCU, "stcu", "stcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdu$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STDU, "stdu", "stdu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdfu$pack $FRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STDFU, "stdfu", "stdfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdcu$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STDCU, "stdcu", "stdcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stqu$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQU, "stqu", "stqu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stqfu$pack $FRintk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQFU, "stqfu", "stqfu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stqcu$pack $CPRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_STQCU, "stqcu", "stqcu", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDUB, "cldub", "cldub", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDUH, "clduh", "clduh", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLD, "cld", "cld", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDF, "cldf", "cldf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CLDD, "cldd", "cldd", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CLDDF, "clddf", "clddf", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDQ, "cldq", "cldq", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDU, "cldu", "cldu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CLDDU, "clddu", "clddu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
+  {
+    FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } }
+  },
+/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
+  },
+/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTB, "cstb", "cstb", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTH, "csth", "csth", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CST, "cst", "cst", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTHF, "csthf", "csthf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTF, "cstf", "cstf", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTD, "cstd", "cstd", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTQ, "cstq", "cstq", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTHU, "csthu", "csthu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTU, "cstu", "cstu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stbi$pack $GRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STBI, "stbi", "stbi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sthi$pack $GRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STHI, "sthi", "sthi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sti$pack $GRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STI, "sti", "sti", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stbfi$pack $FRintk,@($GRi,$d12) */
+  {
+    FRV_INSN_STBFI, "stbfi", "stbfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* sthfi$pack $FRintk,@($GRi,$d12) */
+  {
+    FRV_INSN_STHFI, "sthfi", "sthfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stfi$pack $FRintk,@($GRi,$d12) */
+  {
+    FRV_INSN_STFI, "stfi", "stfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdi$pack $GRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STDI, "stdi", "stdi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stdfi$pack $FRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STDFI, "stdfi", "stdfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } }
+  },
+/* stqi$pack $GRk,@($GRi,$d12) */
+  {
+    FRV_INSN_STQI, "stqi", "stqi", 32,
+    { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* stqfi$pack $FRintk,@($GRi,$d12) */
+  {
+    FRV_INSN_STQFI, "stqfi", "stqfi", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } }
+  },
+/* swap$pack @($GRi,$GRj),$GRk */
+  {
+    FRV_INSN_SWAP, "swap", "swap", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* swapi$pack @($GRi,$d12),$GRk */
+  {
+    FRV_INSN_SWAPI, "swapi", "swapi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
+  {
+    FRV_INSN_CSWAP, "cswap", "cswap", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* movgf$pack $GRj,$FRintk */
+  {
+    FRV_INSN_MOVGF, "movgf", "movgf", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* movfg$pack $FRintk,$GRj */
+  {
+    FRV_INSN_MOVFG, "movfg", "movfg", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* movgfd$pack $GRj,$FRintk */
+  {
+    FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* movfgd$pack $FRintk,$GRj */
+  {
+    FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* movgfq$pack $GRj,$FRintk */
+  {
+    FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
+  },
+/* movfgq$pack $FRintk,$GRj */
+  {
+    FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } }
+  },
+/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
+  {
+    FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
+  {
+    FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } }
+  },
+/* movgs$pack $GRj,$spr */
+  {
+    FRV_INSN_MOVGS, "movgs", "movgs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* movsg$pack $spr,$GRj */
+  {
+    FRV_INSN_MOVSG, "movsg", "movsg", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* bra$pack $hint_taken$label16 */
+  {
+    FRV_INSN_BRA, "bra", "bra", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bno$pack$hint_not_taken */
+  {
+    FRV_INSN_BNO, "bno", "bno", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* beq$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BEQ, "beq", "beq", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bne$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BNE, "bne", "bne", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* ble$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BLE, "ble", "ble", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bgt$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BGT, "bgt", "bgt", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* blt$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BLT, "blt", "blt", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bge$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BGE, "bge", "bge", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bls$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BLS, "bls", "bls", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bhi$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BHI, "bhi", "bhi", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bc$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BC, "bc", "bc", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bnc$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BNC, "bnc", "bnc", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bn$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BN, "bn", "bn", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bp$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BP, "bp", "bp", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bv$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BV, "bv", "bv", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bnv$pack $ICCi_2,$hint,$label16 */
+  {
+    FRV_INSN_BNV, "bnv", "bnv", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbra$pack $hint_taken$label16 */
+  {
+    FRV_INSN_FBRA, "fbra", "fbra", 32,
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbno$pack$hint_not_taken */
+  {
+    FRV_INSN_FBNO, "fbno", "fbno", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbne$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBNE, "fbne", "fbne", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbeq$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fblg$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBLG, "fblg", "fblg", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbue$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBUE, "fbue", "fbue", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbul$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBUL, "fbul", "fbul", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbge$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBGE, "fbge", "fbge", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fblt$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBLT, "fblt", "fblt", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbuge$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbug$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBUG, "fbug", "fbug", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fble$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBLE, "fble", "fble", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbgt$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBGT, "fbgt", "fbgt", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbule$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBULE, "fbule", "fbule", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbu$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBU, "fbu", "fbu", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* fbo$pack $FCCi_2,$hint,$label16 */
+  {
+    FRV_INSN_FBO, "fbo", "fbo", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } }
+  },
+/* bctrlr$pack $ccond,$hint */
+  {
+    FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bralr$pack$hint_taken */
+  {
+    FRV_INSN_BRALR, "bralr", "bralr", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bnolr$pack$hint_not_taken */
+  {
+    FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* beqlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bnelr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BNELR, "bnelr", "bnelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* blelr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BLELR, "blelr", "blelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bgtlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bltlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bgelr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BGELR, "bgelr", "bgelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* blslr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BLSLR, "blslr", "blslr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bhilr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BHILR, "bhilr", "bhilr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bclr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BCLR, "bclr", "bclr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bnclr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bnlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BNLR, "bnlr", "bnlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bplr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BPLR, "bplr", "bplr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bvlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BVLR, "bvlr", "bvlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bnvlr$pack $ICCi_2,$hint */
+  {
+    FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbralr$pack$hint_taken */
+  {
+    FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
+    { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbnolr$pack$hint_not_taken */
+  {
+    FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbeqlr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbnelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fblglr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbuelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbullr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbgelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbltlr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbugelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbuglr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fblelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbgtlr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbulelr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbulr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBULR, "fbulr", "fbulr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* fbolr$pack $FCCi_2,$hint */
+  {
+    FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } }
+  },
+/* bcralr$pack $ccond$hint_taken */
+  {
+    FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcnolr$pack$hint_not_taken */
+  {
+    FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bceqlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcnelr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bclelr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcgtlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcltlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcgelr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bclslr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bchilr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcclr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcnclr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcnlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcplr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcvlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* bcnvlr$pack $ICCi_2,$ccond,$hint */
+  {
+    FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
+    { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbralr$pack $ccond$hint_taken */
+  {
+    FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbnolr$pack$hint_not_taken */
+  {
+    FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbeqlr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbnelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcblglr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbuelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbullr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbgelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbltlr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbugelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbuglr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcblelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbgtlr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbulelr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbulr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* fcbolr$pack $FCCi_2,$ccond,$hint */
+  {
+    FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
+    { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } }
+  },
+/* jmpl$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_JMPL, "jmpl", "jmpl", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* calll$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_CALLL, "calll", "calll", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* jmpil$pack @($GRi,$s12) */
+  {
+    FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* callil$pack @($GRi,$s12) */
+  {
+    FRV_INSN_CALLIL, "callil", "callil", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* call$pack $label24 */
+  {
+    FRV_INSN_CALL, "call", "call", 32,
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } }
+  },
+/* rett$pack $debug */
+  {
+    FRV_INSN_RETT, "rett", "rett", 32,
+    { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* rei$pack $eir */
+  {
+    FRV_INSN_REI, "rei", "rei", 32,
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } }
+  },
+/* tra$pack $GRi,$GRj */
+  {
+    FRV_INSN_TRA, "tra", "tra", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tno$pack */
+  {
+    FRV_INSN_TNO, "tno", "tno", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* teq$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TEQ, "teq", "teq", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tne$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TNE, "tne", "tne", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tle$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TLE, "tle", "tle", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tgt$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TGT, "tgt", "tgt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tlt$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TLT, "tlt", "tlt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tge$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TGE, "tge", "tge", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tls$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TLS, "tls", "tls", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* thi$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_THI, "thi", "thi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tc$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TC, "tc", "tc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tnc$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TNC, "tnc", "tnc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tn$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TN, "tn", "tn", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tp$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TP, "tp", "tp", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tv$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TV, "tv", "tv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tnv$pack $ICCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_TNV, "tnv", "tnv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftra$pack $GRi,$GRj */
+  {
+    FRV_INSN_FTRA, "ftra", "ftra", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftno$pack */
+  {
+    FRV_INSN_FTNO, "ftno", "ftno", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftne$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTNE, "ftne", "ftne", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* fteq$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTEQ, "fteq", "fteq", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftlg$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTLG, "ftlg", "ftlg", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftue$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTUE, "ftue", "ftue", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftul$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTUL, "ftul", "ftul", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftge$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTGE, "ftge", "ftge", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftlt$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTLT, "ftlt", "ftlt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftuge$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftug$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTUG, "ftug", "ftug", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftle$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTLE, "ftle", "ftle", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftgt$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTGT, "ftgt", "ftgt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftule$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTULE, "ftule", "ftule", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftu$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTU, "ftu", "ftu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* fto$pack $FCCi_2,$GRi,$GRj */
+  {
+    FRV_INSN_FTO, "fto", "fto", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tira$pack $GRi,$s12 */
+  {
+    FRV_INSN_TIRA, "tira", "tira", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tino$pack */
+  {
+    FRV_INSN_TINO, "tino", "tino", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tieq$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIEQ, "tieq", "tieq", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tine$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TINE, "tine", "tine", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tile$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TILE, "tile", "tile", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tigt$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIGT, "tigt", "tigt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tilt$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TILT, "tilt", "tilt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tige$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIGE, "tige", "tige", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tils$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TILS, "tils", "tils", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tihi$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIHI, "tihi", "tihi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tic$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIC, "tic", "tic", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tinc$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TINC, "tinc", "tinc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tin$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIN, "tin", "tin", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tip$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIP, "tip", "tip", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tiv$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TIV, "tiv", "tiv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* tinv$pack $ICCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_TINV, "tinv", "tinv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftira$pack $GRi,$s12 */
+  {
+    FRV_INSN_FTIRA, "ftira", "ftira", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftino$pack */
+  {
+    FRV_INSN_FTINO, "ftino", "ftino", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftine$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTINE, "ftine", "ftine", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftieq$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftilg$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTILG, "ftilg", "ftilg", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiue$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiul$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftige$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIGE, "ftige", "ftige", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftilt$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTILT, "ftilt", "ftilt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiuge$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiug$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftile$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTILE, "ftile", "ftile", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftigt$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiule$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftiu$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIU, "ftiu", "ftiu", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* ftio$pack $FCCi_2,$GRi,$s12 */
+  {
+    FRV_INSN_FTIO, "ftio", "ftio", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* break$pack */
+  {
+    FRV_INSN_BREAK, "break", "break", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* mtrap$pack */
+  {
+    FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } }
+  },
+/* andcr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_ANDCR, "andcr", "andcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* orcr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_ORCR, "orcr", "orcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* xorcr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_XORCR, "xorcr", "xorcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* nandcr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* norcr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_NORCR, "norcr", "norcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* andncr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_ANDNCR, "andncr", "andncr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* orncr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_ORNCR, "orncr", "orncr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* nandncr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* norncr$pack $CRi,$CRj,$CRk */
+  {
+    FRV_INSN_NORNCR, "norncr", "norncr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* notcr$pack $CRj,$CRk */
+  {
+    FRV_INSN_NOTCR, "notcr", "notcr", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } }
+  },
+/* ckra$pack $CRj_int */
+  {
+    FRV_INSN_CKRA, "ckra", "ckra", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckno$pack $CRj_int */
+  {
+    FRV_INSN_CKNO, "ckno", "ckno", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckeq$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckne$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKNE, "ckne", "ckne", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckle$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKLE, "ckle", "ckle", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckgt$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKGT, "ckgt", "ckgt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cklt$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKLT, "cklt", "cklt", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckge$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKGE, "ckge", "ckge", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckls$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKLS, "ckls", "ckls", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckhi$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKHI, "ckhi", "ckhi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckc$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKC, "ckc", "ckc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cknc$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKNC, "cknc", "cknc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckn$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKN, "ckn", "ckn", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckp$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKP, "ckp", "ckp", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ckv$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKV, "ckv", "ckv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cknv$pack $ICCi_3,$CRj_int */
+  {
+    FRV_INSN_CKNV, "cknv", "cknv", 32,
+    { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckra$pack $CRj_float */
+  {
+    FRV_INSN_FCKRA, "fckra", "fckra", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckno$pack $CRj_float */
+  {
+    FRV_INSN_FCKNO, "fckno", "fckno", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckne$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKNE, "fckne", "fckne", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckeq$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fcklg$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckue$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKUE, "fckue", "fckue", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckul$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKUL, "fckul", "fckul", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckge$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKGE, "fckge", "fckge", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fcklt$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckuge$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckug$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKUG, "fckug", "fckug", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckle$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKLE, "fckle", "fckle", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckgt$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fckule$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKULE, "fckule", "fckule", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fcku$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKU, "fcku", "fcku", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* fcko$pack $FCCi_3,$CRj_float */
+  {
+    FRV_INSN_FCKO, "fcko", "fcko", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckra$pack $CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKRA, "cckra", "cckra", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckno$pack $CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKNO, "cckno", "cckno", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKNE, "cckne", "cckne", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKLE, "cckle", "cckle", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKGE, "cckge", "cckge", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKLS, "cckls", "cckls", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKC, "cckc", "cckc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKN, "cckn", "cckn", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKP, "cckp", "cckp", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKV, "cckv", "cckv", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
+  {
+    FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckra$pack $CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckno$pack $CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
+  {
+    FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } }
+  },
+/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* ccalll$pack @($GRi,$GRj),$CCi,$cond */
+  {
+    FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
+    { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } }
+  },
+/* ici$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_ICI, "ici", "ici", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* dci$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_DCI, "dci", "dci", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* icei$pack @($GRi,$GRj),$ae */
+  {
+    FRV_INSN_ICEI, "icei", "icei", 32,
+    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+  },
+/* dcei$pack @($GRi,$GRj),$ae */
+  {
+    FRV_INSN_DCEI, "dcei", "dcei", 32,
+    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+  },
+/* dcf$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_DCF, "dcf", "dcf", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* dcef$pack @($GRi,$GRj),$ae */
+  {
+    FRV_INSN_DCEF, "dcef", "dcef", 32,
+    { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } }
+  },
+/* witlb$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_WITLB, "witlb", "witlb", 32,
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* wdtlb$pack $GRk,@($GRi,$GRj) */
+  {
+    FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* itlbi$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* dtlbi$pack @($GRi,$GRj) */
+  {
+    FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
+    { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* icpl$pack $GRi,$GRj,$lock */
+  {
+    FRV_INSN_ICPL, "icpl", "icpl", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* dcpl$pack $GRi,$GRj,$lock */
+  {
+    FRV_INSN_DCPL, "dcpl", "dcpl", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* icul$pack $GRi */
+  {
+    FRV_INSN_ICUL, "icul", "icul", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* dcul$pack $GRi */
+  {
+    FRV_INSN_DCUL, "dcul", "dcul", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* bar$pack */
+  {
+    FRV_INSN_BAR, "bar", "bar", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* membar$pack */
+  {
+    FRV_INSN_MEMBAR, "membar", "membar", 32,
+    { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } }
+  },
+/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
+  {
+    FRV_INSN_COP1, "cop1", "cop1", 32,
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
+  {
+    FRV_INSN_COP2, "cop2", "cop2", 32,
+    { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } }
+  },
+/* clrgr$pack $GRk */
+  {
+    FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* clrfr$pack $FRk */
+  {
+    FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* clrga$pack */
+  {
+    FRV_INSN_CLRGA, "clrga", "clrga", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* clrfa$pack */
+  {
+    FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* commitgr$pack $GRk */
+  {
+    FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* commitfr$pack $FRk */
+  {
+    FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* commitga$pack */
+  {
+    FRV_INSN_COMMITGA, "commitga", "commitga", 32,
+    { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* commitfa$pack */
+  {
+    FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
+    { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } }
+  },
+/* fitos$pack $FRintj,$FRk */
+  {
+    FRV_INSN_FITOS, "fitos", "fitos", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fstoi$pack $FRj,$FRintk */
+  {
+    FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fitod$pack $FRintj,$FRdoublek */
+  {
+    FRV_INSN_FITOD, "fitod", "fitod", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fdtoi$pack $FRdoublej,$FRintk */
+  {
+    FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fditos$pack $FRintj,$FRk */
+  {
+    FRV_INSN_FDITOS, "fditos", "fditos", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fdstoi$pack $FRj,$FRintk */
+  {
+    FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* nfditos$pack $FRintj,$FRk */
+  {
+    FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* nfdstoi$pack $FRj,$FRintk */
+  {
+    FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* cfitos$pack $FRintj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* nfitos$pack $FRintj,$FRk */
+  {
+    FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* nfstoi$pack $FRj,$FRintk */
+  {
+    FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fmovs$pack $FRj,$FRk */
+  {
+    FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fmovd$pack $FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fdmovs$pack $FRj,$FRk */
+  {
+    FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* cfmovs$pack $FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
+    { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fnegs$pack $FRj,$FRk */
+  {
+    FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fnegd$pack $FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fdnegs$pack $FRj,$FRk */
+  {
+    FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* cfnegs$pack $FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fabss$pack $FRj,$FRk */
+  {
+    FRV_INSN_FABSS, "fabss", "fabss", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fabsd$pack $FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FABSD, "fabsd", "fabsd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fdabss$pack $FRj,$FRk */
+  {
+    FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* cfabss$pack $FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } }
+  },
+/* fsqrts$pack $FRj,$FRk */
+  {
+    FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* fdsqrts$pack $FRj,$FRk */
+  {
+    FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* nfdsqrts$pack $FRj,$FRk */
+  {
+    FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* fsqrtd$pack $FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* nfsqrts$pack $FRj,$FRk */
+  {
+    FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* fadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FADDS, "fadds", "fadds", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fmuls$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMULS, "fmuls", "fmuls", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+  },
+/* fdivs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FADDD, "faddd", "faddd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FMULD, "fmuld", "fmuld", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+  },
+/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+  },
+/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* nfadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* nfsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* nfmuls$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } }
+  },
+/* nfdivs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } }
+  },
+/* fcmps$pack $FRi,$FRj,$FCCi_2 */
+  {
+    FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
+  {
+    FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
+  {
+    FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } }
+  },
+/* fdcmps$pack $FRi,$FRj,$FCCi_2 */
+  {
+    FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* fmadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
+  {
+    FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fdmadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfdmadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfmadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfmsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
+    { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmas$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMAS, "fmas", "fmas", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmss$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMSS, "fmss", "fmss", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fdmas$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fdmss$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfdmas$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfdmss$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
+  {
+    FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmad$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMAD, "fmad", "fmad", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fmsd$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FMSD, "fmsd", "fmsd", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfmas$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* nfmss$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } }
+  },
+/* fdadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* fdsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* fdmuls$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* fddivs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* fdsads$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* fdmulcs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* nfdmulcs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* nfdadds$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* nfdsubs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* nfdmuls$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* nfddivs$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } }
+  },
+/* nfdsads$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
+  {
+    FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } }
+  },
+/* mhsetlos$pack $u12,$FRklo */
+  {
+    FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mhsethis$pack $u12,$FRkhi */
+  {
+    FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mhdsets$pack $u12,$FRintk */
+  {
+    FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mhsetloh$pack $s5,$FRklo */
+  {
+    FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mhsethih$pack $s5,$FRkhi */
+  {
+    FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mhdseth$pack $s5,$FRintk */
+  {
+    FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mand$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MAND, "mand", "mand", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mor$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MOR, "mor", "mor", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mxor$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MXOR, "mxor", "mxor", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMAND, "cmand", "cmand", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMOR, "cmor", "cmor", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mnot$pack $FRintj,$FRintk */
+  {
+    FRV_INSN_MNOT, "mnot", "mnot", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mrotli$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mrotri$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mwcut$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mwcuti$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mcut$pack $ACC40Si,$FRintj,$FRintk */
+  {
+    FRV_INSN_MCUT, "mcut", "mcut", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mcuti$pack $ACC40Si,$s6,$FRintk */
+  {
+    FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mcutss$pack $ACC40Si,$FRintj,$FRintk */
+  {
+    FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mcutssi$pack $ACC40Si,$s6,$FRintk */
+  {
+    FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mdcutssi$pack $ACC40Si,$s6,$FRintk */
+  {
+    FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* maveh$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MAVEH, "maveh", "maveh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* msllhi$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* msrlhi$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* msrahi$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mdrotli$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mcplhi$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mcpli$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* msaths$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MSATHS, "msaths", "msaths", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mqsaths$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* msathu$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MSATHU, "msathu", "msathu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mcmpsh$pack $FRinti,$FRintj,$FCCk */
+  {
+    FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mcmpuh$pack $FRinti,$FRintj,$FCCk */
+  {
+    FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mabshs$pack $FRintj,$FRintk */
+  {
+    FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* maddhss$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* maddhus$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* msubhss$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* msubhus$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } }
+  },
+/* mqaddhss$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* mqaddhus$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* mqsubhss$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* mqsubhus$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } }
+  },
+/* maddaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* msubaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mdaddaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mdsubaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* masaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } }
+  },
+/* mdasaccs$pack $ACC40Si,$ACC40Sk */
+  {
+    FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
+    { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
+    { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
+  {
+    FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
+  {
+    FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
+  {
+    FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */
+  {
+    FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
+  {
+    FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
+    { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } }
+  },
+/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
+  {
+    FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } }
+  },
+/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
+  {
+    FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } }
+  },
+/* mexpdhw$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mexpdhd$pack $FRinti,$u6,$FRintk */
+  {
+    FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mpackh$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mdpackh$pack $FRinti,$FRintj,$FRintk */
+  {
+    FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } }
+  },
+/* munpackh$pack $FRinti,$FRintk */
+  {
+    FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mdunpackh$pack $FRinti,$FRintk */
+  {
+    FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+  },
+/* mbtoh$pack $FRintj,$FRintk */
+  {
+    FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mhtob$pack $FRintj,$FRintk */
+  {
+    FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } }
+  },
+/* mbtohe$pack $FRintj,$FRintk */
+  {
+    FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+  },
+/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
+  {
+    FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
+    { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } }
+  },
+/* mclracc$pack $ACC40Sk,$A */
+  {
+    FRV_INSN_MCLRACC, "mclracc", "mclracc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } }
+  },
+/* mrdacc$pack $ACC40Si,$FRintk */
+  {
+    FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mrdaccg$pack $ACCGi,$FRintk */
+  {
+    FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } }
+  },
+/* mwtacc$pack $FRinti,$ACC40Sk */
+  {
+    FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
+  },
+/* mwtaccg$pack $FRinti,$ACCGk */
+  {
+    FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
+    { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } }
+  },
+/* mcop1$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
+  },
+/* mcop2$pack $FRi,$FRj,$FRk */
+  {
+    FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
+    { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } }
+  },
+/* fnop$pack */
+  {
+    FRV_INSN_FNOP, "fnop", "fnop", 32,
+    { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } }
+  },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call.  */
+static void init_tables PARAMS ((void));
+
+static void
+init_tables ()
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name
+  PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
+static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
+/* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name.  */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+     const CGEN_MACH *table;
+     const char *name;
+{
+  while (table->name)
+    {
+      if (strcmp (name, table->bfd_name) == 0)
+	return table;
+      ++table;
+    }
+  abort ();
+}
+
+/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_hw_table (cd)
+     CGEN_CPU_TABLE *cd;
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0];
+  /* MAX_HW is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_HW_ENTRY **selected =
+    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+  cd->hw_table.init_entries = init;
+  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+  /* ??? For now we just use machs to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->hw_table.entries = selected;
+  cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_ifield_table (cd)
+     CGEN_CPU_TABLE *cd;
+{
+  cd->ifld_table = & frv_cgen_ifld_table[0];
+}
+
+/* Subroutine of frv_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_operand_table (cd)
+     CGEN_CPU_TABLE *cd;
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_OPERAND *init = & frv_cgen_operand_table[0];
+  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_OPERAND **selected =
+    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+  cd->operand_table.init_entries = init;
+  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  /* ??? For now we just use mach to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->operand_table.entries = selected;
+  cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of frv_cgen_cpu_open to build the hardware table.
+   ??? This could leave out insns not supported by the specified mach/isa,
+   but that would cause errors like "foo only supported by bar" to become
+   "unknown insn", so for now we include all insns and require the app to
+   do the checking later.
+   ??? On the other hand, parsing of such insns may require their hardware or
+   operand elements to be in the table [which they mightn't be].  */
+
+static void
+build_insn_table (cd)
+     CGEN_CPU_TABLE *cd;
+{
+  int i;
+  const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
+  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+  for (i = 0; i < MAX_INSNS; ++i)
+    insns[i].base = &ib[i];
+  cd->insn_table.init_entries = insns;
+  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of frv_cgen_cpu_open to rebuild the tables.  */
+
+static void
+frv_cgen_rebuild_tables (cd)
+     CGEN_CPU_TABLE *cd;
+{
+  int i;
+  unsigned int isas = cd->isas;
+  unsigned int machs = cd->machs;
+
+  cd->int_insn_p = CGEN_INT_INSN_P;
+
+  /* Data derived from the isa spec.  */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+  cd->default_insn_bitsize = UNSET;
+  cd->base_insn_bitsize = UNSET;
+  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+  cd->max_insn_bitsize = 0;
+  for (i = 0; i < MAX_ISAS; ++i)
+    if (((1 << i) & isas) != 0)
+      {
+	const CGEN_ISA *isa = & frv_cgen_isa_table[i];
+
+	/* Default insn sizes of all selected isas must be
+	   equal or we set the result to 0, meaning "unknown".  */
+	if (cd->default_insn_bitsize == UNSET)
+	  cd->default_insn_bitsize = isa->default_insn_bitsize;
+	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+	  ; /* this is ok */
+	else
+	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Base insn sizes of all selected isas must be equal
+	   or we set the result to 0, meaning "unknown".  */
+	if (cd->base_insn_bitsize == UNSET)
+	  cd->base_insn_bitsize = isa->base_insn_bitsize;
+	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+	  ; /* this is ok */
+	else
+	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Set min,max insn sizes.  */
+	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+	  cd->min_insn_bitsize = isa->min_insn_bitsize;
+	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+	  cd->max_insn_bitsize = isa->max_insn_bitsize;
+      }
+
+  /* Data derived from the mach spec.  */
+  for (i = 0; i < MAX_MACHS; ++i)
+    if (((1 << i) & machs) != 0)
+      {
+	const CGEN_MACH *mach = & frv_cgen_mach_table[i];
+
+	if (mach->insn_chunk_bitsize != 0)
+	{
+	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+	    {
+	      fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      abort ();
+	    }
+
+ 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+	}
+      }
+
+  /* Determine which hw elements are used by MACH.  */
+  build_hw_table (cd);
+
+  /* Build the ifield table.  */
+  build_ifield_table (cd);
+
+  /* Determine which operands are used by MACH/ISA.  */
+  build_operand_table (cd);
+
+  /* Build the instruction table.  */
+  build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+   It's much like opening a file, and must be the first function called.
+   The arguments are a set of (type/value) pairs, terminated with
+   CGEN_CPU_OPEN_END.
+
+   Currently supported values:
+   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
+   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
+   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
+   CGEN_CPU_OPEN_END:     terminates arguments
+
+   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+   precluded.
+
+   ??? We only support ISO C stdargs here, not K&R.
+   Laziness, plus experiment to see if anything requires K&R - eventually
+   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+
+CGEN_CPU_DESC
+frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+  static int init_p;
+  unsigned int isas = 0;  /* 0 = "unspecified" */
+  unsigned int machs = 0; /* 0 = "unspecified" */
+  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+  va_list ap;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (cd, 0, sizeof (*cd));
+
+  va_start (ap, arg_type);
+  while (arg_type != CGEN_CPU_OPEN_END)
+    {
+      switch (arg_type)
+	{
+	case CGEN_CPU_OPEN_ISAS :
+	  isas = va_arg (ap, unsigned int);
+	  break;
+	case CGEN_CPU_OPEN_MACHS :
+	  machs = va_arg (ap, unsigned int);
+	  break;
+	case CGEN_CPU_OPEN_BFDMACH :
+	  {
+	    const char *name = va_arg (ap, const char *);
+	    const CGEN_MACH *mach =
+	      lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
+
+	    machs |= 1 << mach->num;
+	    break;
+	  }
+	case CGEN_CPU_OPEN_ENDIAN :
+	  endian = va_arg (ap, enum cgen_endian);
+	  break;
+	default :
+	  fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
+		   arg_type);
+	  abort (); /* ??? return NULL? */
+	}
+      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+    }
+  va_end (ap);
+
+  /* mach unspecified means "all" */
+  if (machs == 0)
+    machs = (1 << MAX_MACHS) - 1;
+  /* base mach is always selected */
+  machs |= 1;
+  /* isa unspecified means "all" */
+  if (isas == 0)
+    isas = (1 << MAX_ISAS) - 1;
+  if (endian == CGEN_ENDIAN_UNKNOWN)
+    {
+      /* ??? If target has only one, could have a default.  */
+      fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
+      abort ();
+    }
+
+  cd->isas = isas;
+  cd->machs = machs;
+  cd->endian = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  cd->insn_endian = endian;
+
+  /* Table (re)builder.  */
+  cd->rebuild_tables = frv_cgen_rebuild_tables;
+  frv_cgen_rebuild_tables (cd);
+
+  /* Default to not allowing signed overflow.  */
+  cd->signed_overflow_ok_p = 0;
+  
+  return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+   MACH_NAME is the bfd name of the mach.  */
+
+CGEN_CPU_DESC
+frv_cgen_cpu_open_1 (mach_name, endian)
+     const char *mach_name;
+     enum cgen_endian endian;
+{
+  return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+			       CGEN_CPU_OPEN_ENDIAN, endian,
+			       CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+   ??? This can live in a machine independent file, but there's currently
+   no place to put this file (there's no libcgen).  libopcodes is the wrong
+   place as some simulator ports use this but they don't use libopcodes.  */
+
+void
+frv_cgen_cpu_close (cd)
+     CGEN_CPU_DESC cd;
+{
+  unsigned int i;
+  CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+	{
+	  if (CGEN_INSN_RX ((insns)))
+	    regfree(CGEN_INSN_RX (insns));
+	}
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+	{
+	  if (CGEN_INSN_RX (insns))
+	    regfree(CGEN_INSN_RX (insns));
+	}
+    }
+
+  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+  if (cd->insn_table.init_entries)
+    free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+  if (cd->hw_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+  free (cd);
+}
+

--- /dev/null
+++ b/opcodes/frv-desc.h
@@ -0,0 +1,748 @@
+/* CPU data header for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FRV_CPU_H
+#define FRV_CPU_H
+
+#define CGEN_ARCH frv
+
+/* Given symbol S, return frv_cgen_<S>.  */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) frv##_cgen_##s
+#else
+#define CGEN_SYM(s) frv/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families.  */
+#define HAVE_CPU_FRVBF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes).  */
+#define CGEN_MIN_INSN_SIZE 4
+
+/* Maximum size of any insn (in bytes).  */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction.  */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
+
+/* Enums.  */
+
+/* Enum declaration for insn op enums.  */
+typedef enum insn_op {
+  OP_00, OP_01, OP_02, OP_03
+ , OP_04, OP_05, OP_06, OP_07
+ , OP_08, OP_09, OP_0A, OP_0B
+ , OP_0C, OP_0D, OP_0E, OP_0F
+ , OP_10, OP_11, OP_12, OP_13
+ , OP_14, OP_15, OP_16, OP_17
+ , OP_18, OP_19, OP_1A, OP_1B
+ , OP_1C, OP_1D, OP_1E, OP_1F
+ , OP_20, OP_21, OP_22, OP_23
+ , OP_24, OP_25, OP_26, OP_27
+ , OP_28, OP_29, OP_2A, OP_2B
+ , OP_2C, OP_2D, OP_2E, OP_2F
+ , OP_30, OP_31, OP_32, OP_33
+ , OP_34, OP_35, OP_36, OP_37
+ , OP_38, OP_39, OP_3A, OP_3B
+ , OP_3C, OP_3D, OP_3E, OP_3F
+ , OP_40, OP_41, OP_42, OP_43
+ , OP_44, OP_45, OP_46, OP_47
+ , OP_48, OP_49, OP_4A, OP_4B
+ , OP_4C, OP_4D, OP_4E, OP_4F
+ , OP_50, OP_51, OP_52, OP_53
+ , OP_54, OP_55, OP_56, OP_57
+ , OP_58, OP_59, OP_5A, OP_5B
+ , OP_5C, OP_5D, OP_5E, OP_5F
+ , OP_60, OP_61, OP_62, OP_63
+ , OP_64, OP_65, OP_66, OP_67
+ , OP_68, OP_69, OP_6A, OP_6B
+ , OP_6C, OP_6D, OP_6E, OP_6F
+ , OP_70, OP_71, OP_72, OP_73
+ , OP_74, OP_75, OP_76, OP_77
+ , OP_78, OP_79, OP_7A, OP_7B
+ , OP_7C, OP_7D, OP_7E, OP_7F
+} INSN_OP;
+
+/* Enum declaration for insn ope enums.  */
+typedef enum insn_ope1 {
+  OPE1_00, OPE1_01, OPE1_02, OPE1_03
+ , OPE1_04, OPE1_05, OPE1_06, OPE1_07
+ , OPE1_08, OPE1_09, OPE1_0A, OPE1_0B
+ , OPE1_0C, OPE1_0D, OPE1_0E, OPE1_0F
+ , OPE1_10, OPE1_11, OPE1_12, OPE1_13
+ , OPE1_14, OPE1_15, OPE1_16, OPE1_17
+ , OPE1_18, OPE1_19, OPE1_1A, OPE1_1B
+ , OPE1_1C, OPE1_1D, OPE1_1E, OPE1_1F
+ , OPE1_20, OPE1_21, OPE1_22, OPE1_23
+ , OPE1_24, OPE1_25, OPE1_26, OPE1_27
+ , OPE1_28, OPE1_29, OPE1_2A, OPE1_2B
+ , OPE1_2C, OPE1_2D, OPE1_2E, OPE1_2F
+ , OPE1_30, OPE1_31, OPE1_32, OPE1_33
+ , OPE1_34, OPE1_35, OPE1_36, OPE1_37
+ , OPE1_38, OPE1_39, OPE1_3A, OPE1_3B
+ , OPE1_3C, OPE1_3D, OPE1_3E, OPE1_3F
+} INSN_OPE1;
+
+/* Enum declaration for insn ope enums.  */
+typedef enum insn_ope2 {
+  OPE2_00, OPE2_01, OPE2_02, OPE2_03
+ , OPE2_04, OPE2_05, OPE2_06, OPE2_07
+ , OPE2_08, OPE2_09, OPE2_0A, OPE2_0B
+ , OPE2_0C, OPE2_0D, OPE2_0E, OPE2_0F
+} INSN_OPE2;
+
+/* Enum declaration for insn ope enums.  */
+typedef enum insn_ope3 {
+  OPE3_00, OPE3_01, OPE3_02, OPE3_03
+ , OPE3_04, OPE3_05, OPE3_06, OPE3_07
+} INSN_OPE3;
+
+/* Enum declaration for insn ope enums.  */
+typedef enum insn_ope4 {
+  OPE4_0, OPE4_1, OPE4_2, OPE4_3
+} INSN_OPE4;
+
+/* Enum declaration for integer branch cond enums.  */
+typedef enum int_cc {
+  ICC_NEV, ICC_C, ICC_V, ICC_LT
+ , ICC_EQ, ICC_LS, ICC_N, ICC_LE
+ , ICC_RA, ICC_NC, ICC_NV, ICC_GE
+ , ICC_NE, ICC_HI, ICC_P, ICC_GT
+} INT_CC;
+
+/* Enum declaration for float branch cond enums.  */
+typedef enum flt_cc {
+  FCC_NEV, FCC_U, FCC_GT, FCC_UG
+ , FCC_LT, FCC_UL, FCC_LG, FCC_NE
+ , FCC_EQ, FCC_UE, FCC_GE, FCC_UGE
+ , FCC_LE, FCC_ULE, FCC_O, FCC_RA
+} FLT_CC;
+
+/* Enum declaration for .  */
+typedef enum gr_names {
+  H_GR_SP = 1, H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1
+ , H_GR_GR2 = 2, H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5
+ , H_GR_GR6 = 6, H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9
+ , H_GR_GR10 = 10, H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13
+ , H_GR_GR14 = 14, H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17
+ , H_GR_GR18 = 18, H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21
+ , H_GR_GR22 = 22, H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25
+ , H_GR_GR26 = 26, H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29
+ , H_GR_GR30 = 30, H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33
+ , H_GR_GR34 = 34, H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37
+ , H_GR_GR38 = 38, H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41
+ , H_GR_GR42 = 42, H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45
+ , H_GR_GR46 = 46, H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49
+ , H_GR_GR50 = 50, H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53
+ , H_GR_GR54 = 54, H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57
+ , H_GR_GR58 = 58, H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61
+ , H_GR_GR62 = 62, H_GR_GR63 = 63
+} GR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum fr_names {
+  H_FR_FR0, H_FR_FR1, H_FR_FR2, H_FR_FR3
+ , H_FR_FR4, H_FR_FR5, H_FR_FR6, H_FR_FR7
+ , H_FR_FR8, H_FR_FR9, H_FR_FR10, H_FR_FR11
+ , H_FR_FR12, H_FR_FR13, H_FR_FR14, H_FR_FR15
+ , H_FR_FR16, H_FR_FR17, H_FR_FR18, H_FR_FR19
+ , H_FR_FR20, H_FR_FR21, H_FR_FR22, H_FR_FR23
+ , H_FR_FR24, H_FR_FR25, H_FR_FR26, H_FR_FR27
+ , H_FR_FR28, H_FR_FR29, H_FR_FR30, H_FR_FR31
+ , H_FR_FR32, H_FR_FR33, H_FR_FR34, H_FR_FR35
+ , H_FR_FR36, H_FR_FR37, H_FR_FR38, H_FR_FR39
+ , H_FR_FR40, H_FR_FR41, H_FR_FR42, H_FR_FR43
+ , H_FR_FR44, H_FR_FR45, H_FR_FR46, H_FR_FR47
+ , H_FR_FR48, H_FR_FR49, H_FR_FR50, H_FR_FR51
+ , H_FR_FR52, H_FR_FR53, H_FR_FR54, H_FR_FR55
+ , H_FR_FR56, H_FR_FR57, H_FR_FR58, H_FR_FR59
+ , H_FR_FR60, H_FR_FR61, H_FR_FR62, H_FR_FR63
+} FR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum cpr_names {
+  H_CPR_CPR0, H_CPR_CPR1, H_CPR_CPR2, H_CPR_CPR3
+ , H_CPR_CPR4, H_CPR_CPR5, H_CPR_CPR6, H_CPR_CPR7
+ , H_CPR_CPR8, H_CPR_CPR9, H_CPR_CPR10, H_CPR_CPR11
+ , H_CPR_CPR12, H_CPR_CPR13, H_CPR_CPR14, H_CPR_CPR15
+ , H_CPR_CPR16, H_CPR_CPR17, H_CPR_CPR18, H_CPR_CPR19
+ , H_CPR_CPR20, H_CPR_CPR21, H_CPR_CPR22, H_CPR_CPR23
+ , H_CPR_CPR24, H_CPR_CPR25, H_CPR_CPR26, H_CPR_CPR27
+ , H_CPR_CPR28, H_CPR_CPR29, H_CPR_CPR30, H_CPR_CPR31
+ , H_CPR_CPR32, H_CPR_CPR33, H_CPR_CPR34, H_CPR_CPR35
+ , H_CPR_CPR36, H_CPR_CPR37, H_CPR_CPR38, H_CPR_CPR39
+ , H_CPR_CPR40, H_CPR_CPR41, H_CPR_CPR42, H_CPR_CPR43
+ , H_CPR_CPR44, H_CPR_CPR45, H_CPR_CPR46, H_CPR_CPR47
+ , H_CPR_CPR48, H_CPR_CPR49, H_CPR_CPR50, H_CPR_CPR51
+ , H_CPR_CPR52, H_CPR_CPR53, H_CPR_CPR54, H_CPR_CPR55
+ , H_CPR_CPR56, H_CPR_CPR57, H_CPR_CPR58, H_CPR_CPR59
+ , H_CPR_CPR60, H_CPR_CPR61, H_CPR_CPR62, H_CPR_CPR63
+} CPR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum spr_names {
+  H_SPR_PSR = 0, H_SPR_PCSR = 1, H_SPR_BPCSR = 2, H_SPR_TBR = 3
+ , H_SPR_BPSR = 4, H_SPR_HSR0 = 16, H_SPR_HSR1 = 17, H_SPR_HSR2 = 18
+ , H_SPR_HSR3 = 19, H_SPR_HSR4 = 20, H_SPR_HSR5 = 21, H_SPR_HSR6 = 22
+ , H_SPR_HSR7 = 23, H_SPR_HSR8 = 24, H_SPR_HSR9 = 25, H_SPR_HSR10 = 26
+ , H_SPR_HSR11 = 27, H_SPR_HSR12 = 28, H_SPR_HSR13 = 29, H_SPR_HSR14 = 30
+ , H_SPR_HSR15 = 31, H_SPR_HSR16 = 32, H_SPR_HSR17 = 33, H_SPR_HSR18 = 34
+ , H_SPR_HSR19 = 35, H_SPR_HSR20 = 36, H_SPR_HSR21 = 37, H_SPR_HSR22 = 38
+ , H_SPR_HSR23 = 39, H_SPR_HSR24 = 40, H_SPR_HSR25 = 41, H_SPR_HSR26 = 42
+ , H_SPR_HSR27 = 43, H_SPR_HSR28 = 44, H_SPR_HSR29 = 45, H_SPR_HSR30 = 46
+ , H_SPR_HSR31 = 47, H_SPR_HSR32 = 48, H_SPR_HSR33 = 49, H_SPR_HSR34 = 50
+ , H_SPR_HSR35 = 51, H_SPR_HSR36 = 52, H_SPR_HSR37 = 53, H_SPR_HSR38 = 54
+ , H_SPR_HSR39 = 55, H_SPR_HSR40 = 56, H_SPR_HSR41 = 57, H_SPR_HSR42 = 58
+ , H_SPR_HSR43 = 59, H_SPR_HSR44 = 60, H_SPR_HSR45 = 61, H_SPR_HSR46 = 62
+ , H_SPR_HSR47 = 63, H_SPR_HSR48 = 64, H_SPR_HSR49 = 65, H_SPR_HSR50 = 66
+ , H_SPR_HSR51 = 67, H_SPR_HSR52 = 68, H_SPR_HSR53 = 69, H_SPR_HSR54 = 70
+ , H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74
+ , H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78
+ , H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272
+ , H_SPR_LCR = 273, H_SPR_ISR = 288, H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353
+ , H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355, H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357
+ , H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359, H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361
+ , H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363, H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365
+ , H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367, H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369
+ , H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371, H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373
+ , H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375, H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377
+ , H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379, H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381
+ , H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383, H_SPR_NESR0 = 384, H_SPR_NESR1 = 385
+ , H_SPR_NESR2 = 386, H_SPR_NESR3 = 387, H_SPR_NESR4 = 388, H_SPR_NESR5 = 389
+ , H_SPR_NESR6 = 390, H_SPR_NESR7 = 391, H_SPR_NESR8 = 392, H_SPR_NESR9 = 393
+ , H_SPR_NESR10 = 394, H_SPR_NESR11 = 395, H_SPR_NESR12 = 396, H_SPR_NESR13 = 397
+ , H_SPR_NESR14 = 398, H_SPR_NESR15 = 399, H_SPR_NESR16 = 400, H_SPR_NESR17 = 401
+ , H_SPR_NESR18 = 402, H_SPR_NESR19 = 403, H_SPR_NESR20 = 404, H_SPR_NESR21 = 405
+ , H_SPR_NESR22 = 406, H_SPR_NESR23 = 407, H_SPR_NESR24 = 408, H_SPR_NESR25 = 409
+ , H_SPR_NESR26 = 410, H_SPR_NESR27 = 411, H_SPR_NESR28 = 412, H_SPR_NESR29 = 413
+ , H_SPR_NESR30 = 414, H_SPR_NESR31 = 415, H_SPR_NECR = 416, H_SPR_GNER0 = 432
+ , H_SPR_GNER1 = 433, H_SPR_FNER0 = 434, H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512
+ , H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514, H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516
+ , H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518, H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520
+ , H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522, H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524
+ , H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526, H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528
+ , H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530, H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532
+ , H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534, H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536
+ , H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538, H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540
+ , H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542, H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544
+ , H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546, H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548
+ , H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550, H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552
+ , H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554, H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556
+ , H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558, H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560
+ , H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562, H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564
+ , H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566, H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568
+ , H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570, H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572
+ , H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574, H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576
+ , H_SPR_ESR1 = 577, H_SPR_ESR2 = 578, H_SPR_ESR3 = 579, H_SPR_ESR4 = 580
+ , H_SPR_ESR5 = 581, H_SPR_ESR6 = 582, H_SPR_ESR7 = 583, H_SPR_ESR8 = 584
+ , H_SPR_ESR9 = 585, H_SPR_ESR10 = 586, H_SPR_ESR11 = 587, H_SPR_ESR12 = 588
+ , H_SPR_ESR13 = 589, H_SPR_ESR14 = 590, H_SPR_ESR15 = 591, H_SPR_ESR16 = 592
+ , H_SPR_ESR17 = 593, H_SPR_ESR18 = 594, H_SPR_ESR19 = 595, H_SPR_ESR20 = 596
+ , H_SPR_ESR21 = 597, H_SPR_ESR22 = 598, H_SPR_ESR23 = 599, H_SPR_ESR24 = 600
+ , H_SPR_ESR25 = 601, H_SPR_ESR26 = 602, H_SPR_ESR27 = 603, H_SPR_ESR28 = 604
+ , H_SPR_ESR29 = 605, H_SPR_ESR30 = 606, H_SPR_ESR31 = 607, H_SPR_ESR32 = 608
+ , H_SPR_ESR33 = 609, H_SPR_ESR34 = 610, H_SPR_ESR35 = 611, H_SPR_ESR36 = 612
+ , H_SPR_ESR37 = 613, H_SPR_ESR38 = 614, H_SPR_ESR39 = 615, H_SPR_ESR40 = 616
+ , H_SPR_ESR41 = 617, H_SPR_ESR42 = 618, H_SPR_ESR43 = 619, H_SPR_ESR44 = 620
+ , H_SPR_ESR45 = 621, H_SPR_ESR46 = 622, H_SPR_ESR47 = 623, H_SPR_ESR48 = 624
+ , H_SPR_ESR49 = 625, H_SPR_ESR50 = 626, H_SPR_ESR51 = 627, H_SPR_ESR52 = 628
+ , H_SPR_ESR53 = 629, H_SPR_ESR54 = 630, H_SPR_ESR55 = 631, H_SPR_ESR56 = 632
+ , H_SPR_ESR57 = 633, H_SPR_ESR58 = 634, H_SPR_ESR59 = 635, H_SPR_ESR60 = 636
+ , H_SPR_ESR61 = 637, H_SPR_ESR62 = 638, H_SPR_ESR63 = 639, H_SPR_EIR0 = 640
+ , H_SPR_EIR1 = 641, H_SPR_EIR2 = 642, H_SPR_EIR3 = 643, H_SPR_EIR4 = 644
+ , H_SPR_EIR5 = 645, H_SPR_EIR6 = 646, H_SPR_EIR7 = 647, H_SPR_EIR8 = 648
+ , H_SPR_EIR9 = 649, H_SPR_EIR10 = 650, H_SPR_EIR11 = 651, H_SPR_EIR12 = 652
+ , H_SPR_EIR13 = 653, H_SPR_EIR14 = 654, H_SPR_EIR15 = 655, H_SPR_EIR16 = 656
+ , H_SPR_EIR17 = 657, H_SPR_EIR18 = 658, H_SPR_EIR19 = 659, H_SPR_EIR20 = 660
+ , H_SPR_EIR21 = 661, H_SPR_EIR22 = 662, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664
+ , H_SPR_EIR25 = 665, H_SPR_EIR26 = 666, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668
+ , H_SPR_EIR29 = 669, H_SPR_EIR30 = 670, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672
+ , H_SPR_ESFR1 = 673, H_SPR_SR0 = 768, H_SPR_SR1 = 769, H_SPR_SR2 = 770
+ , H_SPR_SR3 = 771, H_SPR_FSR0 = 1024, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026
+ , H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030
+ , H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034
+ , H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036, H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038
+ , H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040, H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042
+ , H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044, H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046
+ , H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048, H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050
+ , H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052, H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054
+ , H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056, H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058
+ , H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060, H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062
+ , H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064, H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066
+ , H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068, H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070
+ , H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072, H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074
+ , H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076, H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078
+ , H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080, H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082
+ , H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084, H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086
+ , H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088, H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092
+ , H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096, H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100
+ , H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104, H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108
+ , H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112, H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116
+ , H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120, H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124
+ , H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128, H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132
+ , H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136, H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140
+ , H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144, H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148
+ , H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089, H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093
+ , H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097, H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101
+ , H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105, H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109
+ , H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113, H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117
+ , H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121, H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125
+ , H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129, H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133
+ , H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137, H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141
+ , H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145, H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149
+ , H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272, H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280
+ , H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282, H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284
+ , H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286, H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288
+ , H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290, H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292
+ , H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294, H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296
+ , H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298, H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300
+ , H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302, H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304
+ , H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306, H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308
+ , H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310, H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312
+ , H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314, H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316
+ , H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318, H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320
+ , H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322, H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324
+ , H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326, H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328
+ , H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330, H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332
+ , H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334, H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336
+ , H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338, H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340
+ , H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342, H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344
+ , H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348, H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352
+ , H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356, H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360
+ , H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364, H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368
+ , H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372, H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376
+ , H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380, H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384
+ , H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388, H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392
+ , H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396, H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400
+ , H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404, H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345
+ , H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349, H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353
+ , H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357, H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361
+ , H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365, H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369
+ , H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373, H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377
+ , H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381, H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385
+ , H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389, H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393
+ , H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397, H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401
+ , H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405, H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536
+ , H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538, H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540
+ , H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542, H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544
+ , H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546, H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548
+ , H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550, H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552
+ , H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554, H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556
+ , H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558, H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560
+ , H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562, H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564
+ , H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566, H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568
+ , H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570, H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572
+ , H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574, H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576
+ , H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578, H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580
+ , H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582, H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584
+ , H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586, H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588
+ , H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590, H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592
+ , H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594, H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596
+ , H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598, H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600
+ , H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602, H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604
+ , H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606, H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608
+ , H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610, H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612
+ , H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614, H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616
+ , H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618, H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620
+ , H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622, H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624
+ , H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626, H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628
+ , H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630, H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632
+ , H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634, H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636
+ , H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638, H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640
+ , H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642, H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644
+ , H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646, H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648
+ , H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650, H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652
+ , H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654, H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656
+ , H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658, H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660
+ , H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662, H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664
+ , H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666, H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668
+ , H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670, H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672
+ , H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674, H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676
+ , H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678, H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680
+ , H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682, H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684
+ , H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686, H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688
+ , H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690, H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692
+ , H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694, H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696
+ , H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698, H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700
+ , H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702, H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704
+ , H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706, H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708
+ , H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710, H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712
+ , H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714, H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716
+ , H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718, H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720
+ , H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722, H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724
+ , H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726, H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728
+ , H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730, H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732
+ , H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734, H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736
+ , H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738, H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740
+ , H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742, H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744
+ , H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746, H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748
+ , H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750, H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752
+ , H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754, H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756
+ , H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758, H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760
+ , H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762, H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764
+ , H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766, H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768
+ , H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770, H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772
+ , H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774, H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776
+ , H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778, H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780
+ , H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782, H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784
+ , H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786, H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788
+ , H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790, H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792
+ , H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794, H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796
+ , H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798, H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800
+ , H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802, H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804
+ , H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806, H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808
+ , H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810, H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812
+ , H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814, H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816
+ , H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818, H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820
+ , H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822, H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824
+ , H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826, H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828
+ , H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830, H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832
+ , H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834, H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836
+ , H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838, H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840
+ , H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842, H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844
+ , H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846, H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848
+ , H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850, H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852
+ , H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854, H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856
+ , H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858, H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860
+ , H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862, H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864
+ , H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866, H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868
+ , H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870, H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872
+ , H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874, H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876
+ , H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878, H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880
+ , H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882, H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884
+ , H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886, H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888
+ , H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890, H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892
+ , H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894, H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896
+ , H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898, H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900
+ , H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902, H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904
+ , H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906, H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908
+ , H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912
+ , H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916
+ , H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920
+ , H_SPR_STBAR = 1921, H_SPR_MMCR = 1922, H_SPR_DCR = 2048, H_SPR_BRR = 2049
+ , H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054
+ , H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058
+ , H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062
+ , H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066
+ , H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070
+ , H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074
+ , H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078
+ , H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082
+ , H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086
+ , H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090
+ , H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093, H_SPR_CPSR = 2094
+ , H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099
+ , H_SPR_IHSR8 = 3848
+} SPR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum accg_names {
+  H_ACCG_ACCG0, H_ACCG_ACCG1, H_ACCG_ACCG2, H_ACCG_ACCG3
+ , H_ACCG_ACCG4, H_ACCG_ACCG5, H_ACCG_ACCG6, H_ACCG_ACCG7
+ , H_ACCG_ACCG8, H_ACCG_ACCG9, H_ACCG_ACCG10, H_ACCG_ACCG11
+ , H_ACCG_ACCG12, H_ACCG_ACCG13, H_ACCG_ACCG14, H_ACCG_ACCG15
+ , H_ACCG_ACCG16, H_ACCG_ACCG17, H_ACCG_ACCG18, H_ACCG_ACCG19
+ , H_ACCG_ACCG20, H_ACCG_ACCG21, H_ACCG_ACCG22, H_ACCG_ACCG23
+ , H_ACCG_ACCG24, H_ACCG_ACCG25, H_ACCG_ACCG26, H_ACCG_ACCG27
+ , H_ACCG_ACCG28, H_ACCG_ACCG29, H_ACCG_ACCG30, H_ACCG_ACCG31
+ , H_ACCG_ACCG32, H_ACCG_ACCG33, H_ACCG_ACCG34, H_ACCG_ACCG35
+ , H_ACCG_ACCG36, H_ACCG_ACCG37, H_ACCG_ACCG38, H_ACCG_ACCG39
+ , H_ACCG_ACCG40, H_ACCG_ACCG41, H_ACCG_ACCG42, H_ACCG_ACCG43
+ , H_ACCG_ACCG44, H_ACCG_ACCG45, H_ACCG_ACCG46, H_ACCG_ACCG47
+ , H_ACCG_ACCG48, H_ACCG_ACCG49, H_ACCG_ACCG50, H_ACCG_ACCG51
+ , H_ACCG_ACCG52, H_ACCG_ACCG53, H_ACCG_ACCG54, H_ACCG_ACCG55
+ , H_ACCG_ACCG56, H_ACCG_ACCG57, H_ACCG_ACCG58, H_ACCG_ACCG59
+ , H_ACCG_ACCG60, H_ACCG_ACCG61, H_ACCG_ACCG62, H_ACCG_ACCG63
+} ACCG_NAMES;
+
+/* Enum declaration for .  */
+typedef enum acc_names {
+  H_ACC40_ACC0, H_ACC40_ACC1, H_ACC40_ACC2, H_ACC40_ACC3
+ , H_ACC40_ACC4, H_ACC40_ACC5, H_ACC40_ACC6, H_ACC40_ACC7
+ , H_ACC40_ACC8, H_ACC40_ACC9, H_ACC40_ACC10, H_ACC40_ACC11
+ , H_ACC40_ACC12, H_ACC40_ACC13, H_ACC40_ACC14, H_ACC40_ACC15
+ , H_ACC40_ACC16, H_ACC40_ACC17, H_ACC40_ACC18, H_ACC40_ACC19
+ , H_ACC40_ACC20, H_ACC40_ACC21, H_ACC40_ACC22, H_ACC40_ACC23
+ , H_ACC40_ACC24, H_ACC40_ACC25, H_ACC40_ACC26, H_ACC40_ACC27
+ , H_ACC40_ACC28, H_ACC40_ACC29, H_ACC40_ACC30, H_ACC40_ACC31
+ , H_ACC40_ACC32, H_ACC40_ACC33, H_ACC40_ACC34, H_ACC40_ACC35
+ , H_ACC40_ACC36, H_ACC40_ACC37, H_ACC40_ACC38, H_ACC40_ACC39
+ , H_ACC40_ACC40, H_ACC40_ACC41, H_ACC40_ACC42, H_ACC40_ACC43
+ , H_ACC40_ACC44, H_ACC40_ACC45, H_ACC40_ACC46, H_ACC40_ACC47
+ , H_ACC40_ACC48, H_ACC40_ACC49, H_ACC40_ACC50, H_ACC40_ACC51
+ , H_ACC40_ACC52, H_ACC40_ACC53, H_ACC40_ACC54, H_ACC40_ACC55
+ , H_ACC40_ACC56, H_ACC40_ACC57, H_ACC40_ACC58, H_ACC40_ACC59
+ , H_ACC40_ACC60, H_ACC40_ACC61, H_ACC40_ACC62, H_ACC40_ACC63
+} ACC_NAMES;
+
+/* Enum declaration for .  */
+typedef enum iccr_names {
+  H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3
+} ICCR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum fccr_names {
+  H_FCCR_FCC0, H_FCCR_FCC1, H_FCCR_FCC2, H_FCCR_FCC3
+} FCCR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum cccr_names {
+  H_CCCR_CC0, H_CCCR_CC1, H_CCCR_CC2, H_CCCR_CC3
+ , H_CCCR_CC4, H_CCCR_CC5, H_CCCR_CC6, H_CCCR_CC7
+} CCCR_NAMES;
+
+/* Attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_FRV, MACH_FR500, MACH_FR400
+ , MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection.  */
+typedef enum isa_attr {
+  ISA_FRV, ISA_MAX
+} ISA_ATTR;
+
+/* Enum declaration for parallel execution pipeline selection.  */
+typedef enum unit_attr {
+  UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01
+ , UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0
+ , UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV
+ , UNIT_LOAD, UNIT_NUM_UNITS
+} UNIT_ATTR;
+
+/* Enum declaration for fr400 major insn categories.  */
+typedef enum fr400_major_attr {
+  FR400_MAJOR_NONE, FR400_MAJOR_I_1, FR400_MAJOR_I_2, FR400_MAJOR_I_3
+ , FR400_MAJOR_I_4, FR400_MAJOR_I_5, FR400_MAJOR_B_1, FR400_MAJOR_B_2
+ , FR400_MAJOR_B_3, FR400_MAJOR_B_4, FR400_MAJOR_B_5, FR400_MAJOR_B_6
+ , FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2
+} FR400_MAJOR_ATTR;
+
+/* Enum declaration for fr500 major insn categories.  */
+typedef enum fr500_major_attr {
+  FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3
+ , FR500_MAJOR_I_4, FR500_MAJOR_I_5, FR500_MAJOR_I_6, FR500_MAJOR_B_1
+ , FR500_MAJOR_B_2, FR500_MAJOR_B_3, FR500_MAJOR_B_4, FR500_MAJOR_B_5
+ , FR500_MAJOR_B_6, FR500_MAJOR_C_1, FR500_MAJOR_C_2, FR500_MAJOR_F_1
+ , FR500_MAJOR_F_2, FR500_MAJOR_F_3, FR500_MAJOR_F_4, FR500_MAJOR_F_5
+ , FR500_MAJOR_F_6, FR500_MAJOR_F_7, FR500_MAJOR_F_8, FR500_MAJOR_M_1
+ , FR500_MAJOR_M_2, FR500_MAJOR_M_3, FR500_MAJOR_M_4, FR500_MAJOR_M_5
+ , FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8
+} FR500_MAJOR_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_ISAS  1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support.  */
+
+extern const struct cgen_ifld frv_cgen_ifld_table[];
+
+/* Ifield attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr.  */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* Enum declaration for frv ifield types.  */
+typedef enum ifield_type {
+  FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP
+ , FRV_F_OPE1, FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4
+ , FRV_F_GRI, FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI
+ , FRV_F_FRJ, FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ
+ , FRV_F_CPRK, FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI
+ , FRV_F_ACC40UI, FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI
+ , FRV_F_CRJ, FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT
+ , FRV_F_CRJ_FLOAT, FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3
+ , FRV_F_FCCI_1, FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK
+ , FRV_F_EIR, FRV_F_S10, FRV_F_S12, FRV_F_D12
+ , FRV_F_U16, FRV_F_S16, FRV_F_S6, FRV_F_S6_1
+ , FRV_F_U6, FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L
+ , FRV_F_U12, FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND
+ , FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK
+ , FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H
+ , FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6
+ , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL
+ , FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL
+ , FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL
+ , FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL
+ , FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL
+ , FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4
+ , FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8
+ , FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF
+ , FRV_F_LI_ON, FRV_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) FRV_F_MAX)
+
+/* Hardware attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr.  */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* Enum declaration for frv hardware types.  */
+typedef enum cgen_hw_type {
+  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER
+ , HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE
+ , HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL
+ , HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA
+ , HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR
+ , HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR
+ , HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO
+ , HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3
+ , HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG
+ , HW_H_ACC40S, HW_H_ACC40U, HW_H_ICCR, HW_H_FCCR
+ , HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN, HW_H_HINT_NOT_TAKEN
+ , HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices.  */
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr.  */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* Enum declaration for frv operand types.  */
+typedef enum cgen_operand_type {
+  FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ
+ , FRV_OPERAND_GRK, FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK
+ , FRV_OPERAND_ACC40SI, FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK
+ , FRV_OPERAND_ACCGI, FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ
+ , FRV_OPERAND_CPRK, FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ
+ , FRV_OPERAND_FRINTK, FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK
+ , FRV_OPERAND_FRKHI, FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ
+ , FRV_OPERAND_FRDOUBLEK, FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT
+ , FRV_OPERAND_CRJ_FLOAT, FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1
+ , FRV_OPERAND_ICCI_2, FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2
+ , FRV_OPERAND_FCCI_3, FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10
+ , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1
+ , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
+ , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
+ , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE
+ , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12
+ , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
+ , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
+ , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
+ , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types.  */
+#define MAX_OPERANDS 77
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices.  */
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
+ , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
+ , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
+ , CGEN_INSN_FR500_MAJOR, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr.  */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[];
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD frv_cgen_opval_gr_names;
+extern CGEN_KEYWORD frv_cgen_opval_gr_names;
+extern CGEN_KEYWORD frv_cgen_opval_gr_names;
+extern CGEN_KEYWORD frv_cgen_opval_gr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fr_names;
+extern CGEN_KEYWORD frv_cgen_opval_cpr_names;
+extern CGEN_KEYWORD frv_cgen_opval_cpr_names;
+extern CGEN_KEYWORD frv_cgen_opval_spr_names;
+extern CGEN_KEYWORD frv_cgen_opval_accg_names;
+extern CGEN_KEYWORD frv_cgen_opval_acc_names;
+extern CGEN_KEYWORD frv_cgen_opval_acc_names;
+extern CGEN_KEYWORD frv_cgen_opval_iccr_names;
+extern CGEN_KEYWORD frv_cgen_opval_fccr_names;
+extern CGEN_KEYWORD frv_cgen_opval_cccr_names;
+extern CGEN_KEYWORD frv_cgen_opval_h_pack;
+extern CGEN_KEYWORD frv_cgen_opval_h_hint_taken;
+extern CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken;
+
+
+
+
+#endif /* FRV_CPU_H */

--- /dev/null
+++ b/opcodes/frv-dis.c
@@ -0,0 +1,789 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-dis.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized.  */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+     PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+     PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+     PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static void print_insn_normal
+     PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+	      bfd_vma, int));
+static int print_insn
+     PARAMS ((CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned));
+static int default_print_insn
+     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+static int read_insn
+     PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
+	      CGEN_EXTRACT_INFO *, unsigned long *));
+
+/* -- disassembler routines inserted here */
+
+/* -- dis.c */
+static void print_spr
+  PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
+static void print_hi
+  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+static void print_lo
+  PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
+
+static void
+print_spr (cd, dis_info, names, regno, attrs)
+     CGEN_CPU_DESC cd;
+     PTR dis_info;
+     CGEN_KEYWORD *names;
+     long regno;
+     unsigned int attrs;
+{
+  /* Use the register index format for any unnamed registers.  */
+  if (cgen_keyword_lookup_value (names, regno) == NULL)
+    {
+      disassemble_info *info = (disassemble_info *) dis_info;
+      (*info->fprintf_func) (info->stream, "spr[%ld]", regno);
+    }
+  else
+    print_keyword (cd, dis_info, names, regno, attrs);
+}
+
+static void
+print_hi (cd, dis_info, value, attrs, pc, length)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     PTR dis_info;
+     long value;
+     unsigned int attrs ATTRIBUTE_UNUSED;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+     int length ATTRIBUTE_UNUSED;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  if (value)
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+  else
+    (*info->fprintf_func) (info->stream, "hi(0x%lx)", value);
+}
+
+static void
+print_lo (cd, dis_info, value, attrs, pc, length)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     PTR dis_info;
+     long value;
+     unsigned int attrs ATTRIBUTE_UNUSED;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+     int length ATTRIBUTE_UNUSED;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  if (value)
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+  else
+    (*info->fprintf_func) (info->stream, "lo(0x%lx)", value);
+}
+
+/* -- */
+
+void frv_cgen_print_operand
+  PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
+           void const *, bfd_vma, int));
+
+/* Main entry point for printing operands.
+   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+   of dis-asm.h on cgen.h.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+void
+frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
+     CGEN_CPU_DESC cd;
+     int opindex;
+     PTR xinfo;
+     CGEN_FIELDS *fields;
+     void const *attrs ATTRIBUTE_UNUSED;
+     bfd_vma pc;
+     int length;
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_ACC40SI :
+      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0);
+      break;
+    case FRV_OPERAND_ACC40SK :
+      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0);
+      break;
+    case FRV_OPERAND_ACC40UI :
+      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0);
+      break;
+    case FRV_OPERAND_ACC40UK :
+      print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0);
+      break;
+    case FRV_OPERAND_ACCGI :
+      print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0);
+      break;
+    case FRV_OPERAND_ACCGK :
+      print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0);
+      break;
+    case FRV_OPERAND_CCI :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0);
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
+      break;
+    case FRV_OPERAND_CPRI :
+      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0);
+      break;
+    case FRV_OPERAND_CPRJ :
+      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0);
+      break;
+    case FRV_OPERAND_CPRK :
+      print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0);
+      break;
+    case FRV_OPERAND_CRI :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0);
+      break;
+    case FRV_OPERAND_CRJ :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0);
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0);
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0);
+      break;
+    case FRV_OPERAND_CRK :
+      print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0);
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0);
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0);
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0);
+      break;
+    case FRV_OPERAND_FCCK :
+      print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0);
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
+    case FRV_OPERAND_FRI :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
+      break;
+    case FRV_OPERAND_FRINTI :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0);
+      break;
+    case FRV_OPERAND_FRINTJ :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
+      break;
+    case FRV_OPERAND_FRINTK :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
+    case FRV_OPERAND_FRJ :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0);
+      break;
+    case FRV_OPERAND_FRK :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
+    case FRV_OPERAND_FRKHI :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
+    case FRV_OPERAND_FRKLO :
+      print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0);
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
+      break;
+    case FRV_OPERAND_GRI :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0);
+      break;
+    case FRV_OPERAND_GRJ :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0);
+      break;
+    case FRV_OPERAND_GRK :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
+      break;
+    case FRV_OPERAND_GRKHI :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
+      break;
+    case FRV_OPERAND_GRKLO :
+      print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0);
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0);
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0);
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0);
+      break;
+    case FRV_OPERAND_LI :
+      print_normal (cd, info, fields->f_LI, 0, pc, length);
+      break;
+    case FRV_OPERAND_AE :
+      print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_CCOND :
+      print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_COND :
+      print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_D12 :
+      print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case FRV_OPERAND_DEBUG :
+      print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_EIR :
+      print_normal (cd, info, fields->f_eir, 0, pc, length);
+      break;
+    case FRV_OPERAND_HINT :
+      print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0);
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0);
+      break;
+    case FRV_OPERAND_LABEL16 :
+      print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case FRV_OPERAND_LABEL24 :
+      print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case FRV_OPERAND_LOCK :
+      print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_PACK :
+      print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0);
+      break;
+    case FRV_OPERAND_S10 :
+      print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_S12 :
+      print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_S16 :
+      print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_S5 :
+      print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_S6 :
+      print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_S6_1 :
+      print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_SLO16 :
+      print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case FRV_OPERAND_SPR :
+      print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL));
+      break;
+    case FRV_OPERAND_U12 :
+      print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+      break;
+    case FRV_OPERAND_U16 :
+      print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_U6 :
+      print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case FRV_OPERAND_UHI16 :
+      print_hi (cd, info, fields->f_u16, 0, pc, length);
+      break;
+    case FRV_OPERAND_ULO16 :
+      print_lo (cd, info, fields->f_u16, 0, pc, length);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+	       opindex);
+    abort ();
+  }
+}
+
+cgen_print_fn * const frv_cgen_print_handlers[] = 
+{
+  print_insn_normal,
+};
+
+
+void
+frv_cgen_init_dis (cd)
+     CGEN_CPU_DESC cd;
+{
+  frv_cgen_init_opcode_table (cd);
+  frv_cgen_init_ibld_table (cd);
+  cd->print_handlers = & frv_cgen_print_handlers[0];
+  cd->print_operand = frv_cgen_print_operand;
+}
+
+
+/* Default print handler.  */
+
+static void
+print_normal (cd, dis_info, value, attrs, pc, length)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     PTR dis_info;
+     long value;
+     unsigned int attrs;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+     int length ATTRIBUTE_UNUSED;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler.  */
+
+static void
+print_address (cd, dis_info, value, attrs, pc, length)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     PTR dis_info;
+     bfd_vma value;
+     unsigned int attrs;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+     int length ATTRIBUTE_UNUSED;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", (long) value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler.  */
+
+static void
+print_keyword (cd, dis_info, keyword_table, value, attrs)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     PTR dis_info;
+     CGEN_KEYWORD *keyword_table;
+     long value;
+     unsigned int attrs ATTRIBUTE_UNUSED;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
+
+  ke = cgen_keyword_lookup_value (keyword_table, value);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   about disassemble_info.  */
+
+static void
+print_insn_normal (cd, dis_info, insn, fields, pc, length)
+     CGEN_CPU_DESC cd;
+     PTR dis_info;
+     const CGEN_INSN *insn;
+     CGEN_FIELDS *fields;
+     bfd_vma pc;
+     int length;
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_INIT_PRINT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+	  continue;
+	}
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+	  continue;
+	}
+
+      /* We have an operand.  */
+      frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+				 fields, CGEN_INSN_ATTRS (insn), pc, length);
+    }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+   the extract info.
+   Returns 0 if all is well, non-zero otherwise.  */
+
+static int
+read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     bfd_vma pc;
+     disassemble_info *info;
+     char *buf;
+     int buflen;
+     CGEN_EXTRACT_INFO *ex_info;
+     unsigned long *insn_value;
+{
+  int status = (*info->read_memory_func) (pc, buf, buflen, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  ex_info->dis_info = info;
+  ex_info->valid = (1 << buflen) - 1;
+  ex_info->insn_bytes = buf;
+
+  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+  return 0;
+}
+
+/* Utility to print an insn.
+   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+print_insn (cd, pc, info, buf, buflen)
+     CGEN_CPU_DESC cd;
+     bfd_vma pc;
+     disassemble_info *info;
+     char *buf;
+     unsigned int buflen;
+{
+  CGEN_INSN_INT insn_value;
+  const CGEN_INSN_LIST *insn_list;
+  CGEN_EXTRACT_INFO ex_info;
+  int basesize;
+
+  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+  basesize = cd->base_insn_bitsize < buflen * 8 ?
+                                     cd->base_insn_bitsize : buflen * 8;
+  insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+  /* Fill in ex_info fields like read_insn would.  Don't actually call
+     read_insn, since the incoming buffer is already read (and possibly
+     modified a la m32r).  */
+  ex_info.valid = (1 << buflen) - 1;
+  ex_info.dis_info = info;
+  ex_info.insn_bytes = buf;
+
+  /* The instructions are stored in hash lists.
+     Pick the first one and keep trying until we find the right one.  */
+
+  insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
+  while (insn_list != NULL)
+    {
+      const CGEN_INSN *insn = insn_list->insn;
+      CGEN_FIELDS fields;
+      int length;
+      unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not needed as insn shouldn't be in hash lists if not supported.  */
+      /* Supported by this cpu?  */
+      if (! frv_cgen_insn_supported (cd, insn))
+        {
+          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+	  continue;
+        }
+#endif
+
+      /* Basic bit mask must be correct.  */
+      /* ??? May wish to allow target to defer this check until the extract
+	 handler.  */
+
+      /* Base size may exceed this instruction's size.  Extract the
+         relevant part from the buffer. */
+      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
+					   info->endian == BFD_ENDIAN_BIG);
+      else
+	insn_value_cropped = insn_value;
+
+      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+	  == CGEN_INSN_BASE_VALUE (insn))
+	{
+	  /* Printing is handled in two passes.  The first pass parses the
+	     machine insn and extracts the fields.  The second pass prints
+	     them.  */
+
+	  /* Make sure the entire insn is loaded into insn_value, if it
+	     can fit.  */
+	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	    {
+	      unsigned long full_insn_value;
+	      int rc = read_insn (cd, pc, info, buf,
+				  CGEN_INSN_BITSIZE (insn) / 8,
+				  & ex_info, & full_insn_value);
+	      if (rc != 0)
+		return rc;
+	      length = CGEN_EXTRACT_FN (cd, insn)
+		(cd, insn, &ex_info, full_insn_value, &fields, pc);
+	    }
+	  else
+	    length = CGEN_EXTRACT_FN (cd, insn)
+	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+	  /* length < 0 -> error */
+	  if (length < 0)
+	    return length;
+	  if (length > 0)
+	    {
+	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+	      /* length is in bits, result is in bytes */
+	      return length / 8;
+	    }
+	}
+
+      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+    }
+
+  return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occured fetching bytes.  */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (cd, pc, info)
+     CGEN_CPU_DESC cd;
+     bfd_vma pc;
+     disassemble_info *info;
+{
+  char buf[CGEN_MAX_INSN_SIZE];
+  int buflen;
+  int status;
+
+  /* Attempt to read the base part of the insn.  */
+  buflen = cd->base_insn_bitsize / 8;
+  status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  /* Try again with the minimum part, if min < base.  */
+  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+    {
+      buflen = cd->min_insn_bitsize / 8;
+      status = (*info->read_memory_func) (pc, buf, buflen, info);
+    }
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+   Print one instruction from PC on INFO->STREAM.
+   Return the size of the instruction (in bytes).  */
+
+typedef struct cpu_desc_list {
+  struct cpu_desc_list *next;
+  int isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_frv (pc, info)
+     bfd_vma pc;
+     disassemble_info *info;
+{
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
+  static CGEN_CPU_DESC cd = 0;
+  static int prev_isa;
+  static int prev_mach;
+  static int prev_endian;
+  int length;
+  int isa,mach;
+  int endian = (info->endian == BFD_ENDIAN_BIG
+		? CGEN_ENDIAN_BIG
+		: CGEN_ENDIAN_LITTLE);
+  enum bfd_architecture arch;
+
+  /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_frv
+#endif
+  arch = info->arch;
+  if (arch == bfd_arch_unknown)
+    arch = CGEN_BFD_ARCH;
+   
+  /* There's no standard way to compute the machine or isa number
+     so we leave it to the target.  */
+#ifdef CGEN_COMPUTE_MACH
+  mach = CGEN_COMPUTE_MACH (info);
+#else
+  mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+  isa = CGEN_COMPUTE_ISA (info);
+#else
+  isa = info->insn_sets;
+#endif
+
+  /* If we've switched cpu's, try to find a handle we've used before */
+  if (cd
+      && (isa != prev_isa
+	  || mach != prev_mach
+	  || endian != prev_endian))
+    {
+      cd = 0;
+      for (cl = cd_list; cl; cl = cl->next)
+	{
+	  if (cl->isa == isa &&
+	      cl->mach == mach &&
+	      cl->endian == endian)
+	    {
+	      cd = cl->cd;
+	      break;
+	    }
+	}
+    } 
+
+  /* If we haven't initialized yet, initialize the opcode table.  */
+  if (! cd)
+    {
+      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+      const char *mach_name;
+
+      if (!arch_type)
+	abort ();
+      mach_name = arch_type->printable_name;
+
+      prev_isa = isa;
+      prev_mach = mach;
+      prev_endian = endian;
+      cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+				 CGEN_CPU_OPEN_BFDMACH, mach_name,
+				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
+				 CGEN_CPU_OPEN_END);
+      if (!cd)
+	abort ();
+
+      /* save this away for future reference */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
+      frv_cgen_init_dis (cd);
+    }
+
+  /* We try to have as much common code as possible.
+     But at this point some targets need to take over.  */
+  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
+     but if not possible try to move this hook elsewhere rather than
+     have two hooks.  */
+  length = CGEN_PRINT_INSN (cd, pc, info);
+  if (length > 0)
+    return length;
+  if (length < 0)
+    return -1;
+
+  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+  return cd->default_insn_bitsize / 8;
+}

--- /dev/null
+++ b/opcodes/frv-ibld.c
@@ -0,0 +1,2051 @@
+/* Instruction building/extraction support for frv. -*- C -*-
+
+THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+- the resultant file is machine generated, cgen-ibld.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+     PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+	      unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+static const char * insert_insn_normal
+     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
+	      CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+static int extract_normal
+     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+	      unsigned int, unsigned int, unsigned int, unsigned int,
+	      unsigned int, unsigned int, bfd_vma, long *));
+static int extract_insn_normal
+     PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+	      CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+     PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+     PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *));
+static CGEN_INLINE int fill_cache
+     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma));
+static CGEN_INLINE long extract_1
+     PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int,
+	      unsigned char *, bfd_vma));
+#endif
+
+/* Operand insertion.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal.  */
+
+static CGEN_INLINE void
+insert_1 (cd, value, start, length, word_length, bufp)
+     CGEN_CPU_DESC cd;
+     unsigned long value;
+     int start,length,word_length;
+     unsigned char *bufp;
+{
+  unsigned long x,mask;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+  cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+   ATTRS is a mask of the boolean attributes.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   The result is an error message or NULL if success.  */
+
+/* ??? This duplicates functionality with bfd's howto table and
+   bfd_install_relocation.  */
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static const char *
+insert_normal (cd, value, attrs, word_offset, start, length, word_length,
+	       total_length, buffer)
+     CGEN_CPU_DESC cd;
+     long value;
+     unsigned int attrs;
+     unsigned int word_offset, start, length, word_length, total_length;
+     CGEN_INSN_BYTES_PTR buffer;
+{
+  static char errbuf[100];
+  /* Written this way to avoid undefined behaviour.  */
+  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
+  if (length == 0)
+    return NULL;
+
+#if 0
+  if (CGEN_INT_INSN_P
+      && word_offset != 0)
+    abort ();
+#endif
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset == 0
+	  && word_length > total_length)
+	word_length = total_length;
+    }
+
+  /* Ensure VALUE will fit.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+    {
+      long minval = - (1L << (length - 1));
+      unsigned long maxval = mask;
+      
+      if ((value > 0 && (unsigned long) value > maxval)
+	  || value < minval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%ld not between %ld and %lu)"),
+		   value, minval, maxval);
+	  return errbuf;
+	}
+    }
+  else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+    {
+      unsigned long maxval = mask;
+      
+      if ((unsigned long) value > maxval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%lu not between 0 and %lu)"),
+		   value, maxval);
+	  return errbuf;
+	}
+    }
+  else
+    {
+      if (! cgen_signed_overflow_ok_p (cd))
+	{
+	  long minval = - (1L << (length - 1));
+	  long maxval =   (1L << (length - 1)) - 1;
+	  
+	  if (value < minval || value > maxval)
+	    {
+	      sprintf
+		/* xgettext:c-format */
+		(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+		 value, minval, maxval);
+	      return errbuf;
+	    }
+	}
+    }
+
+#if CGEN_INT_INSN_P
+
+  {
+    int shift;
+
+    if (CGEN_INSN_LSB0_P)
+      shift = (word_offset + start + 1) - length;
+    else
+      shift = total_length - (word_offset + start + length);
+    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+  }
+
+#else /* ! CGEN_INT_INSN_P */
+
+  {
+    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+    insert_1 (cd, value, start, length, word_length, bufp);
+  }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  return NULL;
+}
+
+/* Default insn builder (insert handler).
+   The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+   that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+   recorded in host byte order, otherwise BUFFER is an array of bytes
+   and the value is recorded in target byte order).
+   The result is an error message or NULL if success.  */
+
+static const char *
+insert_insn_normal (cd, insn, fields, buffer, pc)
+     CGEN_CPU_DESC cd;
+     const CGEN_INSN * insn;
+     CGEN_FIELDS * fields;
+     CGEN_INSN_BYTES_PTR buffer;
+     bfd_vma pc;
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  unsigned long value;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+  CGEN_INIT_INSERT (cd);
+  value = CGEN_INSN_BASE_VALUE (insn);
+
+  /* If we're recording insns as numbers (rather than a string of bytes),
+     target byte order handling is deferred until later.  */
+
+#if CGEN_INT_INSN_P
+
+  put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+		      CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+  cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+					(unsigned) CGEN_FIELDS_BITSIZE (fields)),
+		       value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* ??? It would be better to scan the format's fields.
+     Still need to be able to insert a value based on the operand though;
+     e.g. storing a branch displacement that got resolved later.
+     Needs more thought first.  */
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+    {
+      const char *errmsg;
+
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	continue;
+
+      errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+				       fields, buffer, pc);
+      if (errmsg)
+	return errmsg;
+    }
+
+  return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn.  Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+
+static void
+put_insn_int_value (cd, buf, length, insn_length, value)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     CGEN_INSN_BYTES_PTR buf;
+     int length;
+     int insn_length;
+     CGEN_INSN_INT value;
+{
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     length may be too big.  */
+  if (length > insn_length)
+    *buf = value;
+  else
+    {
+      int shift = insn_length - length;
+      /* Written this way to avoid undefined behaviour.  */
+      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+      *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+    }
+}
+#endif
+
+/* Operand extraction.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+   Ensure sufficient bytes are cached in EX_INFO.
+   OFFSET is the offset in bytes from the start of the insn of the value.
+   BYTES is the length of the needed value.
+   Returns 1 for success, 0 for failure.  */
+
+static CGEN_INLINE int
+fill_cache (cd, ex_info, offset, bytes, pc)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     CGEN_EXTRACT_INFO *ex_info;
+     int offset, bytes;
+     bfd_vma pc;
+{
+  /* It's doubtful that the middle part has already been fetched so
+     we don't optimize that case.  kiss.  */
+  unsigned int mask;
+  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+  /* First do a quick check.  */
+  mask = (1 << bytes) - 1;
+  if (((ex_info->valid >> offset) & mask) == mask)
+    return 1;
+
+  /* Search for the first byte we need to read.  */
+  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+    if (! (mask & ex_info->valid))
+      break;
+
+  if (bytes)
+    {
+      int status;
+
+      pc += offset;
+      status = (*info->read_memory_func)
+	(pc, ex_info->insn_bytes + offset, bytes, info);
+
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, pc, info);
+	  return 0;
+	}
+
+      ex_info->valid |= ((1 << bytes) - 1) << offset;
+    }
+
+  return 1;
+}
+
+/* Subroutine of extract_normal.  */
+
+static CGEN_INLINE long
+extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
+     CGEN_CPU_DESC cd;
+     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+     int start,length,word_length;
+     unsigned char *bufp;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+{
+  unsigned long x;
+  int shift;
+#if 0
+  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+#endif
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+   INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+   or sometimes less for cases like the m32r where the base insn size is 32
+   but some insns are 16 bits.
+   ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
+   but for generality we take a bitmask of all of them.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   Returns 1 for success, 0 for failure.  */
+
+/* ??? The return code isn't properly used.  wip.  */
+
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static int
+extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
+		word_length, total_length, pc, valuep)
+     CGEN_CPU_DESC cd;
+#if ! CGEN_INT_INSN_P
+     CGEN_EXTRACT_INFO *ex_info;
+#else
+     CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+#endif
+     CGEN_INSN_INT insn_value;
+     unsigned int attrs;
+     unsigned int word_offset, start, length, word_length, total_length;
+#if ! CGEN_INT_INSN_P
+     bfd_vma pc;
+#else
+     bfd_vma pc ATTRIBUTE_UNUSED;
+#endif
+     long *valuep;
+{
+  long value, mask;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value
+     so give it a standard value of zero.  */
+  if (length == 0)
+    {
+      *valuep = 0;
+      return 1;
+    }
+
+#if 0
+  if (CGEN_INT_INSN_P
+      && word_offset != 0)
+    abort ();
+#endif
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset == 0
+	  && word_length > total_length)
+	word_length = total_length;
+    }
+
+  /* Does the value reside in INSN_VALUE, and at the right alignment?  */
+
+  if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+    {
+      if (CGEN_INSN_LSB0_P)
+	value = insn_value >> ((word_offset + start + 1) - length);
+      else
+	value = insn_value >> (total_length - ( word_offset + start + length));
+    }
+
+#if ! CGEN_INT_INSN_P
+
+  else
+    {
+      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+      if (word_length > 32)
+	abort ();
+
+      if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+	return 0;
+
+      value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+    }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  value &= mask;
+  /* sign extend? */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+      && (value & (1L << (length - 1))))
+    value |= ~mask;
+
+  *valuep = value;
+
+  return 1;
+}
+
+/* Default insn extractor.
+
+   INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+   The extracted fields are stored in FIELDS.
+   EX_INFO is used to handle reading variable length insns.
+   Return the length of the insn in bits, or 0 if no match,
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
+     CGEN_CPU_DESC cd;
+     const CGEN_INSN *insn;
+     CGEN_EXTRACT_INFO *ex_info;
+     CGEN_INSN_INT insn_value;
+     CGEN_FIELDS *fields;
+     bfd_vma pc;
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+  CGEN_INIT_EXTRACT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      int length;
+
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	continue;
+
+      length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+					ex_info, insn_value, fields, pc);
+      if (length <= 0)
+	return length;
+    }
+
+  /* We recognized and successfully extracted this insn.  */
+  return CGEN_INSN_BITSIZE (insn);
+}
+
+/* machine generated code added here */
+
+const char * frv_cgen_insert_operand
+  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.  */
+
+const char *
+frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
+     CGEN_CPU_DESC cd;
+     int opindex;
+     CGEN_FIELDS * fields;
+     CGEN_INSN_BYTES_PTR buffer;
+     bfd_vma pc ATTRIBUTE_UNUSED;
+{
+  const char * errmsg = NULL;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACC40SI :
+      errmsg = insert_normal (cd, fields->f_ACC40Si, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACC40SK :
+      errmsg = insert_normal (cd, fields->f_ACC40Sk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACC40UI :
+      errmsg = insert_normal (cd, fields->f_ACC40Ui, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACC40UK :
+      errmsg = insert_normal (cd, fields->f_ACC40Uk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACCGI :
+      errmsg = insert_normal (cd, fields->f_ACCGi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ACCGK :
+      errmsg = insert_normal (cd, fields->f_ACCGk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CCI :
+      errmsg = insert_normal (cd, fields->f_CCi, 0, 0, 11, 3, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CPRI :
+      errmsg = insert_normal (cd, fields->f_CPRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CPRJ :
+      errmsg = insert_normal (cd, fields->f_CPRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CPRK :
+      errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CRI :
+      errmsg = insert_normal (cd, fields->f_CRi, 0, 0, 14, 3, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CRJ :
+      errmsg = insert_normal (cd, fields->f_CRj, 0, 0, 2, 3, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      errmsg = insert_normal (cd, fields->f_CRj_float, 0, 0, 26, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      {
+        long value = fields->f_CRj_int;
+        value = ((value) - (4));
+        errmsg = insert_normal (cd, value, 0, 0, 26, 2, 32, total_length, buffer);
+      }
+      break;
+    case FRV_OPERAND_CRK :
+      errmsg = insert_normal (cd, fields->f_CRk, 0, 0, 27, 3, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      errmsg = insert_normal (cd, fields->f_FCCi_1, 0, 0, 11, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      errmsg = insert_normal (cd, fields->f_FCCi_2, 0, 0, 26, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      errmsg = insert_normal (cd, fields->f_FCCi_3, 0, 0, 1, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FCCK :
+      errmsg = insert_normal (cd, fields->f_FCCk, 0, 0, 26, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRI :
+      errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRINTI :
+      errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRINTJ :
+      errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRINTK :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRJ :
+      errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRK :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRKHI :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_FRKLO :
+      errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRI :
+      errmsg = insert_normal (cd, fields->f_GRi, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRJ :
+      errmsg = insert_normal (cd, fields->f_GRj, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRK :
+      errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRKHI :
+      errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_GRKLO :
+      errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      errmsg = insert_normal (cd, fields->f_ICCi_1, 0, 0, 11, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      errmsg = insert_normal (cd, fields->f_ICCi_2, 0, 0, 26, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      errmsg = insert_normal (cd, fields->f_ICCi_3, 0, 0, 1, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_LI :
+      errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_AE :
+      errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_CCOND :
+      errmsg = insert_normal (cd, fields->f_ccond, 0, 0, 12, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_COND :
+      errmsg = insert_normal (cd, fields->f_cond, 0, 0, 8, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_D12 :
+      errmsg = insert_normal (cd, fields->f_d12, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_DEBUG :
+      errmsg = insert_normal (cd, fields->f_debug, 0, 0, 25, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_EIR :
+      errmsg = insert_normal (cd, fields->f_eir, 0, 0, 17, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_HINT :
+      errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_LABEL16 :
+      {
+        long value = fields->f_label16;
+        value = ((int) (((value) - (pc))) >> (2));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer);
+      }
+      break;
+    case FRV_OPERAND_LABEL24 :
+      {
+{
+  FLD (f_labelH6) = ((int) (((FLD (f_label24)) - (pc))) >> (20));
+  FLD (f_labelL18) = ((((unsigned int) (((FLD (f_label24)) - (pc))) >> (2))) & (262143));
+}
+        errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_labelL18, 0, 0, 17, 18, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case FRV_OPERAND_LOCK :
+      errmsg = insert_normal (cd, fields->f_lock, 0, 0, 25, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_PACK :
+      errmsg = insert_normal (cd, fields->f_pack, 0, 0, 31, 1, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S10 :
+      errmsg = insert_normal (cd, fields->f_s10, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 10, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S12 :
+      errmsg = insert_normal (cd, fields->f_d12, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S16 :
+      errmsg = insert_normal (cd, fields->f_s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S5 :
+      errmsg = insert_normal (cd, fields->f_s5, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 5, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S6 :
+      errmsg = insert_normal (cd, fields->f_s6, 0|(1<<CGEN_IFLD_SIGNED), 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_S6_1 :
+      errmsg = insert_normal (cd, fields->f_s6_1, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_SLO16 :
+      errmsg = insert_normal (cd, fields->f_s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_SPR :
+      {
+{
+  FLD (f_spr_h) = ((unsigned int) (FLD (f_spr)) >> (6));
+  FLD (f_spr_l) = ((FLD (f_spr)) & (63));
+}
+        errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_spr_l, 0, 0, 17, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case FRV_OPERAND_U12 :
+      {
+{
+  FLD (f_u12_h) = ((int) (FLD (f_u12)) >> (6));
+  FLD (f_u12_l) = ((FLD (f_u12)) & (63));
+}
+        errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_u12_l, 0, 0, 5, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case FRV_OPERAND_U16 :
+      errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_U6 :
+      errmsg = insert_normal (cd, fields->f_u6, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_UHI16 :
+      errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer);
+      break;
+    case FRV_OPERAND_ULO16 :
+      errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+	       opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+int frv_cgen_extract_operand
+  PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+           CGEN_FIELDS *, bfd_vma));
+
+/* Main entry point for operand extraction.
+   The result is <= 0 for error, >0 for success.
+   ??? Actual values aren't well defined right now.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+int
+frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
+     CGEN_CPU_DESC cd;
+     int opindex;
+     CGEN_EXTRACT_INFO *ex_info;
+     CGEN_INSN_INT insn_value;
+     CGEN_FIELDS * fields;
+     bfd_vma pc;
+{
+  /* Assume success (for those operands that are nops).  */
+  int length = 1;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A);
+      break;
+    case FRV_OPERAND_ACC40SI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Si);
+      break;
+    case FRV_OPERAND_ACC40SK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Sk);
+      break;
+    case FRV_OPERAND_ACC40UI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Ui);
+      break;
+    case FRV_OPERAND_ACC40UK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Uk);
+      break;
+    case FRV_OPERAND_ACCGI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACCGi);
+      break;
+    case FRV_OPERAND_ACCGK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACCGk);
+      break;
+    case FRV_OPERAND_CCI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 32, total_length, pc, & fields->f_CCi);
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk);
+      break;
+    case FRV_OPERAND_CPRI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_CPRi);
+      break;
+    case FRV_OPERAND_CPRJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_CPRj);
+      break;
+    case FRV_OPERAND_CPRK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk);
+      break;
+    case FRV_OPERAND_CRI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_CRi);
+      break;
+    case FRV_OPERAND_CRJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_CRj);
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_CRj_float);
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & value);
+        value = ((value) + (4));
+        fields->f_CRj_int = value;
+      }
+      break;
+    case FRV_OPERAND_CRK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 3, 32, total_length, pc, & fields->f_CRk);
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_FCCi_1);
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCi_2);
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_FCCi_3);
+      break;
+    case FRV_OPERAND_FCCK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCk);
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRINTI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi);
+      break;
+    case FRV_OPERAND_FRINTJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRINTK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj);
+      break;
+    case FRV_OPERAND_FRK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRKHI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_FRKLO :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk);
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_GRi);
+      break;
+    case FRV_OPERAND_GRJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_GRj);
+      break;
+    case FRV_OPERAND_GRK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRKHI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_GRKLO :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk);
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_ICCi_1);
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_ICCi_2);
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_ICCi_3);
+      break;
+    case FRV_OPERAND_LI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI);
+      break;
+    case FRV_OPERAND_AE :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae);
+      break;
+    case FRV_OPERAND_CCOND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 1, 32, total_length, pc, & fields->f_ccond);
+      break;
+    case FRV_OPERAND_COND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_cond);
+      break;
+    case FRV_OPERAND_D12 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, pc, & fields->f_d12);
+      break;
+    case FRV_OPERAND_DEBUG :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_debug);
+      break;
+    case FRV_OPERAND_EIR :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_eir);
+      break;
+    case FRV_OPERAND_HINT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint);
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint);
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint);
+      break;
+    case FRV_OPERAND_LABEL16 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value);
+        value = ((((value) << (2))) + (pc));
+        fields->f_label16 = value;
+      }
+      break;
+    case FRV_OPERAND_LABEL24 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, pc, & fields->f_labelH6);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18);
+        if (length <= 0) break;
+{
+  FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc));
+}
+      }
+      break;
+    case FRV_OPERAND_LOCK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_lock);
+      break;
+    case FRV_OPERAND_PACK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 1, 32, total_length, pc, & fields->f_pack);
+      break;
+    case FRV_OPERAND_S10 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 10, 32, total_length, pc, & fields->f_s10);
+      break;
+    case FRV_OPERAND_S12 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, pc, & fields->f_d12);
+      break;
+    case FRV_OPERAND_S16 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_s16);
+      break;
+    case FRV_OPERAND_S5 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 5, 32, total_length, pc, & fields->f_s5);
+      break;
+    case FRV_OPERAND_S6 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 5, 6, 32, total_length, pc, & fields->f_s6);
+      break;
+    case FRV_OPERAND_S6_1 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 6, 32, total_length, pc, & fields->f_s6_1);
+      break;
+    case FRV_OPERAND_SLO16 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_s16);
+      break;
+    case FRV_OPERAND_SPR :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_spr_h);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_spr_l);
+        if (length <= 0) break;
+{
+  FLD (f_spr) = ((((FLD (f_spr_h)) << (6))) | (FLD (f_spr_l)));
+}
+      }
+      break;
+    case FRV_OPERAND_U12 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, pc, & fields->f_u12_h);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l);
+        if (length <= 0) break;
+{
+  FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l)));
+}
+      }
+      break;
+    case FRV_OPERAND_U16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16);
+      break;
+    case FRV_OPERAND_U6 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u6);
+      break;
+    case FRV_OPERAND_UHI16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16);
+      break;
+    case FRV_OPERAND_ULO16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+	       opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+cgen_insert_fn * const frv_cgen_insert_handlers[] = 
+{
+  insert_insn_normal,
+};
+
+cgen_extract_fn * const frv_cgen_extract_handlers[] = 
+{
+  extract_insn_normal,
+};
+
+int frv_cgen_get_int_operand
+  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+bfd_vma frv_cgen_get_vma_operand
+  PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they return.
+   TODO: floating point, inlining support, remove cases where result type
+   not appropriate.  */
+
+int
+frv_cgen_get_int_operand (cd, opindex, fields)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     int opindex;
+     const CGEN_FIELDS * fields;
+{
+  int value;
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      value = fields->f_A;
+      break;
+    case FRV_OPERAND_ACC40SI :
+      value = fields->f_ACC40Si;
+      break;
+    case FRV_OPERAND_ACC40SK :
+      value = fields->f_ACC40Sk;
+      break;
+    case FRV_OPERAND_ACC40UI :
+      value = fields->f_ACC40Ui;
+      break;
+    case FRV_OPERAND_ACC40UK :
+      value = fields->f_ACC40Uk;
+      break;
+    case FRV_OPERAND_ACCGI :
+      value = fields->f_ACCGi;
+      break;
+    case FRV_OPERAND_ACCGK :
+      value = fields->f_ACCGk;
+      break;
+    case FRV_OPERAND_CCI :
+      value = fields->f_CCi;
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      value = fields->f_CPRk;
+      break;
+    case FRV_OPERAND_CPRI :
+      value = fields->f_CPRi;
+      break;
+    case FRV_OPERAND_CPRJ :
+      value = fields->f_CPRj;
+      break;
+    case FRV_OPERAND_CPRK :
+      value = fields->f_CPRk;
+      break;
+    case FRV_OPERAND_CRI :
+      value = fields->f_CRi;
+      break;
+    case FRV_OPERAND_CRJ :
+      value = fields->f_CRj;
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      value = fields->f_CRj_float;
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      value = fields->f_CRj_int;
+      break;
+    case FRV_OPERAND_CRK :
+      value = fields->f_CRk;
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      value = fields->f_FCCi_1;
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      value = fields->f_FCCi_2;
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      value = fields->f_FCCi_3;
+      break;
+    case FRV_OPERAND_FCCK :
+      value = fields->f_FCCk;
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRINTI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRINTJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRINTK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRKHI :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRKLO :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRI :
+      value = fields->f_GRi;
+      break;
+    case FRV_OPERAND_GRJ :
+      value = fields->f_GRj;
+      break;
+    case FRV_OPERAND_GRK :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRKHI :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRKLO :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      value = fields->f_ICCi_1;
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      value = fields->f_ICCi_2;
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      value = fields->f_ICCi_3;
+      break;
+    case FRV_OPERAND_LI :
+      value = fields->f_LI;
+      break;
+    case FRV_OPERAND_AE :
+      value = fields->f_ae;
+      break;
+    case FRV_OPERAND_CCOND :
+      value = fields->f_ccond;
+      break;
+    case FRV_OPERAND_COND :
+      value = fields->f_cond;
+      break;
+    case FRV_OPERAND_D12 :
+      value = fields->f_d12;
+      break;
+    case FRV_OPERAND_DEBUG :
+      value = fields->f_debug;
+      break;
+    case FRV_OPERAND_EIR :
+      value = fields->f_eir;
+      break;
+    case FRV_OPERAND_HINT :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_LABEL16 :
+      value = fields->f_label16;
+      break;
+    case FRV_OPERAND_LABEL24 :
+      value = fields->f_label24;
+      break;
+    case FRV_OPERAND_LOCK :
+      value = fields->f_lock;
+      break;
+    case FRV_OPERAND_PACK :
+      value = fields->f_pack;
+      break;
+    case FRV_OPERAND_S10 :
+      value = fields->f_s10;
+      break;
+    case FRV_OPERAND_S12 :
+      value = fields->f_d12;
+      break;
+    case FRV_OPERAND_S16 :
+      value = fields->f_s16;
+      break;
+    case FRV_OPERAND_S5 :
+      value = fields->f_s5;
+      break;
+    case FRV_OPERAND_S6 :
+      value = fields->f_s6;
+      break;
+    case FRV_OPERAND_S6_1 :
+      value = fields->f_s6_1;
+      break;
+    case FRV_OPERAND_SLO16 :
+      value = fields->f_s16;
+      break;
+    case FRV_OPERAND_SPR :
+      value = fields->f_spr;
+      break;
+    case FRV_OPERAND_U12 :
+      value = fields->f_u12;
+      break;
+    case FRV_OPERAND_U16 :
+      value = fields->f_u16;
+      break;
+    case FRV_OPERAND_U6 :
+      value = fields->f_u6;
+      break;
+    case FRV_OPERAND_UHI16 :
+      value = fields->f_u16;
+      break;
+    case FRV_OPERAND_ULO16 :
+      value = fields->f_u16;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+bfd_vma
+frv_cgen_get_vma_operand (cd, opindex, fields)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     int opindex;
+     const CGEN_FIELDS * fields;
+{
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      value = fields->f_A;
+      break;
+    case FRV_OPERAND_ACC40SI :
+      value = fields->f_ACC40Si;
+      break;
+    case FRV_OPERAND_ACC40SK :
+      value = fields->f_ACC40Sk;
+      break;
+    case FRV_OPERAND_ACC40UI :
+      value = fields->f_ACC40Ui;
+      break;
+    case FRV_OPERAND_ACC40UK :
+      value = fields->f_ACC40Uk;
+      break;
+    case FRV_OPERAND_ACCGI :
+      value = fields->f_ACCGi;
+      break;
+    case FRV_OPERAND_ACCGK :
+      value = fields->f_ACCGk;
+      break;
+    case FRV_OPERAND_CCI :
+      value = fields->f_CCi;
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      value = fields->f_CPRk;
+      break;
+    case FRV_OPERAND_CPRI :
+      value = fields->f_CPRi;
+      break;
+    case FRV_OPERAND_CPRJ :
+      value = fields->f_CPRj;
+      break;
+    case FRV_OPERAND_CPRK :
+      value = fields->f_CPRk;
+      break;
+    case FRV_OPERAND_CRI :
+      value = fields->f_CRi;
+      break;
+    case FRV_OPERAND_CRJ :
+      value = fields->f_CRj;
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      value = fields->f_CRj_float;
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      value = fields->f_CRj_int;
+      break;
+    case FRV_OPERAND_CRK :
+      value = fields->f_CRk;
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      value = fields->f_FCCi_1;
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      value = fields->f_FCCi_2;
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      value = fields->f_FCCi_3;
+      break;
+    case FRV_OPERAND_FCCK :
+      value = fields->f_FCCk;
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRINTI :
+      value = fields->f_FRi;
+      break;
+    case FRV_OPERAND_FRINTJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRINTK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRJ :
+      value = fields->f_FRj;
+      break;
+    case FRV_OPERAND_FRK :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRKHI :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_FRKLO :
+      value = fields->f_FRk;
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRI :
+      value = fields->f_GRi;
+      break;
+    case FRV_OPERAND_GRJ :
+      value = fields->f_GRj;
+      break;
+    case FRV_OPERAND_GRK :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRKHI :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_GRKLO :
+      value = fields->f_GRk;
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      value = fields->f_ICCi_1;
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      value = fields->f_ICCi_2;
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      value = fields->f_ICCi_3;
+      break;
+    case FRV_OPERAND_LI :
+      value = fields->f_LI;
+      break;
+    case FRV_OPERAND_AE :
+      value = fields->f_ae;
+      break;
+    case FRV_OPERAND_CCOND :
+      value = fields->f_ccond;
+      break;
+    case FRV_OPERAND_COND :
+      value = fields->f_cond;
+      break;
+    case FRV_OPERAND_D12 :
+      value = fields->f_d12;
+      break;
+    case FRV_OPERAND_DEBUG :
+      value = fields->f_debug;
+      break;
+    case FRV_OPERAND_EIR :
+      value = fields->f_eir;
+      break;
+    case FRV_OPERAND_HINT :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      value = fields->f_hint;
+      break;
+    case FRV_OPERAND_LABEL16 :
+      value = fields->f_label16;
+      break;
+    case FRV_OPERAND_LABEL24 :
+      value = fields->f_label24;
+      break;
+    case FRV_OPERAND_LOCK :
+      value = fields->f_lock;
+      break;
+    case FRV_OPERAND_PACK :
+      value = fields->f_pack;
+      break;
+    case FRV_OPERAND_S10 :
+      value = fields->f_s10;
+      break;
+    case FRV_OPERAND_S12 :
+      value = fields->f_d12;
+      break;
+    case FRV_OPERAND_S16 :
+      value = fields->f_s16;
+      break;
+    case FRV_OPERAND_S5 :
+      value = fields->f_s5;
+      break;
+    case FRV_OPERAND_S6 :
+      value = fields->f_s6;
+      break;
+    case FRV_OPERAND_S6_1 :
+      value = fields->f_s6_1;
+      break;
+    case FRV_OPERAND_SLO16 :
+      value = fields->f_s16;
+      break;
+    case FRV_OPERAND_SPR :
+      value = fields->f_spr;
+      break;
+    case FRV_OPERAND_U12 :
+      value = fields->f_u12;
+      break;
+    case FRV_OPERAND_U16 :
+      value = fields->f_u16;
+      break;
+    case FRV_OPERAND_U6 :
+      value = fields->f_u6;
+      break;
+    case FRV_OPERAND_UHI16 :
+      value = fields->f_u16;
+      break;
+    case FRV_OPERAND_ULO16 :
+      value = fields->f_u16;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+void frv_cgen_set_int_operand
+  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
+void frv_cgen_set_vma_operand
+  PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they accept.
+   TODO: floating point, inlining support, remove cases where argument type
+   not appropriate.  */
+
+void
+frv_cgen_set_int_operand (cd, opindex, fields, value)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     int opindex;
+     CGEN_FIELDS * fields;
+     int value;
+{
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      fields->f_A = value;
+      break;
+    case FRV_OPERAND_ACC40SI :
+      fields->f_ACC40Si = value;
+      break;
+    case FRV_OPERAND_ACC40SK :
+      fields->f_ACC40Sk = value;
+      break;
+    case FRV_OPERAND_ACC40UI :
+      fields->f_ACC40Ui = value;
+      break;
+    case FRV_OPERAND_ACC40UK :
+      fields->f_ACC40Uk = value;
+      break;
+    case FRV_OPERAND_ACCGI :
+      fields->f_ACCGi = value;
+      break;
+    case FRV_OPERAND_ACCGK :
+      fields->f_ACCGk = value;
+      break;
+    case FRV_OPERAND_CCI :
+      fields->f_CCi = value;
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      fields->f_CPRk = value;
+      break;
+    case FRV_OPERAND_CPRI :
+      fields->f_CPRi = value;
+      break;
+    case FRV_OPERAND_CPRJ :
+      fields->f_CPRj = value;
+      break;
+    case FRV_OPERAND_CPRK :
+      fields->f_CPRk = value;
+      break;
+    case FRV_OPERAND_CRI :
+      fields->f_CRi = value;
+      break;
+    case FRV_OPERAND_CRJ :
+      fields->f_CRj = value;
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      fields->f_CRj_float = value;
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      fields->f_CRj_int = value;
+      break;
+    case FRV_OPERAND_CRK :
+      fields->f_CRk = value;
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      fields->f_FCCi_1 = value;
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      fields->f_FCCi_2 = value;
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      fields->f_FCCi_3 = value;
+      break;
+    case FRV_OPERAND_FCCK :
+      fields->f_FCCk = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRINTI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRINTJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRINTK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRKHI :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRKLO :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRI :
+      fields->f_GRi = value;
+      break;
+    case FRV_OPERAND_GRJ :
+      fields->f_GRj = value;
+      break;
+    case FRV_OPERAND_GRK :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRKHI :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRKLO :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      fields->f_ICCi_1 = value;
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      fields->f_ICCi_2 = value;
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      fields->f_ICCi_3 = value;
+      break;
+    case FRV_OPERAND_LI :
+      fields->f_LI = value;
+      break;
+    case FRV_OPERAND_AE :
+      fields->f_ae = value;
+      break;
+    case FRV_OPERAND_CCOND :
+      fields->f_ccond = value;
+      break;
+    case FRV_OPERAND_COND :
+      fields->f_cond = value;
+      break;
+    case FRV_OPERAND_D12 :
+      fields->f_d12 = value;
+      break;
+    case FRV_OPERAND_DEBUG :
+      fields->f_debug = value;
+      break;
+    case FRV_OPERAND_EIR :
+      fields->f_eir = value;
+      break;
+    case FRV_OPERAND_HINT :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_LABEL16 :
+      fields->f_label16 = value;
+      break;
+    case FRV_OPERAND_LABEL24 :
+      fields->f_label24 = value;
+      break;
+    case FRV_OPERAND_LOCK :
+      fields->f_lock = value;
+      break;
+    case FRV_OPERAND_PACK :
+      fields->f_pack = value;
+      break;
+    case FRV_OPERAND_S10 :
+      fields->f_s10 = value;
+      break;
+    case FRV_OPERAND_S12 :
+      fields->f_d12 = value;
+      break;
+    case FRV_OPERAND_S16 :
+      fields->f_s16 = value;
+      break;
+    case FRV_OPERAND_S5 :
+      fields->f_s5 = value;
+      break;
+    case FRV_OPERAND_S6 :
+      fields->f_s6 = value;
+      break;
+    case FRV_OPERAND_S6_1 :
+      fields->f_s6_1 = value;
+      break;
+    case FRV_OPERAND_SLO16 :
+      fields->f_s16 = value;
+      break;
+    case FRV_OPERAND_SPR :
+      fields->f_spr = value;
+      break;
+    case FRV_OPERAND_U12 :
+      fields->f_u12 = value;
+      break;
+    case FRV_OPERAND_U16 :
+      fields->f_u16 = value;
+      break;
+    case FRV_OPERAND_U6 :
+      fields->f_u6 = value;
+      break;
+    case FRV_OPERAND_UHI16 :
+      fields->f_u16 = value;
+      break;
+    case FRV_OPERAND_ULO16 :
+      fields->f_u16 = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+void
+frv_cgen_set_vma_operand (cd, opindex, fields, value)
+     CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+     int opindex;
+     CGEN_FIELDS * fields;
+     bfd_vma value;
+{
+  switch (opindex)
+    {
+    case FRV_OPERAND_A :
+      fields->f_A = value;
+      break;
+    case FRV_OPERAND_ACC40SI :
+      fields->f_ACC40Si = value;
+      break;
+    case FRV_OPERAND_ACC40SK :
+      fields->f_ACC40Sk = value;
+      break;
+    case FRV_OPERAND_ACC40UI :
+      fields->f_ACC40Ui = value;
+      break;
+    case FRV_OPERAND_ACC40UK :
+      fields->f_ACC40Uk = value;
+      break;
+    case FRV_OPERAND_ACCGI :
+      fields->f_ACCGi = value;
+      break;
+    case FRV_OPERAND_ACCGK :
+      fields->f_ACCGk = value;
+      break;
+    case FRV_OPERAND_CCI :
+      fields->f_CCi = value;
+      break;
+    case FRV_OPERAND_CPRDOUBLEK :
+      fields->f_CPRk = value;
+      break;
+    case FRV_OPERAND_CPRI :
+      fields->f_CPRi = value;
+      break;
+    case FRV_OPERAND_CPRJ :
+      fields->f_CPRj = value;
+      break;
+    case FRV_OPERAND_CPRK :
+      fields->f_CPRk = value;
+      break;
+    case FRV_OPERAND_CRI :
+      fields->f_CRi = value;
+      break;
+    case FRV_OPERAND_CRJ :
+      fields->f_CRj = value;
+      break;
+    case FRV_OPERAND_CRJ_FLOAT :
+      fields->f_CRj_float = value;
+      break;
+    case FRV_OPERAND_CRJ_INT :
+      fields->f_CRj_int = value;
+      break;
+    case FRV_OPERAND_CRK :
+      fields->f_CRk = value;
+      break;
+    case FRV_OPERAND_FCCI_1 :
+      fields->f_FCCi_1 = value;
+      break;
+    case FRV_OPERAND_FCCI_2 :
+      fields->f_FCCi_2 = value;
+      break;
+    case FRV_OPERAND_FCCI_3 :
+      fields->f_FCCi_3 = value;
+      break;
+    case FRV_OPERAND_FCCK :
+      fields->f_FCCk = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRDOUBLEK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRINTI :
+      fields->f_FRi = value;
+      break;
+    case FRV_OPERAND_FRINTJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRINTK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRJ :
+      fields->f_FRj = value;
+      break;
+    case FRV_OPERAND_FRK :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRKHI :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_FRKLO :
+      fields->f_FRk = value;
+      break;
+    case FRV_OPERAND_GRDOUBLEK :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRI :
+      fields->f_GRi = value;
+      break;
+    case FRV_OPERAND_GRJ :
+      fields->f_GRj = value;
+      break;
+    case FRV_OPERAND_GRK :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRKHI :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_GRKLO :
+      fields->f_GRk = value;
+      break;
+    case FRV_OPERAND_ICCI_1 :
+      fields->f_ICCi_1 = value;
+      break;
+    case FRV_OPERAND_ICCI_2 :
+      fields->f_ICCi_2 = value;
+      break;
+    case FRV_OPERAND_ICCI_3 :
+      fields->f_ICCi_3 = value;
+      break;
+    case FRV_OPERAND_LI :
+      fields->f_LI = value;
+      break;
+    case FRV_OPERAND_AE :
+      fields->f_ae = value;
+      break;
+    case FRV_OPERAND_CCOND :
+      fields->f_ccond = value;
+      break;
+    case FRV_OPERAND_COND :
+      fields->f_cond = value;
+      break;
+    case FRV_OPERAND_D12 :
+      fields->f_d12 = value;
+      break;
+    case FRV_OPERAND_DEBUG :
+      fields->f_debug = value;
+      break;
+    case FRV_OPERAND_EIR :
+      fields->f_eir = value;
+      break;
+    case FRV_OPERAND_HINT :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_HINT_NOT_TAKEN :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_HINT_TAKEN :
+      fields->f_hint = value;
+      break;
+    case FRV_OPERAND_LABEL16 :
+      fields->f_label16 = value;
+      break;
+    case FRV_OPERAND_LABEL24 :
+      fields->f_label24 = value;
+      break;
+    case FRV_OPERAND_LOCK :
+      fields->f_lock = value;
+      break;
+    case FRV_OPERAND_PACK :
+      fields->f_pack = value;
+      break;
+    case FRV_OPERAND_S10 :
+      fields->f_s10 = value;
+      break;
+    case FRV_OPERAND_S12 :
+      fields->f_d12 = value;
+      break;
+    case FRV_OPERAND_S16 :
+      fields->f_s16 = value;
+      break;
+    case FRV_OPERAND_S5 :
+      fields->f_s5 = value;
+      break;
+    case FRV_OPERAND_S6 :
+      fields->f_s6 = value;
+      break;
+    case FRV_OPERAND_S6_1 :
+      fields->f_s6_1 = value;
+      break;
+    case FRV_OPERAND_SLO16 :
+      fields->f_s16 = value;
+      break;
+    case FRV_OPERAND_SPR :
+      fields->f_spr = value;
+      break;
+    case FRV_OPERAND_U12 :
+      fields->f_u12 = value;
+      break;
+    case FRV_OPERAND_U16 :
+      fields->f_u16 = value;
+      break;
+    case FRV_OPERAND_U6 :
+      fields->f_u6 = value;
+      break;
+    case FRV_OPERAND_UHI16 :
+      fields->f_u16 = value;
+      break;
+    case FRV_OPERAND_ULO16 :
+      fields->f_u16 = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+/* Function to call before using the instruction builder tables.  */
+
+void
+frv_cgen_init_ibld_table (cd)
+     CGEN_CPU_DESC cd;
+{
+  cd->insert_handlers = & frv_cgen_insert_handlers[0];
+  cd->extract_handlers = & frv_cgen_extract_handlers[0];
+
+  cd->insert_operand = frv_cgen_insert_operand;
+  cd->extract_operand = frv_cgen_extract_operand;
+
+  cd->get_int_operand = frv_cgen_get_int_operand;
+  cd->set_int_operand = frv_cgen_set_int_operand;
+  cd->get_vma_operand = frv_cgen_get_vma_operand;
+  cd->set_vma_operand = frv_cgen_set_vma_operand;
+}

--- /dev/null
+++ b/opcodes/frv-opc.c
@@ -0,0 +1,5842 @@
+/* Instruction opcode table for frv.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "frv-desc.h"
+#include "frv-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+#include "elf/frv.h"
+
+static int match_unit
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE));
+static int match_vliw
+  PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int));
+static VLIW_COMBO * add_next_to_vliw
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int find_major_in_vliw
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr400_check_insn_major_constraints
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr500_check_insn_major_constraints
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int check_insn_major_constraints
+  PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+
+int
+frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
+	return 1; /* is a branch */
+      break;
+    default:
+      if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
+	return 1; /* is a branch */
+      break;
+    }
+
+  return 0; /* not a branch */
+}
+
+int
+frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      return 0; /* No float insns */
+    default:
+      if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
+	return 1; /* is a float insn */
+      break;
+    }
+
+  return 0; /* not a branch */
+}
+
+int
+frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
+{
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
+	return 1; /* is a media insn */
+      break;
+    default:
+      if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
+	return 1; /* is a media insn */
+      break;
+    }
+
+  return 0; /* not a branch */
+}
+
+int
+frv_is_branch_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+			   bfd_mach_fr400))
+    return 1;
+  if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+			   bfd_mach_fr500))
+    return 1;
+
+  return 0;
+}
+
+int
+frv_is_float_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+			  bfd_mach_fr400))
+    return 1;
+  if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+			  bfd_mach_fr500))
+    return 1;
+
+  return 0;
+}
+
+int
+frv_is_media_insn (const CGEN_INSN *insn)
+{
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
+			  bfd_mach_fr400))
+    return 1;
+  if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
+			  bfd_mach_fr500))
+    return 1;
+
+  return 0;
+}
+
+/* This table represents the allowable packing for vliw insns for the fr400.
+   The fr400 has only 2 vliw slots. Represent this by not allowing any insns
+   in slots 2 and 3.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr400_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3    */
+  {  UNIT_I0,    UNIT_I1,    UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_I0,    UNIT_B0,    UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_B0,    UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  }
+};
+
+/* This table represents the allowable packing for vliw insns for the fr500.
+   Subsets of any given row are also allowed.  */
+static VLIW_COMBO fr500_allowed_vliw[] =
+{
+  /*  slot0       slot1       slot2       slot3    */
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_FM1  },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_I1,    UNIT_B0   },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_FM1,   UNIT_B0   },
+  {  UNIT_I0,    UNIT_FM0,   UNIT_B0,    UNIT_B1   },
+  {  UNIT_I0,    UNIT_I1,    UNIT_B0,    UNIT_B1   },
+  {  UNIT_I0,    UNIT_B0,    UNIT_B1,    UNIT_NIL  },
+  {  UNIT_FM0,   UNIT_FM1,   UNIT_B0,    UNIT_B1   },
+  {  UNIT_FM0,   UNIT_B0,    UNIT_B1,    UNIT_NIL  },
+  {  UNIT_B0,    UNIT_B1,    UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_C,     UNIT_NIL,   UNIT_NIL,   UNIT_NIL  },
+  {  UNIT_NIL,   UNIT_NIL,   UNIT_NIL,   UNIT_NIL  }
+};
+
+/* Some insns are assigned specialized implementation units which map to
+   different actual implementation units on different machines.  These
+   tables perform that mapping.  */
+static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* B0       */     UNIT_B0,  /* branches only in B0 unit.  */
+/* B1       */     UNIT_B0,
+/* B01      */     UNIT_B0,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I0,  /* multiply and divide only in I0 unit.  */
+/* LOAD     */     UNIT_I0   /* load                only in I0 unit.  */
+};
+
+static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
+{
+/* unit in insn    actual unit */
+/* NIL      */     UNIT_NIL,
+/* I0       */     UNIT_I0,
+/* I1       */     UNIT_I1,
+/* I01      */     UNIT_I01, 
+/* FM0      */     UNIT_FM0,
+/* FM1      */     UNIT_FM1,
+/* FM01     */     UNIT_FM01,
+/* B0       */     UNIT_B0,
+/* B1       */     UNIT_B1,
+/* B01      */     UNIT_B01,
+/* C        */     UNIT_C,
+/* MULT-DIV */     UNIT_I01, /* multiply and divide in I0 or I1 unit.  */
+/* LOAD     */     UNIT_I01  /* load                in I0 or I1 unit.  */
+};
+
+void
+frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
+{
+  vliw->next_slot = 0;
+  vliw->constraint_violation = 0;
+  vliw->mach = mach;
+  vliw->elf_flags = elf_flags;
+
+  switch (mach)
+    {
+    case bfd_mach_fr400:
+      vliw->current_vliw = fr400_allowed_vliw;
+      vliw->unit_mapping = fr400_unit_mapping;
+      break;
+    default:
+      vliw->current_vliw = fr500_allowed_vliw;
+      vliw->unit_mapping = fr500_unit_mapping;
+      break;
+    }
+}
+
+/* Return 1 if unit1 is a match for unit2.
+   Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
+   *_allowed_vliw tables above.  */
+static int
+match_unit (FRV_VLIW *vliw,
+	    CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
+{
+  /* Map any specialized implementation units to actual ones.  */
+  unit1 = vliw->unit_mapping[unit1];
+
+  if (unit1 == unit2)
+    return 1;
+  if (unit1 < unit2)
+    return 0;
+
+  switch (unit1)
+    {
+    case UNIT_I01:
+    case UNIT_FM01:
+    case UNIT_B01:
+      /* The 01 versions of these units are within 2 enums of the 0 or 1
+	 versions.  */
+      if (unit1 - unit2 <= 2)
+	return 1;
+      break;
+    default:
+      break;
+    }
+
+  return 0;
+}
+
+/* Return 1 if the vliws match, 0 otherwise.  */
+
+static int
+match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
+{
+  int i;
+
+  for (i = 0; i < vliw_size; ++i)
+    {
+      if ((*vliw1)[i] != (*vliw2)[i])
+	return 0;
+    }
+
+  return 1;
+}
+
+/* Find the next vliw vliw in the table that can accomodate the new insn.
+   If one is found then return it. Otherwise return NULL.  */
+
+static VLIW_COMBO *
+add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
+{
+  int           next    = vliw->next_slot;
+  VLIW_COMBO    *current = vliw->current_vliw;
+  VLIW_COMBO    *potential;
+
+  if (next <= 0)
+    abort (); /* Should never happen */
+
+  /* The table is sorted by units allowed within slots, so vliws with
+     identical starting sequences are together.  */
+  potential = current;
+  do
+    {
+      if (match_unit (vliw, unit, (*potential)[next]))
+	return potential;
+      ++potential;
+    }
+  while (match_vliw (potential, current, next));
+
+  return NULL;
+}
+
+/* Look for the given major insn type in the given vliw. Return 1 if found,
+   return 0 otherwise.  */
+
+static int
+find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
+{
+  int i;
+
+  for (i = 0; i < vliw->next_slot; ++i)
+    if (vliw->major[i] == major)
+      return 1;
+
+  return 0;
+}
+
+/* Check for constraints between the insns in the vliw due to major insn
+   types.  */
+
+static int
+fr400_check_insn_major_constraints (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+  /* In the cpu file, all media insns are represented as being allowed in
+     both media units. This makes it easier since this is the case for fr500.
+     Catch the invalid combinations here.  Insns of major class FR400_MAJOR_M_2
+     cannot coexist with any other media insn in a vliw.  */
+  switch (major)
+    {
+    case FR400_MAJOR_M_2:
+      return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
+	&&   ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
+    default:
+      break;
+    }
+  return 1;
+}
+
+static int
+fr500_check_insn_major_constraints (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+  /* TODO: A table might be faster for some of the more complex instances
+     here.  */
+  switch (major)
+    {
+    case FR500_MAJOR_I_1:
+    case FR500_MAJOR_I_4:
+    case FR500_MAJOR_I_5:
+    case FR500_MAJOR_I_6:
+    case FR500_MAJOR_B_1:
+    case FR500_MAJOR_B_2:
+    case FR500_MAJOR_B_3:
+    case FR500_MAJOR_B_4:
+    case FR500_MAJOR_B_5:
+    case FR500_MAJOR_B_6:
+    case FR500_MAJOR_F_4:
+    case FR500_MAJOR_F_8:
+    case FR500_MAJOR_M_8:
+      return 1; /* OK */
+    case FR500_MAJOR_I_2:
+      /* Cannot coexist with I-3 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
+    case FR500_MAJOR_I_3:
+      /* Cannot coexist with I-2 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2);
+    case FR500_MAJOR_F_1:
+    case FR500_MAJOR_F_2:
+      /* Cannot coexist with F-5, F-6, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_3:
+      /* Cannot coexist with F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_5:
+      /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_6:
+      /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_F_7:
+      /* Cannot coexist with F-3, F-5, F-7, or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_1:
+      /* Cannot coexist with M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_2:
+    case FR500_MAJOR_M_3:
+      /* Cannot coexist with M-5, M-6 or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_4:
+      /* Cannot coexist with M-6 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6);
+    case FR500_MAJOR_M_5:
+      /* Cannot coexist with M-2, M-3, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_6:
+      /* Cannot coexist with M-2, M-3, M-4, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_4)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7);
+    case FR500_MAJOR_M_7:
+      /* Cannot coexist with M-1, M-2, M-3, M-5, M-6  or M-7 insn.  */
+      return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_3)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_M_7)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_1)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_2)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_3)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_5)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_6)
+	&&   ! find_major_in_vliw (vliw, FR500_MAJOR_F_7);
+    default:
+      abort ();
+      break;
+    }
+  return 1;
+}
+
+static int
+check_insn_major_constraints (
+  FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+  int rc;
+  switch (vliw->mach)
+    {
+    case bfd_mach_fr400:
+      rc = fr400_check_insn_major_constraints (vliw, major);
+      break;
+    default:
+      rc = fr500_check_insn_major_constraints (vliw, major);
+      break;
+    }
+  return rc;
+}
+
+/* Add in insn to the VLIW vliw if possible. Return 0 if successful,
+   non-zero otherwise.  */
+int
+frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
+{
+  int index;
+  CGEN_ATTR_VALUE_TYPE major;
+  CGEN_ATTR_VALUE_TYPE unit;
+  VLIW_COMBO *new_vliw;
+
+  if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
+    return 1;
+
+  index = vliw->next_slot;
+  if (index >= FRV_VLIW_SIZE)
+    return 1;
+
+  unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT);
+  if (unit == UNIT_NIL)
+    abort (); /* no UNIT specified for this insn in frv.cpu  */
+
+  if (vliw->mach == bfd_mach_fr400)
+    major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
+  else
+    major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR);
+
+  if (index <= 0)
+    {
+      /* Any insn can be added to slot 0.  */
+      while (! match_unit (vliw, unit, (*vliw->current_vliw)[0]))
+	++vliw->current_vliw;
+      vliw->major[0] = major;
+      vliw->next_slot = 1;
+      return 0;
+    }
+
+  /* If there are already insns in the vliw(s) check to see that
+     this one can be added.  Do this by finding an allowable vliw
+     combination that can accept the new insn.  */
+  if (! (vliw->elf_flags & EF_FRV_NOPACK))
+    {
+      new_vliw = add_next_to_vliw (vliw, unit);
+      if (new_vliw && check_insn_major_constraints (vliw, major))
+	{
+	  vliw->current_vliw = new_vliw;
+	  vliw->major[index] = major;
+	  vliw->next_slot++;
+	  return 0;
+	}
+
+      /* The frv machine supports all packing conbinations.  If we fail,
+	 to add the insn, then it could not be handled as if it was the fr500.
+	 Just return as if it was handled ok.  */
+      if (vliw->mach == bfd_mach_frv)
+	return 0;
+    }
+
+  vliw->constraint_violation = 1;
+  return 1;
+}
+
+int
+spr_valid (regno)
+     long regno;
+{
+  if (regno < 0)     return 0;
+  if (regno <= 4095) return 1;
+  return 0;
+}
+/* -- */
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+
+/* Instruction formats.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & frv_cgen_ifld_table[FRV_##f]
+#else
+#define F(f) & frv_cgen_ifld_table[FRV_/**/f]
+#endif
+static const CGEN_IFMT ifmt_empty = {
+  0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_not = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_smul = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cadd = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cnot = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_csmul = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addcc = {
+  32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_smulcc = {
+  32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_smuli = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addicc = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_smulicc = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmpb = {
+  32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_setlo = {
+  32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sethi = {
+  32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_setlos = {
+  32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_S16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldsb = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldbf = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldc = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldd = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddf = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddc = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldsbi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldbfi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lddfi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stdf = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cldbf = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_clddf = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cstdf = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stdfi = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgf = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmovgf = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movgs = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_OP) }, { F (F_SPR) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bra = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bno = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beq = {
+  32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbra = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbno = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbne = {
+  32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bctrlr = {
+  32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bralr = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bnolr = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_beqlr = {
+  32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbralr = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbnolr = {
+  32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fbeqlr = {
+  32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bcralr = {
+  32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bceqlr = {
+  32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fcbralr = {
+  32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fcbeqlr = {
+  32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpl = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_calll = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpil = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_callil = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_call = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_OP) }, { F (F_LABEL24) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rett = {
+  32, 32, 0x7dffffff, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_DEBUG) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rei = {
+  32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_EIR) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tra = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tno = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_teq = {
+  32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftra = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftno = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftne = {
+  32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tira = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tino = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tieq = {
+  32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftira = {
+  32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftino = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ftine = {
+  32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_break = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_andcr = {
+  32, 32, 0x71ff8ff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_MISC_NULL_7) }, { F (F_CRI) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_notcr = {
+  32, 32, 0x71fffff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ckra = {
+  32, 32, 0x79ffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ckeq = {
+  32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fckra = {
+  32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_FCCI_3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cckra = {
+  32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cckeq = {
+  32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfckra = {
+  32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfckne = {
+  32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cjmpl = {
+  32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ccalll = {
+  32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ici = {
+  32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_icei = {
+  32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_AE) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_icpl = {
+  32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LOCK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_icul = {
+  32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bar = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cop1 = {
+  32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_clrgr = {
+  32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_clrfr = {
+  32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fitos = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fstoi = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fitod = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fdtoi = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfitos = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfstoi = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fmovs = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fmovd = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfmovs = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fadds = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_faddd = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfadds = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fcmps = {
+  32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fcmpd = {
+  32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cfcmps = {
+  32, 32, 0x79fc00c0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhsetlos = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhsethis = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhdsets = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhsetloh = {
+  32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhsethih = {
+  32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mhdseth = {
+  32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mand = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmand = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mnot = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmnot = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mrotli = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mcut = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mcuti = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mcmpsh = {
+  32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mabshs = {
+  32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_maddaccs = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mmulhs = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmmulhs = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mmachu = {
+  32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmmachu = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmexpdhw = {
+  32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_munpackh = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmbtoh = {
+  32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mclracc = {
+  32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mrdacc = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mrdaccg = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACCGI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mwtacc = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mwtaccg = {
+  32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACCGK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_fnop = {
+  32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } }
+};
+
+#undef F
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) FRV_OPERAND_##op
+#else
+#define OPERAND(op) FRV_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.  */
+
+static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* add$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x0 }
+  },
+/* sub$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x100 }
+  },
+/* and$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40000 }
+  },
+/* or$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40080 }
+  },
+/* xor$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40100 }
+  },
+/* not$pack $GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_not, { 0x40180 }
+  },
+/* sdiv$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x380 }
+  },
+/* nsdiv$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40380 }
+  },
+/* udiv$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x3c0 }
+  },
+/* nudiv$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x403c0 }
+  },
+/* smul$pack $GRi,$GRj,$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_smul, { 0x200 }
+  },
+/* umul$pack $GRi,$GRj,$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_smul, { 0x280 }
+  },
+/* sll$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40200 }
+  },
+/* srl$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40280 }
+  },
+/* sra$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x40300 }
+  },
+/* scan$pack $GRi,$GRj,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } },
+    & ifmt_add, { 0x2c0000 }
+  },
+/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1600000 }
+  },
+/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1600040 }
+  },
+/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1680000 }
+  },
+/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1680040 }
+  },
+/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1680080 }
+  },
+/* cnot$pack $GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cnot, { 0x16800c0 }
+  },
+/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_csmul, { 0x1600080 }
+  },
+/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x16000c0 }
+  },
+/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x16400c0 }
+  },
+/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1700000 }
+  },
+/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1700040 }
+  },
+/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1700080 }
+  },
+/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x19400c0 }
+  },
+/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x40 }
+  },
+/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x140 }
+  },
+/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x40040 }
+  },
+/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x400c0 }
+  },
+/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x40140 }
+  },
+/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x40240 }
+  },
+/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x402c0 }
+  },
+/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x40340 }
+  },
+/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } },
+    & ifmt_smulcc, { 0x240 }
+  },
+/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } },
+    & ifmt_smulcc, { 0x2c0 }
+  },
+/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1640000 }
+  },
+/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1640040 }
+  },
+/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_csmul, { 0x1640080 }
+  },
+/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x16c0000 }
+  },
+/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x16c0040 }
+  },
+/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x16c0080 }
+  },
+/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1740000 }
+  },
+/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1740040 }
+  },
+/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } },
+    & ifmt_cadd, { 0x1740080 }
+  },
+/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x80 }
+  },
+/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x180 }
+  },
+/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0xc0 }
+  },
+/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addcc, { 0x1c0 }
+  },
+/* addi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x400000 }
+  },
+/* subi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x500000 }
+  },
+/* andi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x800000 }
+  },
+/* ori$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x880000 }
+  },
+/* xori$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x900000 }
+  },
+/* sdivi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x780000 }
+  },
+/* nsdivi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0xb80000 }
+  },
+/* udivi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x7c0000 }
+  },
+/* nudivi$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0xbc0000 }
+  },
+/* smuli$pack $GRi,$s12,$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_smuli, { 0x600000 }
+  },
+/* umuli$pack $GRi,$s12,$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_smuli, { 0x680000 }
+  },
+/* slli$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0xa00000 }
+  },
+/* srli$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0xa80000 }
+  },
+/* srai$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0xb00000 }
+  },
+/* scani$pack $GRi,$s12,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } },
+    & ifmt_addi, { 0x11c0000 }
+  },
+/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x440000 }
+  },
+/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x540000 }
+  },
+/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x840000 }
+  },
+/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x8c0000 }
+  },
+/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x940000 }
+  },
+/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } },
+    & ifmt_smulicc, { 0x640000 }
+  },
+/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } },
+    & ifmt_smulicc, { 0x6c0000 }
+  },
+/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0xa40000 }
+  },
+/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0xac0000 }
+  },
+/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0xb40000 }
+  },
+/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x480000 }
+  },
+/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x580000 }
+  },
+/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x4c0000 }
+  },
+/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } },
+    & ifmt_addicc, { 0x5c0000 }
+  },
+/* cmpb$pack $GRi,$GRj,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } },
+    & ifmt_cmpb, { 0x300 }
+  },
+/* cmpba$pack $GRi,$GRj,$ICCi_1 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } },
+    & ifmt_cmpb, { 0x340 }
+  },
+/* setlo$pack $ulo16,$GRklo */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (ULO16), ',', OP (GRKLO), 0 } },
+    & ifmt_setlo, { 0xf40000 }
+  },
+/* sethi$pack $uhi16,$GRkhi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (UHI16), ',', OP (GRKHI), 0 } },
+    & ifmt_sethi, { 0xf80000 }
+  },
+/* setlos$pack $slo16,$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (SLO16), ',', OP (GRK), 0 } },
+    & ifmt_setlos, { 0xfc0000 }
+  },
+/* ldsb$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80000 }
+  },
+/* ldub$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80040 }
+  },
+/* ldsh$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80080 }
+  },
+/* lduh$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x800c0 }
+  },
+/* ld$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80100 }
+  },
+/* ldbf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80200 }
+  },
+/* ldhf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80240 }
+  },
+/* ldf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80280 }
+  },
+/* ldc$pack @($GRi,$GRj),$CPRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } },
+    & ifmt_ldc, { 0x80340 }
+  },
+/* nldsb$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80800 }
+  },
+/* nldub$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80840 }
+  },
+/* nldsh$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80880 }
+  },
+/* nlduh$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x808c0 }
+  },
+/* nld$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80900 }
+  },
+/* nldbf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80a00 }
+  },
+/* nldhf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80a40 }
+  },
+/* nldf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80a80 }
+  },
+/* ldd$pack @($GRi,$GRj),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_ldd, { 0x80140 }
+  },
+/* lddf$pack @($GRi,$GRj),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddf, { 0x802c0 }
+  },
+/* lddc$pack @($GRi,$GRj),$CPRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } },
+    & ifmt_lddc, { 0x80380 }
+  },
+/* nldd$pack @($GRi,$GRj),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_ldd, { 0x80940 }
+  },
+/* nlddf$pack @($GRi,$GRj),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddf, { 0x80ac0 }
+  },
+/* ldq$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80180 }
+  },
+/* ldqf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80300 }
+  },
+/* ldqc$pack @($GRi,$GRj),$CPRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } },
+    & ifmt_ldc, { 0x803c0 }
+  },
+/* nldq$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80980 }
+  },
+/* nldqf$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80b00 }
+  },
+/* ldsbu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80400 }
+  },
+/* ldubu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80440 }
+  },
+/* ldshu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80480 }
+  },
+/* lduhu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x804c0 }
+  },
+/* ldu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80500 }
+  },
+/* nldsbu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80c00 }
+  },
+/* nldubu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80c40 }
+  },
+/* nldshu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80c80 }
+  },
+/* nlduhu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80cc0 }
+  },
+/* nldu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80d00 }
+  },
+/* ldbfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80600 }
+  },
+/* ldhfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80640 }
+  },
+/* ldfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80680 }
+  },
+/* ldcu$pack @($GRi,$GRj),$CPRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } },
+    & ifmt_ldc, { 0x80740 }
+  },
+/* nldbfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80e00 }
+  },
+/* nldhfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80e40 }
+  },
+/* nldfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80e80 }
+  },
+/* lddu$pack @($GRi,$GRj),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_ldd, { 0x80540 }
+  },
+/* nlddu$pack @($GRi,$GRj),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_ldd, { 0x80d40 }
+  },
+/* lddfu$pack @($GRi,$GRj),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddf, { 0x806c0 }
+  },
+/* lddcu$pack @($GRi,$GRj),$CPRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } },
+    & ifmt_lddc, { 0x80780 }
+  },
+/* nlddfu$pack @($GRi,$GRj),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddf, { 0x80ec0 }
+  },
+/* ldqu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80580 }
+  },
+/* nldqu$pack @($GRi,$GRj),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsb, { 0x80d80 }
+  },
+/* ldqfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80700 }
+  },
+/* ldqcu$pack @($GRi,$GRj),$CPRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } },
+    & ifmt_ldc, { 0x807c0 }
+  },
+/* nldqfu$pack @($GRi,$GRj),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbf, { 0x80f00 }
+  },
+/* ldsbi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xc00000 }
+  },
+/* ldshi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xc40000 }
+  },
+/* ldi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xc80000 }
+  },
+/* ldubi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xd40000 }
+  },
+/* lduhi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xd80000 }
+  },
+/* ldbfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0xe00000 }
+  },
+/* ldhfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0xe40000 }
+  },
+/* ldfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0xe80000 }
+  },
+/* nldsbi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x1000000 }
+  },
+/* nldubi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x1040000 }
+  },
+/* nldshi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x1080000 }
+  },
+/* nlduhi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x10c0000 }
+  },
+/* nldi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x1100000 }
+  },
+/* nldbfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0x1200000 }
+  },
+/* nldhfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0x1240000 }
+  },
+/* nldfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0x1280000 }
+  },
+/* lddi$pack @($GRi,$d12),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_lddi, { 0xcc0000 }
+  },
+/* lddfi$pack @($GRi,$d12),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddfi, { 0xec0000 }
+  },
+/* nlddi$pack @($GRi,$d12),$GRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } },
+    & ifmt_lddi, { 0x1140000 }
+  },
+/* nlddfi$pack @($GRi,$d12),$FRdoublek */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } },
+    & ifmt_lddfi, { 0x12c0000 }
+  },
+/* ldqi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0xd00000 }
+  },
+/* ldqfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0xf00000 }
+  },
+/* nldqi$pack @($GRi,$d12),$GRk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
+    & ifmt_ldsbi, { 0x1180000 }
+  },
+/* nldqfi$pack @($GRi,$d12),$FRintk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
+    & ifmt_ldbfi, { 0x1300000 }
+  },
+/* stb$pack $GRk,@($GRi,$GRj) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldsb, { 0xc0000 }
+  },
+/* sth$pack $GRk,@($GRi,$GRj) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldsb, { 0xc0040 }
+  },
+/* st$pack $GRk,@($GRi,$GRj) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } },
+    & ifmt_ldsb, { 0xc0080 }
+  },
+/* stbf$pack $FRintk,@($GRi,$GRj) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, OP (PACK), ' ', OP (F