OSDN > Developer >

alaskanemily > Chamber > binutils_os216 > 提交

alaskanemily

binutils_os216
Fork

Fork origin: git://...db.git

R/O
HTTP
SSH
HTTPS

提交

Commit MetaInfo

修订版	6ec7c1ae19e9e1bf2edad5125941a2fd5fdfde0b (tree)
时间	2017-02-06 19:26:13
作者	Claudiu Zissulescu <claziss@syno...>
Commiter	Claudiu Zissulescu

Log Message

[ARC] Provide an interface to decode ARC instructions.

gas/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>

* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.

include/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>

* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
flag classes.

opcode/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>

* arc-dis.c (arc_disassemble_info): New structure.
(init_arc_disasm_info): New function.
(find_format_from_table): Ignore implicit flags.
(find_format): Update dissassembler private data.
(print_flags): Likewise.
(print_insn_arc): Likewise.
(arc_opcode_to_insn_type): Consider the new added instruction
classes.
(arcAnalyzeInstr): Remove.
(arc_insn_decode): New function.
* arc-dis.h (arc_ldst_writeback_mode): New enum.
(arc_ldst_data_size): Likewise.
(arc_condition_code): Likewise.
(arc_operand_kind): Likewise.
(arc_insn_kind): New struct.
(arc_instruction): Likewise.
(arc_insn_decode): Declare function.
(ARC_Debugger_OperandType): Deleted.
(Flow): Likewise.
(NullifyMode): Likewise.
(allOperandsSize): Likewise.
(arcDisState): Likewise.
(arcAnalyzeInstr): Likewise.
* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
insn_class_t enums.
* arc-opc.c (F_SIZED): New define.
(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
* opcodes/arc-tbl.h: Update instructions to include new
F_CLASS_IMPLICIT flags.
(bbit0, lp): Change class.
(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie

更改概述

modified: gas/config/tc-arc.c (diff)
modified: include/opcode/arc.h (diff)
modified: opcodes/arc-dis.c (diff)
modified: opcodes/arc-dis.h (diff)
modified: opcodes/arc-opc.c (diff)
modified: opcodes/arc-tbl.h (diff)

差异

--- a/gas/config/tc-arc.c

+++ b/gas/config/tc-arc.c

		@@ -1671,6 +1671,10 @@ parse_opcode_flags (const struct arc_opcode *opcode,
1671	1671	int cl_matches = 0;
1672	1672	struct arc_flags *pflag = NULL;
1673	1673
	1674	+ /* Check if opcode has implicit flag classes. */
	1675	+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
	1676	+ continue;
	1677	+
1674	1678	/* Check for extension conditional codes. */
1675	1679	if (ext_condcode.arc_ext_condcode
1676	1680	&& cl_flags->flag_class & F_CLASS_EXTEND)

--- a/include/opcode/arc.h

+++ b/include/opcode/arc.h

		@@ -42,27 +42,40 @@ typedef enum
42	42	ACL,
43	43	ARITH,
44	44	AUXREG,
	45	+ BBIT0,
	46	+ BBIT1,
	47	+ BI,
	48	+ BIH,
45	49	BITOP,
46	50	BITSTREAM,
47	51	BMU,
48	52	BRANCH,
	53	+ BRCC,
49	54	CONTROL,
50	55	DIVREM,
51	56	DPI,
52	57	DSP,
	58	+ EI,
	59	+ ENTER,
53	60	FLOAT,
54	61	INVALID,
	62	+ JLI,
55	63	JUMP,
56	64	KERNEL,
	65	+ LEAVE,
57	66	LOAD,
58	67	LOGICAL,
	68	+ LOOP,
59	69	MEMORY,
60	70	MOVE,
61	71	MPY,
62	72	NET,
63	73	PROTOCOL_DECODE,
64	74	PMU,
	75	+ POP,
	76	+ PUSH,
65	77	STORE,
	78	+ SUB,
66	79	XY
67	80	} insn_class_t;
68	81

		@@ -111,7 +124,16 @@ typedef enum
111	124	F_CLASS_EXTEND = (1 << 2),
112	125
113	126	/* Condition code flag. */
114		- F_CLASS_COND = (1 << 3)
	127	+ F_CLASS_COND = (1 << 3),
	128	+
	129	+ /* Write back mode. */
	130	+ F_CLASS_WB = (1 << 4),
	131	+
	132	+ /* Data size. */
	133	+ F_CLASS_ZZ = (1 << 5),
	134	+
	135	+ /* Implicit flag. */
	136	+ F_CLASS_IMPLICIT = (1 << 6)
115	137	} flag_class_t;
116	138
117	139	/* The opcode table is an array of struct arc_opcode. */

--- a/opcodes/arc-dis.c

+++ b/opcodes/arc-dis.c

		@@ -51,6 +51,33 @@ struct arc_operand_iterator
51	51	const unsigned char *opidx;
52	52	};
53	53
	54	+/* A private data used by ARC decoder. */
	55	+struct arc_disassemble_info
	56	+{
	57	+ /* The current disassembled arc opcode. */
	58	+ const struct arc_opcode *opcode;
	59	+
	60	+ /* Instruction length w/o limm field. */
	61	+ unsigned insn_len;
	62	+
	63	+ /* TRUE if we have limm. */
	64	+ bfd_boolean limm_p;
	65	+
	66	+ /* LIMM value, if exists. */
	67	+ unsigned limm;
	68	+
	69	+ /* Condition code, if exists. */
	70	+ unsigned condition_code;
	71	+
	72	+ /* Writeback mode. */
	73	+ unsigned writeback_mode;
	74	+
	75	+ /* Number of operands. */
	76	+ unsigned operands_count;
	77	+
	78	+ struct arc_insn_operand operands[MAX_INSN_ARGS];
	79	+};
	80	+
54	81	/* Globals variables. */
55	82
56	83	static const char * const regnames[64] =

		@@ -108,6 +135,20 @@ static linkclass decodelist = NULL;
108	135
109	136	/* Functions implementation. */
110	137
	138	+/* Initialize private data. */
	139	+static bfd_boolean
	140	+init_arc_disasm_info (struct disassemble_info *info)
	141	+{
	142	+ struct arc_disassemble_info *arc_infop
	143	+ = calloc (sizeof (*arc_infop), 1);
	144	+
	145	+ if (arc_infop == NULL)
	146	+ return FALSE;
	147	+
	148	+ info->private_data = arc_infop;
	149	+ return TRUE;
	150	+}
	151	+
111	152	/* Add a new element to the decode list. */
112	153
113	154	static void

		@@ -280,6 +321,10 @@ find_format_from_table (struct disassemble_info *info,
280	321	continue;
281	322	}
282	323
	324	+ /* Check for the implicit flags. */
	325	+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
	326	+ continue;
	327	+
283	328	for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
284	329	{
285	330	const struct arc_flag_operand *flg_operand =

		@@ -367,6 +412,7 @@ find_format (bfd_vma memaddr,
367	412	bfd_boolean needs_limm;
368	413	const extInstruction_t einsn, i;
369	414	unsigned limm = 0;
	415	+ struct arc_disassemble_info *arc_infop = info->private_data;
370	416
371	417	/* First, try the extension instructions. */
372	418	if (*insn_len == 4)

		@@ -422,6 +468,12 @@ An error occured while generating the extension instruction operations");
422	468	}
423	469
424	470	*opcode_result = opcode;
	471	+
	472	+ /* Update private data. */
	473	+ arc_infop->opcode = opcode;
	474	+ arc_infop->limm = (needs_limm) ? limm : 0;
	475	+ arc_infop->limm_p = needs_limm;
	476	+
425	477	return TRUE;
426	478	}
427	479

		@@ -432,6 +484,7 @@ print_flags (const struct arc_opcode *opcode,
432	484	{
433	485	const unsigned char *flgidx;
434	486	unsigned int value;
	487	+ struct arc_disassemble_info *arc_infop = info->private_data;
435	488
436	489	/* Now extract and print the flags. */
437	490	for (flgidx = opcode->flags; *flgidx; flgidx++)

		@@ -459,6 +512,18 @@ print_flags (const struct arc_opcode *opcode,
459	512	const struct arc_flag_operand *flg_operand =
460	513	&arc_flag_operands[*flgopridx];
461	514
	515	+ /* Implicit flags are only used for the insn decoder. */
	516	+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
	517	+ {
	518	+ if (cl_flags->flag_class & F_CLASS_COND)
	519	+ arc_infop->condition_code = flg_operand->code;
	520	+ else if (cl_flags->flag_class & F_CLASS_WB)
	521	+ arc_infop->writeback_mode = flg_operand->code;
	522	+ else if (cl_flags->flag_class & F_CLASS_ZZ)
	523	+ info->data_size = flg_operand->code;
	524	+ continue;
	525	+ }
	526	+
462	527	if (!flg_operand->favail)
463	528	continue;
464	529

		@@ -496,8 +561,13 @@ print_flags (const struct arc_opcode *opcode,
496	561	info->insn_type = dis_condjsr;
497	562	else if (info->insn_type == dis_branch)
498	563	info->insn_type = dis_condbranch;
	564	+ arc_infop->condition_code = flg_operand->code;
499	565	}
500	566
	567	+ /* Check for the write back modes. */
	568	+ if (cl_flags->flag_class & F_CLASS_WB)
	569	+ arc_infop->writeback_mode = flg_operand->code;
	570	+
501	571	(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
502	572	}
503	573	}

		@@ -733,7 +803,15 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
733	803	switch (opcode->insn_class)
734	804	{
735	805	case BRANCH:
	806	+ case BBIT0:
	807	+ case BBIT1:
	808	+ case BI:
	809	+ case BIH:
	810	+ case BRCC:
	811	+ case EI:
	812	+ case JLI:
736	813	case JUMP:
	814	+ case LOOP:
737	815	if (!strncmp (opcode->name, "bl", 2)
738	816	\|\| !strncmp (opcode->name, "jl", 2))
739	817	{

		@@ -753,8 +831,14 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
753	831	case LOAD:
754	832	case STORE:
755	833	case MEMORY:
	834	+ case ENTER:
	835	+ case PUSH:
	836	+ case POP:
756	837	insn_type = dis_dref;
757	838	break;
	839	+ case LEAVE:
	840	+ insn_type = dis_branch;
	841	+ break;
758	842	default:
759	843	insn_type = dis_nonbranch;
760	844	break;

		@@ -783,6 +867,7 @@ print_insn_arc (bfd_vma memaddr,
783	867	int value;
784	868	struct arc_operand_iterator iter;
785	869	Elf_Internal_Ehdr *header = NULL;
	870	+ struct arc_disassemble_info *arc_infop;
786	871
787	872	if (info->disassembler_options)
788	873	{

		@@ -792,6 +877,9 @@ print_insn_arc (bfd_vma memaddr,
792	877	info->disassembler_options = NULL;
793	878	}
794	879
	880	+ if (info->private_data == NULL && !init_arc_disasm_info (info))
	881	+ return -1;
	882	+
795	883	memset (&iter, 0, sizeof (iter));
796	884	highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
797	885	lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);

		@@ -813,7 +901,7 @@ print_insn_arc (bfd_vma memaddr,
813	901	default:
814	902	isa_mask = ARC_OPCODE_ARCv2EM;
815	903	/* TODO: Perhaps remove defitinion of header since it is only used at
816		- this location. */
	904	+ this location. */
817	905	if (header != NULL
818	906	&& (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
819	907	{

		@@ -899,6 +987,8 @@ print_insn_arc (bfd_vma memaddr,
899	987
900	988	insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info);
901	989	pr_debug ("instruction length = %d bytes\n", insn_len);
	990	+ arc_infop = info->private_data;
	991	+ arc_infop->insn_len = insn_len;
902	992
903	993	switch (insn_len)
904	994	{

		@@ -957,7 +1047,7 @@ print_insn_arc (bfd_vma memaddr,
957	1047	/* Set some defaults for the insn info. */
958	1048	info->insn_info_valid = 1;
959	1049	info->branch_delay_insns = 0;
960		- info->data_size = 0;
	1050	+ info->data_size = 4;
961	1051	info->insn_type = dis_nonbranch;
962	1052	info->target = 0;
963	1053	info->target2 = 0;

		@@ -1016,6 +1106,7 @@ print_insn_arc (bfd_vma memaddr,
1016	1106
1017	1107	need_comma = FALSE;
1018	1108	open_braket = FALSE;
	1109	+ arc_infop->operands_count = 0;
1019	1110
1020	1111	/* Now extract and print the operands. */
1021	1112	operand = NULL;

		@@ -1034,14 +1125,14 @@ print_insn_arc (bfd_vma memaddr,
1034	1125
1035	1126	if ((operand->flags & ARC_OPERAND_IGNORE)
1036	1127	&& (operand->flags & ARC_OPERAND_IR)
1037		- && value == -1)
	1128	+ && value == -1)
1038	1129	continue;
1039	1130
1040	1131	if (operand->flags & ARC_OPERAND_COLON)
1041		- {
1042		- (*info->fprintf_func) (info->stream, ":");
1043		- continue;
1044		- }
	1132	+ {
	1133	+ (*info->fprintf_func) (info->stream, ":");
	1134	+ continue;
	1135	+ }
1045	1136
1046	1137	if (need_comma)
1047	1138	(*info->fprintf_func) (info->stream, ",");

		@@ -1106,12 +1197,12 @@ print_insn_arc (bfd_vma memaddr,
1106	1197	(*info->fprintf_func) (info->stream, "%d", value);
1107	1198	}
1108	1199	else if (operand->flags & ARC_OPERAND_ADDRTYPE)
1109		- {
1110		- const char *addrtype = get_addrtype (value);
1111		- (*info->fprintf_func) (info->stream, "%s", addrtype);
1112		- /* A colon follow an address type. */
1113		- need_comma = FALSE;
1114		- }
	1200	+ {
	1201	+ const char *addrtype = get_addrtype (value);
	1202	+ (*info->fprintf_func) (info->stream, "%s", addrtype);
	1203	+ /* A colon follow an address type. */
	1204	+ need_comma = FALSE;
	1205	+ }
1115	1206	else
1116	1207	{
1117	1208	if (operand->flags & ARC_OPERAND_TRUNCATE

		@@ -1129,6 +1220,24 @@ print_insn_arc (bfd_vma memaddr,
1129	1220	(*info->fprintf_func) (info->stream, "%#x", value);
1130	1221	}
1131	1222	}
	1223	+
	1224	+ if (operand->flags & ARC_OPERAND_LIMM)
	1225	+ {
	1226	+ arc_infop->operands[arc_infop->operands_count].kind
	1227	+ = ARC_OPERAND_KIND_LIMM;
	1228	+ /* It is not important to have exactly the LIMM indicator
	1229	+ here. */
	1230	+ arc_infop->operands[arc_infop->operands_count].value = 63;
	1231	+ }
	1232	+ else
	1233	+ {
	1234	+ arc_infop->operands[arc_infop->operands_count].value = value;
	1235	+ arc_infop->operands[arc_infop->operands_count].kind
	1236	+ = (operand->flags & ARC_OPERAND_IR
	1237	+ ? ARC_OPERAND_KIND_REG
	1238	+ : ARC_OPERAND_KIND_SHIMM);
	1239	+ }
	1240	+ arc_infop->operands_count ++;
1132	1241	}
1133	1242
1134	1243	return insn_len;

		@@ -1152,30 +1261,6 @@ arc_get_disassembler (bfd *abfd)
1152	1261	return print_insn_arc;
1153	1262	}
1154	1263
1155		-/* Disassemble ARC instructions. Used by debugger. */
1156		-
1157		-struct arcDisState
1158		-arcAnalyzeInstr (bfd_vma memaddr,
1159		- struct disassemble_info *info)
1160		-{
1161		- struct arcDisState ret;
1162		- memset (&ret, 0, sizeof (struct arcDisState));
1163		-
1164		- ret.instructionLen = print_insn_arc (memaddr, info);
1165		-
1166		-#if 0
1167		- ret.words[0] = insn[0];
1168		- ret.words[1] = insn[1];
1169		- ret._this = &ret;
1170		- ret.coreRegName = _coreRegName;
1171		- ret.auxRegName = _auxRegName;
1172		- ret.condCodeName = _condCodeName;
1173		- ret.instName = _instName;
1174		-#endif
1175		-
1176		- return ret;
1177		-}
1178		-
1179	1264	void
1180	1265	print_arc_disassembler_options (FILE *stream)
1181	1266	{

		@@ -1199,6 +1284,58 @@ with -M switch (multiple options should be separated by commas):\n"));
1199	1284	fpud Recognize double precision FPU instructions.\n"));
1200	1285	}
1201	1286
	1287	+void arc_insn_decode (bfd_vma addr,
	1288	+ struct disassemble_info *info,
	1289	+ disassembler_ftype disasm_func,
	1290	+ struct arc_instruction *insn)
	1291	+{
	1292	+ const struct arc_opcode *opcode;
	1293	+ struct arc_disassemble_info *arc_infop;
	1294	+
	1295	+ /* Ensure that insn would be in the reset state. */
	1296	+ memset (insn, 0, sizeof (struct arc_instruction));
	1297	+
	1298	+ /* There was an error when disassembling, for example memory read error. */
	1299	+ if (disasm_func (addr, info) < 0)
	1300	+ {
	1301	+ insn->valid = FALSE;
	1302	+ return;
	1303	+ }
	1304	+
	1305	+ assert (info->private_data != NULL);
	1306	+ arc_infop = info->private_data;
	1307	+
	1308	+ insn->length = arc_infop->insn_len;;
	1309	+ insn->address = addr;
	1310	+
	1311	+ /* Quick exit if memory at this address is not an instruction. */
	1312	+ if (info->insn_type == dis_noninsn)
	1313	+ {
	1314	+ insn->valid = FALSE;
	1315	+ return;
	1316	+ }
	1317	+
	1318	+ insn->valid = TRUE;
	1319	+
	1320	+ opcode = (const struct arc_opcode *) arc_infop->opcode;
	1321	+ insn->insn_class = opcode->insn_class;
	1322	+ insn->limm_value = arc_infop->limm;
	1323	+ insn->limm_p = arc_infop->limm_p;
	1324	+
	1325	+ insn->is_control_flow = (info->insn_type == dis_branch
	1326	+ \|\| info->insn_type == dis_condbranch
	1327	+ \|\| info->insn_type == dis_jsr
	1328	+ \|\| info->insn_type == dis_condjsr);
	1329	+
	1330	+ insn->has_delay_slot = info->branch_delay_insns;
	1331	+ insn->writeback_mode
	1332	+ = (enum arc_ldst_writeback_mode) arc_infop->writeback_mode;
	1333	+ insn->data_size_mode = info->data_size;
	1334	+ insn->condition_code = arc_infop->condition_code;
	1335	+ memcpy (insn->operands, arc_infop->operands,
	1336	+ sizeof (struct arc_insn_operand) * MAX_INSN_ARGS);
	1337	+ insn->operands_count = arc_infop->operands_count;
	1338	+}
1202	1339
1203	1340	/* Local variables:
1204	1341	eval: (c-set-style "gnu")

--- a/opcodes/arc-dis.h

+++ b/opcodes/arc-dis.h

		@@ -26,86 +26,148 @@
26	26	extern "C" {
27	27	#endif
28	28
29		-enum ARC_Debugger_OperandType
	29	+enum arc_ldst_writeback_mode
30	30	{
31		- ARC_UNDEFINED,
32		- ARC_LIMM,
33		- ARC_SHIMM,
34		- ARC_REGISTER,
35		- ARCOMPACT_REGISTER /* Valid only for the
36		- registers allowed in
37		- 16 bit mode. */
	31	+ ARC_WRITEBACK_NO = 0,
	32	+ ARC_WRITEBACK_AW = 1,
	33	+ ARC_WRITEBACK_A = ARC_WRITEBACK_AW,
	34	+ ARC_WRITEBACK_AB = 2,
	35	+ ARC_WRITEBACK_AS = 3,
38	36	};
39	37
40		-enum Flow
	38	+
	39	+enum arc_ldst_data_size
41	40	{
42		- noflow,
43		- direct_jump,
44		- direct_call,
45		- indirect_jump,
46		- indirect_call,
47		- invalid_instr
	41	+ ARC_SCALING_NONE = 4,
	42	+ ARC_SCALING_B = 1,
	43	+ ARC_SCALING_H = 2,
	44	+ ARC_SCALING_D = 8,
48	45	};
49	46
50		-enum NullifyMode
	47	+
	48	+enum arc_condition_code
51	49	{
52		- BR_exec_when_no_jump,
53		- BR_exec_always,
54		- BR_exec_when_jump
	50	+ ARC_CC_AL = 0x0,
	51	+ ARC_CC_RA = ARC_CC_AL,
	52	+ ARC_CC_EQ = 0x1,
	53	+ ARC_CC_Z = ARC_CC_EQ,
	54	+ ARC_CC_NE = 0x2,
	55	+ ARC_CC_NZ = ARC_CC_NE,
	56	+ ARC_CC_PL = 0x3,
	57	+ ARC_CC_P = ARC_CC_PL,
	58	+ ARC_CC_MI = 0x4,
	59	+ ARC_CC_N = ARC_CC_MI,
	60	+ ARC_CC_CS = 0x5,
	61	+ ARC_CC_C = ARC_CC_CS,
	62	+ ARC_CC_LO = ARC_CC_CS,
	63	+ ARC_CC_CC = 0x6,
	64	+ ARC_CC_NC = ARC_CC_CC,
	65	+ ARC_CC_HS = ARC_CC_CC,
	66	+ ARC_CC_VS = 0x7,
	67	+ ARC_CC_V = ARC_CC_VS,
	68	+ ARC_CC_VC = 0x8,
	69	+ ARC_CC_NV = ARC_CC_VC,
	70	+ ARC_CC_GT = 0x9,
	71	+ ARC_CC_GE = 0xA,
	72	+ ARC_CC_LT = 0xB,
	73	+ ARC_CC_LE = 0xC,
	74	+ ARC_CC_HI = 0xD,
	75	+ ARC_CC_LS = 0xE,
	76	+ ARC_CC_PNZ = 0xF,
	77	+ ARC_CC_UNDEF0 = 0x10,
	78	+ ARC_CC_UNDEF1 = 0x11,
	79	+ ARC_CC_UNDEF2 = 0x12,
	80	+ ARC_CC_UNDEF3 = 0x13,
	81	+ ARC_CC_UNDEF4 = 0x14,
	82	+ ARC_CC_UNDEF5 = 0x15,
	83	+ ARC_CC_UNDEF6 = 0x16,
	84	+ ARC_CC_UNDEF7 = 0x17,
	85	+ ARC_CC_UNDEF8 = 0x18,
	86	+ ARC_CC_UNDEF9 = 0x19,
	87	+ ARC_CC_UNDEFA = 0x1A,
	88	+ ARC_CC_UNDEFB = 0x1B,
	89	+ ARC_CC_UNDEFC = 0x1C,
	90	+ ARC_CC_UNDEFD = 0x1D,
	91	+ ARC_CC_UNDEFE = 0x1E,
	92	+ ARC_CC_UNDEFF = 0x1F
55	93	};
56	94
57		-enum { allOperandsSize = 256 };
	95	+enum arc_operand_kind
	96	+{
	97	+ ARC_OPERAND_KIND_UNKNOWN = 0,
	98	+ ARC_OPERAND_KIND_REG,
	99	+ ARC_OPERAND_KIND_SHIMM,
	100	+ ARC_OPERAND_KIND_LIMM
	101	+};
58	102
59		-struct arcDisState
	103	+struct arc_insn_operand
60	104	{
61		- void *_this;
62		- int instructionLen;
63		- void (err)(void, const char*);
64		- const char (coreRegName)(void*, int);
65		- const char (auxRegName)(void*, int);
66		- const char (condCodeName)(void*, int);
67		- const char (instName)(void, int, int, int);
68		-
69		- unsigned char* instruction;
70		- unsigned index;
71		- const char comm[6]; / Instr name, cond, NOP, 3 operands. */
72		-
73		- union
74		- {
75		- unsigned int registerNum;
76		- unsigned int shortimm;
77		- unsigned int longimm;
78		- } source_operand;
79		- enum ARC_Debugger_OperandType sourceType;
80		-
81		- int opWidth;
82		- int targets[4];
83		- /* START ARC LOCAL. */
84		- unsigned int addresses[4];
85		- /* END ARC LOCAL. */
86		- /* Set as a side-effect of calling the disassembler.
87		- Used only by the debugger. */
88		- enum Flow flow;
89		- int register_for_indirect_jump;
90		- int ea_reg1, ea_reg2, _offset;
91		- int _cond, _opcode;
92		- unsigned long words[2];
93		- char *commentBuffer;
94		- char instrBuffer[40];
95		- char operandBuffer[allOperandsSize];
96		- char _ea_present;
97		- char _addrWriteBack; /* Address writeback. */
98		- char _mem_load;
99		- char _load_len;
100		- enum NullifyMode nullifyMode;
101		- unsigned char commNum;
102		- unsigned char isBranch;
103		- unsigned char tcnt;
104		- unsigned char acnt;
	105	+ /* Operand value as encoded in instruction. */
	106	+ unsigned long value;
	107	+
	108	+ enum arc_operand_kind kind;
	109	+};
	110	+
	111	+/* Container for information about instruction. Provides a higher
	112	+ level access to data that is contained in struct arc_opcode. */
	113	+
	114	+struct arc_instruction
	115	+{
	116	+ /* Address of this instruction. */
	117	+ bfd_vma address;
	118	+
	119	+ /* Whether this is a valid instruction. */
	120	+ bfd_boolean valid;
	121	+
	122	+ insn_class_t insn_class;
	123	+
	124	+ /* Length (without LIMM). */
	125	+ unsigned length;
	126	+
	127	+ /* Is there a LIMM in this instruction? */
	128	+ int limm_p;
	129	+
	130	+ /* Long immediate value. */
	131	+ unsigned limm_value;
	132	+
	133	+ /* Is it a branch/jump instruction? */
	134	+ int is_control_flow;
	135	+
	136	+ /* Whether this instruction has a delay slot. */
	137	+ int has_delay_slot;
	138	+
	139	+ /* Value of condition code field. */
	140	+ enum arc_condition_code condition_code;
	141	+
	142	+ /* Load/store writeback mode. */
	143	+ enum arc_ldst_writeback_mode writeback_mode;
	144	+
	145	+ /* Load/store data size. */
	146	+ enum arc_ldst_data_size data_size_mode;
	147	+
	148	+ /* Amount of operands in instruction. Note that amount of operands
	149	+ reported by opcodes disassembler can be different from the one
	150	+ encoded in the instruction. Notable case is "ld a,[b,offset]",
	151	+ when offset == 0. In this case opcodes disassembler presents
	152	+ this instruction as "ld a,[b]", hence there are two operands,
	153	+ not three. OPERANDS_COUNT and OPERANDS contain only those
	154	+ explicit operands, hence it is up to invoker to handle the case
	155	+ described above based on instruction opcodes. Another notable
	156	+ thing is that in opcodes disassembler representation square
	157	+ brackets (`[' and `]') are so called fake-operands - they are in
	158	+ the list of operands, but do not have any value of they own.
	159	+ Those "operands" are not present in this array. */
	160	+ struct arc_insn_operand operands[MAX_INSN_ARGS];
	161	+
	162	+ unsigned int operands_count;
105	163	};
106	164
107		-struct arcDisState
108		-arcAnalyzeInstr (bfd_vma memaddr, struct disassemble_info *);
	165	+/* Fill INSN with data about instruction at specified ADDR. */
	166	+
	167	+void arc_insn_decode (bfd_vma addr,
	168	+ struct disassemble_info *di,
	169	+ disassembler_ftype func,
	170	+ struct arc_instruction *insn);
109	171
110	172	#ifdef __cplusplus
111	173	}

--- a/opcodes/arc-opc.c

+++ b/opcodes/arc-opc.c

		@@ -1290,9 +1290,11 @@ const struct arc_flag_operand arc_flag_operands[] =
1290	1290	{ "h", 2, 2, 7, 1 },
1291	1291	#define F_H17 (F_H7 + 1)
1292	1292	{ "h", 2, 2, 17, 1 },
	1293	+#define F_SIZED (F_H17 + 1)
	1294	+ { "dd", 8, 0, 0, 0 }, /* Fake. */
1293	1295
1294	1296	/* Fake Flags. */
1295		-#define F_NE (F_H17 + 1)
	1297	+#define F_NE (F_SIZED + 1)
1296	1298	{ "ne", 0, 0, 0, 1 },
1297	1299
1298	1300	/* ARC NPS400 Support: See comment near head of file. */

		@@ -1398,7 +1400,52 @@ const struct arc_flag_class arc_flag_classes[] =
1398	1400	#define C_EMPTY 0
1399	1401	{ F_CLASS_NONE, { F_NULL } },
1400	1402
1401		-#define C_CC (C_EMPTY + 1)
	1403	+#define C_CC_EQ (C_EMPTY + 1)
	1404	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_EQUAL, F_NULL} },
	1405	+
	1406	+#define C_CC_GE (C_CC_EQ + 1)
	1407	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_GE, F_NULL} },
	1408	+
	1409	+#define C_CC_GT (C_CC_GE + 1)
	1410	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_GT, F_NULL} },
	1411	+
	1412	+#define C_CC_HI (C_CC_GT + 1)
	1413	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_HI, F_NULL} },
	1414	+
	1415	+#define C_CC_HS (C_CC_HI + 1)
	1416	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_NOTCARRY, F_NULL} },
	1417	+
	1418	+#define C_CC_LE (C_CC_HS + 1)
	1419	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_LE, F_NULL} },
	1420	+
	1421	+#define C_CC_LO (C_CC_LE + 1)
	1422	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_CARRY, F_NULL} },
	1423	+
	1424	+#define C_CC_LS (C_CC_LO + 1)
	1425	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_LS, F_NULL} },
	1426	+
	1427	+#define C_CC_LT (C_CC_LS + 1)
	1428	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_LT, F_NULL} },
	1429	+
	1430	+#define C_CC_NE (C_CC_LT + 1)
	1431	+ {F_CLASS_IMPLICIT \| F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
	1432	+
	1433	+#define C_AA_AB (C_CC_NE + 1)
	1434	+ {F_CLASS_IMPLICIT \| F_CLASS_WB, {F_AB3, F_NULL} },
	1435	+
	1436	+#define C_AA_AW (C_AA_AB + 1)
	1437	+ {F_CLASS_IMPLICIT \| F_CLASS_WB, {F_AW3, F_NULL} },
	1438	+
	1439	+#define C_ZZ_D (C_AA_AW + 1)
	1440	+ {F_CLASS_IMPLICIT \| F_CLASS_ZZ, {F_SIZED, F_NULL} },
	1441	+
	1442	+#define C_ZZ_H (C_ZZ_D + 1)
	1443	+ {F_CLASS_IMPLICIT \| F_CLASS_ZZ, {F_H1, F_NULL} },
	1444	+
	1445	+#define C_ZZ_B (C_ZZ_H + 1)
	1446	+ {F_CLASS_IMPLICIT \| F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
	1447	+
	1448	+#define C_CC (C_ZZ_B + 1)
1402	1449	{ F_CLASS_OPTIONAL \| F_CLASS_EXTEND \| F_CLASS_COND,
1403	1450	{ F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1404	1451	F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,

		@@ -1409,13 +1456,13 @@ const struct arc_flag_class arc_flag_classes[] =
1409	1456
1410	1457	#define C_AA_ADDR3 (C_CC + 1)
1411	1458	#define C_AA27 (C_CC + 1)
1412		- { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
	1459	+ { F_CLASS_OPTIONAL \| F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1413	1460	#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1414	1461	#define C_AA21 (C_AA_ADDR3 + 1)
1415		- { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
	1462	+ { F_CLASS_OPTIONAL \| F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1416	1463	#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1417	1464	#define C_AA8 (C_AA_ADDR9 + 1)
1418		- { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
	1465	+ { F_CLASS_OPTIONAL \| F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1419	1466
1420	1467	#define C_F (C_AA_ADDR22 + 1)
1421	1468	{ F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },

--- a/opcodes/arc-tbl.h

+++ b/opcodes/arc-tbl.h

		@@ -1397,76 +1397,76 @@
1397	1397	{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
1398	1398
1399	1399	/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */
1400		-{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1400	+{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
1401	1401
1402	1402	/* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110. */
1403		-{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1403	+{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
1404	1404
1405	1405	/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */
1406		-{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1406	+{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
1407	1407
1408	1408	/* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110. */
1409		-{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1409	+{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
1410	1410
1411	1411	/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110. */
1412		-{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1412	+{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
1413	1413
1414	1414	/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110. */
1415		-{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1415	+{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
1416	1416
1417	1417	/* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110. */
1418		-{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1418	+{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
1419	1419
1420	1420	/* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110. */
1421		-{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1421	+{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
1422	1422
1423	1423	/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110. */
1424		-{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1424	+{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
1425	1425
1426	1426	/* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110. */
1427		-{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1427	+{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
1428	1428
1429	1429	/* bbit0 limm,limm,s9 00001110sssssss1S111111110001110. */
1430		-{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
	1430	+{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT0, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
1431	1431
1432	1432	/* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110. */
1433		-{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1433	+{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT0, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
1434	1434
1435	1435	/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */
1436		-{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1436	+{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
1437	1437
1438	1438	/* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111. */
1439		-{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1439	+{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
1440	1440
1441	1441	/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */
1442		-{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1442	+{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
1443	1443
1444	1444	/* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111. */
1445		-{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1445	+{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
1446	1446
1447	1447	/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111. */
1448		-{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1448	+{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
1449	1449
1450	1450	/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111. */
1451		-{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1451	+{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
1452	1452
1453	1453	/* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111. */
1454		-{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1454	+{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
1455	1455
1456	1456	/* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111. */
1457		-{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1457	+{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
1458	1458
1459	1459	/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111. */
1460		-{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1460	+{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
1461	1461
1462	1462	/* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111. */
1463		-{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1463	+{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
1464	1464
1465	1465	/* bbit1 limm,limm,s9 00001110sssssss1S111111110001111. */
1466		-{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
	1466	+{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BBIT1, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
1467	1467
1468	1468	/* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111. */
1469		-{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1469	+{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BBIT1, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
1470	1470
1471	1471	/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */
1472	1472	{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},

		@@ -1532,25 +1532,25 @@
1532	1532	{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
1533	1533
1534	1534	/* beq_s s10 1111001sssssssss. */
1535		-{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }},
	1535	+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_EQ }},
1536	1536
1537	1537	/* bge_s s7 1111011001ssssss. */
1538		-{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1538	+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GE }},
1539	1539
1540	1540	/* bgt_s s7 1111011000ssssss. */
1541		-{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1541	+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GT }},
1542	1542
1543	1543	/* bhi_s s7 1111011100ssssss. */
1544		-{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1544	+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HI }},
1545	1545
1546	1546	/* bhs_s s7 1111011101ssssss. */
1547		-{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1547	+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HS }},
1548	1548
1549	1549	/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */
1550		-{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
	1550	+{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BI, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
1551	1551
1552	1552	/* bi limm 00100RRR001001000RRR111110RRRRRR. */
1553		-{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
	1553	+{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BI, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
1554	1554
1555	1555	/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */
1556	1556	{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},

		@@ -1616,10 +1616,10 @@
1616	1616	{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
1617	1617
1618	1618	/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */
1619		-{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
	1619	+{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BIH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
1620	1620
1621	1621	/* bih limm 00100RRR001001010RRR111110RRRRRR. */
1622		-{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
	1622	+{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BIH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
1623	1623
1624	1624	/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1625	1625	{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }},

		@@ -1628,16 +1628,16 @@
1628	1628	{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }},
1629	1629
1630	1630	/* ble_s s7 1111011011ssssss. */
1631		-{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1631	+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LE }},
1632	1632
1633	1633	/* blo_s s7 1111011110ssssss. */
1634		-{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1634	+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LO }},
1635	1635
1636	1636	/* bls_s s7 1111011111ssssss. */
1637		-{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1637	+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LS }},
1638	1638
1639	1639	/* blt_s s7 1111011010ssssss. */
1640		-{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
	1640	+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LT }},
1641	1641
1642	1642	/* bl_s s13 11111sssssssssss. */
1643	1643	{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }},

		@@ -1766,217 +1766,217 @@
1766	1766	{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
1767	1767
1768	1768	/* bne_s s10 1111010sssssssss. */
1769		-{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }},
	1769	+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_NE }},
1770	1770
1771	1771	/* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */
1772		-{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1772	+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
1773	1773
1774	1774	/* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000. */
1775		-{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1775	+{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }},
1776	1776
1777	1777	/* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */
1778		-{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1778	+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
1779	1779
1780	1780	/* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000. */
1781		-{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1781	+{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_EQ }},
1782	1782
1783	1783	/* breq b,limm,s9 00001bbbsssssss1SBBB111110000000. */
1784		-{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1784	+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ }},
1785	1785
1786	1786	/* breq limm,c,s9 00001110sssssss1S111CCCCCC000000. */
1787		-{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1787	+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ }},
1788	1788
1789	1789	/* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000. */
1790		-{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1790	+{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_EQ }},
1791	1791
1792	1792	/* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000. */
1793		-{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1793	+{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_EQ }},
1794	1794
1795	1795	/* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000. */
1796		-{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1796	+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ }},
1797	1797
1798	1798	/* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000. */
1799		-{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1799	+{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_EQ }},
1800	1800
1801	1801	/* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000. */
1802		-{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1802	+{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_EQ }},
1803	1803
1804	1804	/* breq_s b,0,s8 11101bbb0sssssss. */
1805		-{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
	1805	+{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { C_CC_EQ }},
1806	1806
1807	1807	/* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */
1808		-{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1808	+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE }},
1809	1809
1810	1810	/* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011. */
1811		-{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1811	+{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }},
1812	1812
1813	1813	/* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */
1814		-{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1814	+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE }},
1815	1815
1816	1816	/* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011. */
1817		-{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1817	+{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_GE }},
1818	1818
1819	1819	/* brge b,limm,s9 00001bbbsssssss1SBBB111110000011. */
1820		-{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1820	+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE }},
1821	1821
1822	1822	/* brge limm,c,s9 00001110sssssss1S111CCCCCC000011. */
1823		-{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1823	+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE }},
1824	1824
1825	1825	/* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011. */
1826		-{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1826	+{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_GE }},
1827	1827
1828	1828	/* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011. */
1829		-{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1829	+{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_GE }},
1830	1830
1831	1831	/* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011. */
1832		-{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1832	+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE }},
1833	1833
1834	1834	/* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011. */
1835		-{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1835	+{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_GE }},
1836	1836
1837	1837	/* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011. */
1838		-{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1838	+{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_GE }},
1839	1839
1840	1840	/* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */
1841		-{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1841	+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS }},
1842	1842
1843	1843	/* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101. */
1844		-{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1844	+{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }},
1845	1845
1846	1846	/* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */
1847		-{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1847	+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS }},
1848	1848
1849	1849	/* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101. */
1850		-{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1850	+{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_HS }},
1851	1851
1852	1852	/* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101. */
1853		-{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1853	+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS }},
1854	1854
1855	1855	/* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101. */
1856		-{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1856	+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS }},
1857	1857
1858	1858	/* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101. */
1859		-{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1859	+{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_HS }},
1860	1860
1861	1861	/* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101. */
1862		-{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1862	+{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_HS }},
1863	1863
1864	1864	/* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101. */
1865		-{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1865	+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS }},
1866	1866
1867	1867	/* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101. */
1868		-{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1868	+{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_HS }},
1869	1869
1870	1870	/* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101. */
1871		-{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1871	+{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_HS }},
1872	1872
1873	1873	/* brk 00100101011011110000000000111111. */
1874		-{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
	1874	+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { C_CC_HS }},
1875	1875
1876	1876	/* brk_s 0111111111111111. */
1877	1877	{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
1878	1878
1879	1879	/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */
1880		-{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1880	+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO }},
1881	1881
1882	1882	/* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100. */
1883		-{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1883	+{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }},
1884	1884
1885	1885	/* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */
1886		-{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1886	+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO }},
1887	1887
1888	1888	/* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100. */
1889		-{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1889	+{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_LO }},
1890	1890
1891	1891	/* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100. */
1892		-{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1892	+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO }},
1893	1893
1894	1894	/* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100. */
1895		-{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1895	+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO }},
1896	1896
1897	1897	/* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100. */
1898		-{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1898	+{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_LO }},
1899	1899
1900	1900	/* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100. */
1901		-{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1901	+{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_LO }},
1902	1902
1903	1903	/* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100. */
1904		-{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1904	+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO }},
1905	1905
1906	1906	/* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100. */
1907		-{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1907	+{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_LO }},
1908	1908
1909	1909	/* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100. */
1910		-{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1910	+{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_LO }},
1911	1911
1912	1912	/* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */
1913		-{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1913	+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT }},
1914	1914
1915	1915	/* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010. */
1916		-{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1916	+{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }},
1917	1917
1918	1918	/* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */
1919		-{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1919	+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT }},
1920	1920
1921	1921	/* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010. */
1922		-{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1922	+{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_LT }},
1923	1923
1924	1924	/* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010. */
1925		-{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1925	+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT }},
1926	1926
1927	1927	/* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010. */
1928		-{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1928	+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT }},
1929	1929
1930	1930	/* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010. */
1931		-{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1931	+{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_LT }},
1932	1932
1933	1933	/* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010. */
1934		-{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1934	+{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_LT }},
1935	1935
1936	1936	/* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010. */
1937		-{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1937	+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT }},
1938	1938
1939	1939	/* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010. */
1940		-{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1940	+{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_LT }},
1941	1941
1942	1942	/* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010. */
1943		-{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1943	+{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_LT }},
1944	1944
1945	1945	/* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */
1946		-{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
	1946	+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE }},
1947	1947
1948	1948	/* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001. */
1949		-{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
	1949	+{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }},
1950	1950
1951	1951	/* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001. */
1952		-{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
	1952	+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE }},
1953	1953
1954	1954	/* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001. */
1955		-{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
	1955	+{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T, C_CC_NE }},
1956	1956
1957	1957	/* brne b,limm,s9 00001bbbsssssss1SBBB111110000001. */
1958		-{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
	1958	+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE }},
1959	1959
1960	1960	/* brne limm,c,s9 00001110sssssss1S111CCCCCC000001. */
1961		-{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
	1961	+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE }},
1962	1962
1963	1963	/* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001. */
1964		-{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
	1964	+{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T, C_CC_NE }},
1965	1965
1966	1966	/* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001. */
1967		-{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
	1967	+{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T, C_CC_NE }},
1968	1968
1969	1969	/* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001. */
1970		-{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
	1970	+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE }},
1971	1971
1972	1972	/* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001. */
1973		-{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
	1973	+{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T, C_CC_NE }},
1974	1974
1975	1975	/* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001. */
1976		-{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
	1976	+{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T, C_CC_NE }},
1977	1977
1978	1978	/* brne_s b,0,s8 11101bbb1sssssss. */
1979		-{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
	1979	+{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRCC, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { C_CC_NE }},
1980	1980
1981	1981	/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */
1982	1982	{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},

		@@ -6188,11 +6188,11 @@
6188	6188	{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
6189	6189
6190	6190	/* ei_s u10 010111uuuuuuuuuu. */
6191		-{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }},
	6191	+{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, EI, CD2, { UIMM10_6_S }, { 0 }},
6192	6192
6193	6193	/* enter_s u6 110000UU111uuuu0. */
6194		-{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
6195		-{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM6_11_S }, { 0 }},
	6194	+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
	6195	+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ENTER, CD1, { UIMM6_11_S }, { 0 }},
6196	6196
6197	6197	/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */
6198	6198	{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},

		@@ -7875,10 +7875,10 @@
7875	7875	{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }},
7876	7876
7877	7877	/* jeq_s BLINK 0111110011100000. */
7878		-{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
	7878	+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }},
7879	7879
7880	7880	/* jeq_s BLINK 0111110011100000. */
7881		-{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
	7881	+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }},
7882	7882
7883	7883	/* jl c 00100RRR001000100RRRCCCCCCRRRRRR. */
7884	7884	{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},

		@@ -7953,7 +7953,7 @@
7953	7953	{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }},
7954	7954
7955	7955	/* jli_s u10 010110uuuuuuuuuu. */
7956		-{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, CD1, { UIMM10_6_S }, { 0 }},
	7956	+{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JLI, CD1, { UIMM10_6_S }, { 0 }},
7957	7957
7958	7958	/* jl_s b 01111bbb01000000. */
7959	7959	{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},

		@@ -7968,10 +7968,10 @@
7968	7968	{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
7969	7969
7970	7970	/* jne_s BLINK 0111110111100000. */
7971		-{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
	7971	+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }},
7972	7972
7973	7973	/* jne_s BLINK 0111110111100000. */
7974		-{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
	7974	+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }},
7975	7975
7976	7976	/* j_s b 01111bbb00000000. */
7977	7977	{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},

		@@ -8073,70 +8073,70 @@
8073	8073	{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
8074	8074
8075	8075	/* ldb_s a,b,c 01100bbbccc01aaa. */
8076		-{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
	8076	+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B }},
8077	8077
8078	8078	/* ldb_s c,b,u5 10001bbbcccuuuuu. */
8079		-{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
	8079	+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
8080	8080
8081	8081	/* ldb_s b,SP,u7 11000bbb001uuuuu. */
8082		-{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
	8082	+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
8083	8083
8084	8084	/* ldb_s R0,GP,s9 1100101sssssssss. */
8085		-{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { 0 }},
	8085	+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B }},
8086	8086
8087	8087	/* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA. */
8088		-{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }},
	8088	+{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8089	8089
8090	8090	/* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA. */
8091		-{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }},
	8091	+{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
8092	8092
8093	8093	/* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110. */
8094		-{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }},
	8094	+{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8095	8095
8096	8096	/* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110. */
8097		-{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }},
	8097	+{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
8098	8098
8099	8099	/* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA. */
8100		-{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
	8100	+{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8101	8101
8102	8102	/* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110. */
8103		-{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
	8103	+{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8104	8104
8105	8105	/* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA. */
8106		-{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20 }},
	8106	+{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
8107	8107
8108	8108	/* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA. */
8109		-{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }},
	8109	+{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
8110	8110
8111	8111	/* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA. */
8112		-{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }},
	8112	+{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
8113	8113
8114	8114	/* ldd<.di> 0,limm 00010110000000000111DRR110111110. */
8115		-{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20 }},
	8115	+{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20, C_ZZ_D }},
8116	8116
8117	8117	/* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110. */
8118		-{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }},
	8118	+{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8, C_ZZ_D }},
8119	8119
8120	8120	/* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110. */
8121		-{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }},
	8121	+{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16, C_ZZ_D }},
8122	8122
8123	8123	/* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA. */
8124		-{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
	8124	+{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, LOAD, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8125	8125
8126	8126	/* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110. */
8127		-{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }},
	8127	+{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21, C_ZZ_D }},
8128	8128
8129	8129	/* ldh_s a,b,c 01100bbbccc10aaa. */
8130		-{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
	8130	+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }},
8131	8131
8132	8132	/* ldh_s c,b,u6 10010bbbcccuuuuu. */
8133		-{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
	8133	+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
8134	8134
8135	8135	/* ldh_s.X c,b,u6 10011bbbcccuuuuu. */
8136		-{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
	8136	+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD, C_ZZ_H }},
8137	8137
8138	8138	/* ldh_s R0,GP,s10 1100110sssssssss. */
8139		-{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }},
	8139	+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }},
8140	8140
8141	8141	/* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR. */
8142	8142	{ "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, CD2, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},

		@@ -8184,16 +8184,16 @@
8184	8184	{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }},
8185	8185
8186	8186	/* ldw_s a,b,c 01100bbbccc10aaa. */
8187		-{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
	8187	+{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }},
8188	8188
8189	8189	/* ldw_s c,b,u6 10010bbbcccuuuuu. */
8190		-{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
	8190	+{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
8191	8191
8192	8192	/* ldw_s.X c,b,u6 10011bbbcccuuuuu. */
8193		-{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }},
	8193	+{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD, C_ZZ_H }},
8194	8194
8195	8195	/* ldw_s R0,GP,s10 1100110sssssssss. */
8196		-{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }},
	8196	+{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }},
8197	8197
8198	8198	/* ld_s a,b,c 01100bbbccc00aaa. */
8199	8199	{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},

		@@ -8229,8 +8229,8 @@
8229	8229	{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOAD, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
8230	8230
8231	8231	/* leave_s u7 11000UUU110uuuu0. */
8232		-{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
8233		-{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM7_11_S }, { 0 }},
	8232	+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
	8233	+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
8234	8234
8235	8235	/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */
8236	8236	{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},

		@@ -8269,22 +8269,22 @@
8269	8269	{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
8270	8270
8271	8271	/* lp s13 00100RRR101010000RRRssssssSSSSSS. */
8272		-{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }},
	8272	+{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOOP, NONE, { SIMM13_A16_20 }, { 0 }},
8273	8273
8274	8274	/* lp s13 00100RRR10101000RRRRssssssSSSSSS. */
8275		-{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }},
	8275	+{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOOP, NONE, { SIMM13_A16_20 }, { 0 }},
8276	8276
8277	8277	/* lp<cc> u7 00100RRR111010000RRRuuuuuu1QQQQQ. */
8278		-{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }},
	8278	+{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, LOOP, NONE, { UIMM7_A16_20 }, { C_CC }},
8279	8279
8280	8280	/* lp u7 00100RRR011010000RRRuuuuuuRRRRRR. */
8281		-{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }},
	8281	+{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, LOOP, NONE, { UIMM7_A16_20 }, { 0 }},
8282	8282
8283	8283	/* lp<cc> u7 00100RRR11101000RRRRuuuuuu1QQQQQ. */
8284		-{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }},
	8284	+{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOOP, NONE, { UIMM7_A16_20 }, { C_CC }},
8285	8285
8286	8286	/* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR. */
8287		-{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }},
	8287	+{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, LOOP, NONE, { UIMM7_A16_20 }, { 0 }},
8288	8288
8289	8289	/* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR. */
8290	8290	{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},

		@@ -10201,10 +10201,10 @@
10201	10201	{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MOVE, NONE, { ZA_S, LIMM_S }, { 0 }},
10202	10202
10203	10203	/* mov_s.ne b,h 01110bbbhhh111HH. */
10204		-{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, RH_S }, { C_NE }},
	10204	+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, RH_S }, { C_NE, C_CC_NE }},
10205	10205
10206	10206	/* mov_s.ne b,limm 01110bbb11011111. */
10207		-{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, LIMM_S }, { C_NE }},
	10207	+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MOVE, NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE }},
10208	10208
10209	10209	/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */
10210	10210	{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},

		@@ -12889,10 +12889,10 @@
12889	12889	{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
12890	12890
12891	12891	/* pop_s b 11000bbb11000001. */
12892		-{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }},
	12892	+{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, POP, NONE, { RB_S }, { C_AA_AB }},
12893	12893
12894	12894	/* pop_s BLINK 11000RRR11010001. */
12895		-{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
	12895	+{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, POP, NONE, { BLINK_S }, { C_AA_AB }},
12896	12896
12897	12897	/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */
12898	12898	{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},

		@@ -12991,10 +12991,10 @@
12991	12991	{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
12992	12992
12993	12993	/* push_s b 11000bbb11100001. */
12994		-{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }},
	12994	+{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, PUSH, NONE, { RB_S }, { C_AA_AW }},
12995	12995
12996	12996	/* push_s blink 11000RRR11110001. */
12997		-{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
	12997	+{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
12998	12998
12999	12999	/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */
13000	13000	{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},

		@@ -14641,40 +14641,40 @@
14641	14641	{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
14642	14642
14643	14643	/* stb_s c,b,u5 10101bbbcccuuuuu. */
14644		-{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }},
	14644	+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
14645	14645
14646	14646	/* stb_s b,SP,u7 11000bbb011uuuuu. */
14647		-{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
	14647	+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
14648	14648
14649	14649	/* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110. */
14650		-{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
	14650	+{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14651	14651
14652	14652	/* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111. */
14653		-{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }},
	14653	+{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14654	14654
14655	14655	/* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110. */
14656		-{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
	14656	+{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14657	14657
14658	14658	/* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111. */
14659		-{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
	14659	+{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14660	14660
14661	14661	/* std<.di> c,limm 00011110000000000111CCCCCCDRR110. */
14662		-{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26 }},
	14662	+{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
14663	14663
14664	14664	/* std<.di> w6,limm 00011110000000000111wwwwwwDRR111. */
14665		-{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26 }},
	14665	+{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26, C_ZZ_D }},
14666	14666
14667	14667	/* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110. */
14668		-{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
	14668	+{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14669	14669
14670	14670	/* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111. */
14671		-{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
	14671	+{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14672	14672
14673	14673	/* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110. */
14674		-{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }},
	14674	+{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27, C_ZZ_D }},
14675	14675
14676	14676	/* sth_s c,b,u6 10110bbbcccuuuuu. */
14677		-{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
	14677	+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
14678	14678
14679	14679	/* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA. */
14680	14680	{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, STORE, NONE, { RA, UIMM6_A16_21, RB }, { 0 }},

		@@ -14689,7 +14689,7 @@
14689	14689	{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, STORE, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }},
14690	14690
14691	14691	/* stw_s c,b,u6 10110bbbcccuuuuu. */
14692		-{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }},
	14692	+{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
14693	14693
14694	14694	/* st_s b,SP,u7 11000bbb010uuuuu. */
14695	14695	{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},

		@@ -14701,244 +14701,244 @@
14701	14701	{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, STORE, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
14702	14702
14703	14703	/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */
14704		-{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
	14704	+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }},
14705	14705
14706	14706	/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */
14707		-{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
	14707	+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }},
14708	14708
14709	14709	/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */
14710		-{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
	14710	+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
14711	14711
14712	14712	/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
14713		-{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
	14713	+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
14714	14714
14715	14715	/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */
14716		-{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
	14716	+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
14717	14717
14718	14718	/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */
14719		-{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
	14719	+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
14720	14720
14721	14721	/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */
14722		-{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
	14722	+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
14723	14723
14724	14724	/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */
14725		-{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
	14725	+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }},
14726	14726
14727	14727	/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
14728		-{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
	14728	+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }},
14729	14729
14730	14730	/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */
14731		-{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
	14731	+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
14732	14732
14733	14733	/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */
14734		-{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
	14734	+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
14735	14735
14736	14736	/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */
14737		-{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
	14737	+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
14738	14738
14739	14739	/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */
14740		-{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
	14740	+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
14741	14741
14742	14742	/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */
14743		-{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
	14743	+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
14744	14744
14745	14745	/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */
14746		-{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
	14746	+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
14747	14747
14748	14748	/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */
14749		-{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
	14749	+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
14750	14750
14751	14751	/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */
14752		-{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
	14752	+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
14753	14753
14754	14754	/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */
14755		-{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
	14755	+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
14756	14756
14757	14757	/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */
14758		-{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
	14758	+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
14759	14759
14760	14760	/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */
14761		-{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
	14761	+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
14762	14762
14763	14763	/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */
14764		-{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
	14764	+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }},
14765	14765
14766	14766	/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */
14767		-{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
	14767	+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }},
14768	14768
14769	14769	/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */
14770		-{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
	14770	+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
14771	14771
14772	14772	/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */
14773		-{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
	14773	+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
14774	14774
14775	14775	/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */
14776		-{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
	14776	+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
14777	14777
14778	14778	/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */
14779		-{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
	14779	+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
14780	14780
14781	14781	/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */
14782		-{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
	14782	+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
14783	14783
14784	14784	/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */
14785		-{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
	14785	+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }},
14786	14786
14787	14787	/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */
14788		-{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
	14788	+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }},
14789	14789
14790	14790	/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */
14791		-{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
	14791	+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
14792	14792
14793	14793	/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */
14794		-{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
	14794	+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
14795	14795
14796	14796	/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */
14797		-{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
	14797	+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
14798	14798
14799	14799	/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */
14800		-{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
	14800	+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
14801	14801
14802	14802	/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */
14803		-{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
	14803	+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
14804	14804
14805	14805	/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */
14806		-{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
	14806	+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
14807	14807
14808	14808	/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */
14809		-{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
	14809	+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
14810	14810
14811	14811	/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */
14812		-{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
	14812	+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
14813	14813
14814	14814	/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */
14815		-{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
	14815	+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
14816	14816
14817	14817	/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */
14818		-{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
	14818	+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
14819	14819
14820	14820	/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */
14821		-{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
	14821	+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
14822	14822
14823	14823	/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */
14824		-{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
	14824	+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }},
14825	14825
14826	14826	/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */
14827		-{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
	14827	+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }},
14828	14828
14829	14829	/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */
14830		-{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
	14830	+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
14831	14831
14832	14832	/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */
14833		-{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
	14833	+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
14834	14834
14835	14835	/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */
14836		-{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
	14836	+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
14837	14837
14838	14838	/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */
14839		-{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
	14839	+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
14840	14840
14841	14841	/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */
14842		-{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
	14842	+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
14843	14843
14844	14844	/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */
14845		-{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
	14845	+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }},
14846	14846
14847	14847	/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */
14848		-{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
	14848	+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }},
14849	14849
14850	14850	/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */
14851		-{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
	14851	+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
14852	14852
14853	14853	/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */
14854		-{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
	14854	+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
14855	14855
14856	14856	/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */
14857		-{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
	14857	+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
14858	14858
14859	14859	/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */
14860		-{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
	14860	+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
14861	14861
14862	14862	/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */
14863		-{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
	14863	+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
14864	14864
14865	14865	/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */
14866		-{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
	14866	+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
14867	14867
14868	14868	/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */
14869		-{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
	14869	+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
14870	14870
14871	14871	/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */
14872		-{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
	14872	+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
14873	14873
14874	14874	/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */
14875		-{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
	14875	+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
14876	14876
14877	14877	/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */
14878		-{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
	14878	+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
14879	14879
14880	14880	/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */
14881		-{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
	14881	+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
14882	14882
14883	14883	/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */
14884		-{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }},
	14884	+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, RC }, { C_F }},
14885	14885
14886	14886	/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */
14887		-{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }},
	14887	+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, RC }, { C_F }},
14888	14888
14889	14889	/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */
14890		-{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
	14890	+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
14891	14891
14892	14892	/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */
14893		-{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
	14893	+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
14894	14894
14895	14895	/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */
14896		-{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
	14896	+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
14897	14897
14898	14898	/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */
14899		-{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
	14899	+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
14900	14900
14901	14901	/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */
14902		-{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
	14902	+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
14903	14903
14904	14904	/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */
14905		-{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
	14905	+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, RC }, { C_F }},
14906	14906
14907	14907	/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */
14908		-{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
	14908	+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, RB, LIMM }, { C_F }},
14909	14909
14910	14910	/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */
14911		-{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
	14911	+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
14912	14912
14913	14913	/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */
14914		-{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
	14914	+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
14915	14915
14916	14916	/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */
14917		-{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
	14917	+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
14918	14918
14919	14919	/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */
14920		-{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
	14920	+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
14921	14921
14922	14922	/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */
14923		-{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
	14923	+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
14924	14924
14925	14925	/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */
14926		-{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
	14926	+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
14927	14927
14928	14928	/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */
14929		-{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
	14929	+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
14930	14930
14931	14931	/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */
14932		-{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
	14932	+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
14933	14933
14934	14934	/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */
14935		-{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
	14935	+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
14936	14936
14937	14937	/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */
14938		-{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
	14938	+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
14939	14939
14940	14940	/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */
14941		-{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
	14941	+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
14942	14942
14943	14943	/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */
14944	14944	{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }},

		@@ -15064,22 +15064,22 @@
15064	15064	{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
15065	15065
15066	15066	/* sub_s b,b,c 01111bbbccc00010. */
15067		-{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
	15067	+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
15068	15068
15069	15069	/* sub_s a,b,c 01001bbbccc10aaa. */
15070		-{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, CD2, { RA_S, RB_S, RC_S }, { 0 }},
	15070	+{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, CD2, { RA_S, RB_S, RC_S }, { 0 }},
15071	15071
15072	15072	/* sub_s c,b,u3 01101bbbccc01uuu. */
15073		-{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
	15073	+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
15074	15074
15075	15075	/* sub_s b,b,u5 10111bbb011uuuuu. */
15076		-{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
	15076	+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
15077	15077
15078	15078	/* sub_s SP,SP,u7 11000001101uuuuu. */
15079		-{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
	15079	+{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }},
15080	15080
15081	15081	/* sub_s.ne b,b,b 01111bbb11000000. */
15082		-{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE }},
	15082	+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, SUB, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE, C_CC_NE }},
15083	15083
15084	15084	/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */
15085	15085	{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }},

binutils_os216 Fork

提交

标签

Frequently used words (click to add to your profile)

Commit MetaInfo

Log Message

更改概述

差异

binutils_os216
Fork