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testsuite: clarify scan-dump file globbing behavior

The test commands for scanning optimization dump files
perform globbing on the argument that specifies the suffix
of the dump files to be scanned. This behavior is currently
undocumented. Furthermore, the current implementation of
"scan-dump" and similar procedures yields an error whenever
the file name globbing matches more than one file (due to an
attempt to call "open" on multiple files) while a failure to
match any file results in an unresolved test.

This commit documents the globbing behavior. The dump
scanning procedures are changed to make the test unresolved
if globbing matches more than one file.

This is a backport from master
(commit d4501bbedca267f2051e4f57415d6d2a61306915).

gcc/ChangeLog:

2020-07-02 Frederik Harwath <frederik@codesourcery.com>

* doc/sourcebuild.texi: Describe globbing of the
dump file scanning commands "suffix" argument.

gcc/testsuite/ChangeLog:

2020-07-02 Frederik Harwath <frederik@codesourcery.com>

* lib/scandump.exp (glob-dump-file): New proc.
(scan-dump): Use glob-dump-file for file name expansion.
(scan-dump-times): Likewise.
(scan-dump-dem): Likewise.
(scan-dump-dem-not): Likewise.

Fix failure in gfortran.dg/gomp/combined-if.f90 test

Enabling nvptx offloading results in extra '#pragma omp simd' statements
in the tree dump with an extra '_simt_'.

This is a backport from master
(commit 0fce12c0920c12492c878c0ca5f639f93b93f183).

2020-06-26 Kwok Cheung Yeung <kcy@codesourcery.com>

gcc/testsuite/
* gfortran.dg/gomp/combined-if.f90: Adjust expected number
of matches depending on whether nvptx offloading is supported.
* lib/target-supports.exp
(check_effective_target_offload_nvptx): New.

fortran: Fix ICE when 'if' clause used with 'target parallel' (PR95869)

This is a backport from master
(commit f530bac8a11da9c85bdd8e58d589747f9825e38d).

2020-06-25 Tobias Burnus <tobias@codesourcery.com>
Kwok Cheung Yeung <kcy@codesourery.com>

gcc/fortran/

PR fortran/95869
* trans-openmp.c (gfc_trans_omp_target): Use correct scoping block.

gcc/testsuite/

PR fortran/95869
* gfortran.dg/gomp/combined-if.f90 (test_target_parallel): Re-enable.
* gfortran.dg/gomp/pr95869.f90: New.

fortran: Apply if clause to all sub-constructs in combined OpenMP constructs

The unmodified 'if' clause should be applied to all the sub-constructs that
accept an 'if' clause in a combined OpenMP construct, and not just to the
'parallel' sub-construct.

This is a backport from master
(commit 1dfa89b0355520ca501054726f25de9733796f48).

2020-06-25 Kwok Cheung Yeung <kcy@codesourcery.com>

gcc/fortran/

* trans-openmp.c (gfc_split_omp_clauses): Add if clause
to target and simd sub-constructs.

gcc/testsuite/

* gfortran.dg/gomp/combined-if.f90: New.

Reviewed-by: Jakub Jelinek <jakub@redhat.com>

Merge remote-tracking branch 'origin/releases/gcc-10' into devel/omp/gcc-10

Merge up to 6e81b0cf4ff75f65edfd2d83bfa2933f35ae66af (June 18, 2020)

identify lfs prefixed case PR95347

The same problem also arises for plfs where prefixed_load_p()
doesn't recognize it so we get just lfs in the asm output
with an @pcrel address.

Backport from master
2020-06-03 Aaron Sawdey <acsawdey@linux.ibm.com>

PR target/95347
* config/rs6000/rs6000.c (is_stfs_insn): Rename to
is_lfs_stfs_insn and make it recognize lfs as well.
(prefixed_store_p): Use is_lfs_stfs_insn().
(prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs.

Correctly identify stfs if prefixed

Because reg_to_non_prefixed() only looks at the register being used, it
doesn't get the right answer for stfs, which leads to us not seeing
that it has a PCREL symbol ref. This patch works around this by
introducing a helper function that inspects the insn to see if it is in
fact a stfs. Then if we use NON_PREFIXED_DEFAULT, address_to_insn_form()
can see that it has the PCREL symbol ref.

Backport from master
2020-06-02 Aaron Sawdey <acsawdey@linux.ibm.com>

PR target/95347
* config/rs6000/rs6000.c (prefixed_store_p): Add special case
for stfs.
(is_stfs_insn): New helper function.

amdgcn: Switch to HSACO v3 binary format

This upgrades the compiler to emit HSA Code Object v3 binaries. This means
changing the assembler directives, and linker command line options.

The gcn-run and libgomp loaders need corresponding alterations. The
relocations no longer need to be fixed up manually, and the kernel symbol
names have changed slightly.

This move makes the binaries compatible with the new rocgdb from ROCm 3.5.

This is a backport from GCC 11.

2020-06-18 Andrew Stubbs <ams@codesourcery.com>

gcc/
* config/gcn/gcn-hsa.h (TEXT_SECTION_ASM_OP): Use ".text".
(BSS_SECTION_ASM_OP): Use ".bss".
(ASM_SPEC): Remove "-mattr=-code-object-v3".
(LINK_SPEC): Add "--export-dynamic".
* config/gcn/gcn-opts.h (processor_type): Replace PROCESSOR_VEGA with
PROCESSOR_VEGA10 and PROCESSOR_VEGA20.
* config/gcn/gcn-run.c (HSA_RUNTIME_LIB): Use ".so.1" variant.
(load_image): Remove obsolete relocation handling.
Add ".kd" suffix to the symbol names.
* config/gcn/gcn.c (MAX_NORMAL_SGPR_COUNT): Set to 62.
(gcn_option_override): Update gcn_isa test.
(gcn_kernel_arg_types): Update all the assembler directives.
Remove the obsolete options.
(gcn_conditional_register_usage): Update MAX_NORMAL_SGPR_COUNT usage.
(gcn_omp_device_kind_arch_isa): Handle PROCESSOR_VEGA10 and
PROCESSOR_VEGA20.
(output_file_start): Rework assembler file header.
(gcn_hsa_declare_function_name): Rework kernel metadata.
* config/gcn/gcn.h (GCN_KERNEL_ARG_TYPES): Set to 16.
* config/gcn/gcn.opt (PROCESSOR_VEGA): Remove enum.
(PROCESSOR_VEGA10): New enum value.
(PROCESSOR_VEGA20): New enum value.

libgomp/
* plugin/plugin-gcn.c (init_environment_variables): Use ".so.1"
variant for HSA_RUNTIME_LIB name.
(find_executable_symbol_1): Delete.
(find_executable_symbol): Delete.
(init_kernel_properties): Add ".kd" suffix to symbol names.
(find_load_offset): Delete.
(create_and_finalize_hsa_program): Remove relocation handling.

(cherry picked from commit f062c3f11505b70c5275e5bc0e52f3e441f8afbc)

forwprop: simplify_vector_constructor follow-up fix [PR95713]

As the following testcase shows, the exception for the aarch64
vec_pack_trunc_di is not sufficient on x86, the halfvectype
"vectors" have SImode but the x86 vec_pack_trunc_si meant for
the bool bitmasks combines 2x SImode into DImode, while in the
testcase the halfvectype is 1x SImode "vector" with SImode and
result is 2x HImode "vector" with SImode.

Richard Sandiford's reply:
FWIW, since the aarch64 case was only found by inspection and might
not be useful, personally I'd prefer to drop that case after all.

2020-06-18 Jakub Jelinek <jakub@redhat.com>

PR target/95713
* tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow
scalar mode halfvectype other than vector boolean for
VEC_PACK_TRUNC_EXPR.

* gcc.dg/pr95713.c: New test.

(cherry picked from commit 9a875db43cd4210843c480c8df26a1d6624d057d)

[PATCH][GCC] arm: Fix the MVE ACLE vaddq_m polymorphic variants.

Hello,

This patch fixes the MVE ACLE vaddq_m polymorphic variants by modifying the corresponding
intrinsic parameters and vaddq_m polymorphic variant's _Generic case entries in "arm_mve.h"
header file.

2020-06-04 Srinath Parvathaneni <srinath.parvathaneni@arm.com>

gcc/
* config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic
arguments.
(__arm_vaddq_m_n_s32): Likewise.
(__arm_vaddq_m_n_s16): Likewise.
(__arm_vaddq_m_n_u8): Likewise.
(__arm_vaddq_m_n_u32): Likewise.
(__arm_vaddq_m_n_u16): Likewise.
(__arm_vaddq_m): Modify polymorphic variant.

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: New test.

(cherry picked from commit dc39db873670bea8d8e655444387ceaa53a01a79)

[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.

This patch modifies the MVE scalar shift RTL patterns. The current patterns
have wrong constraints and predicates due to which the values returned from
MVE scalar shift instructions are overwritten in the code-gen.

example:
$ cat x.c
int32_t foo(int64_t acc, int shift)
{
return sqrshrl_sat48 (acc, shift);
}

Code-gen before applying this patch:
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mfloat-abi=hard -O2 -S
$ cat x.s
foo:
push {r4, r5}
sqrshrl r0, r1, #48, r2 ----> (a)
mov r0, r4 ----> (b)
pop {r4, r5}
bx lr

Code-gen after applying this patch:
foo:
sqrshrl r0, r1, #48, r2
bx lr

In the current compiler the return value (r0) from sqrshrl (a) is getting
overwritten by the mov statement (b).
This patch fixes above issue.

2020-06-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>

gcc/
* config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate
and constraint of all the operands.
(mve_sqrshrl_sat<supf>_di): Likewise.
(mve_uqrshl_si): Likewise.
(mve_sqrshr_si): Likewise.
(mve_uqshll_di): Likewise.
(mve_urshrl_di): Likewise.
(mve_uqshl_si): Likewise.
(mve_urshr_si): Likewise.
(mve_sqshl_si): Likewise.
(mve_srshr_si): Likewise.
(mve_srshrl_di): Likewise.
(mve_sqshll_di): Likewise.
* config/arm/predicates.md (arm_low_register_operand): Define.

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.

(cherry picked from commit 6af598703f919b56f628c496843cdfe6f0cb8276)

Daily bump.

Add 'dg-do run' to 'libgomp.fortran/use_device_ptr-optional-3.f90' [PR94848]

Fix-up for r279858/commit f760c0c77fe350616da9dbeaea16442b0acfb09c "Fortran]
OpenMP/OpenACC – fix more issues with OPTIONAL".

With offloading enabled, we then saw:

PASS: libgomp.fortran/use_device_ptr-optional-3.f90 -O0 (test for excess errors)
PASS: libgomp.fortran/use_device_ptr-optional-3.f90 -O0 execution test
PASS: libgomp.fortran/use_device_ptr-optional-3.f90 -O1 (test for excess errors)
PASS: libgomp.fortran/use_device_ptr-optional-3.f90 -O1 execution test
FAIL: libgomp.fortran/use_device_ptr-optional-3.f90 -O2 (test for excess errors)
UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90 -O2 compilation failed to produce executable
FAIL: libgomp.fortran/use_device_ptr-optional-3.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors)
UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions compilation failed to produce executable
FAIL: libgomp.fortran/use_device_ptr-optional-3.f90 -O3 -g (test for excess errors)
UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90 -O3 -g compilation failed to produce executable
FAIL: libgomp.fortran/use_device_ptr-optional-3.f90 -Os (test for excess errors)
UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90 -Os compilation failed to produce executable

... due to:

/tmp/cciVc43I.o:(.gnu.offload_vars+0x10): undefined reference to `A.12.4064'
[...]

..., but after the recent PR94848, PR95551 changes, that problem is now gone.

libgomp/
PR lto/94848
* testsuite/libgomp.fortran/use_device_ptr-optional-3.f90: Add
'dg-do run'.

(cherry picked from commit 5864930754f63e2dcef9606f2514ae20e80f436e)

hurd: libgcc unwinding support over signal trampolines

libgcc/
* config.host (md_unwind_header) <i[34567]86-*-gnu*>: Set to
'i386/gnu-unwind.h'
* config/i386/gnu-unwind.h: New file.

Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
(cherry picked from commit 5e2eebc80d6eeca24745c27a925afdb64292ed22)

[HSA] Avoid ICE when "HSA does not implement indirect calls"

Made apparent by recent commit dc703151d4f4560e647649506d5b4ceb0ee11e90
"openmp: Implement discovery of implicit declare target to clauses":

+FAIL: libgomp.c/target-39.c (internal compiler error)
+FAIL: libgomp.c/target-39.c (test for excess errors)
+UNRESOLVED: libgomp.c/target-39.c compilation failed to produce executable

This is in a '--enable-offload-targets=[...],hsa' build, with '-foffload=hsa'
enabled (by default).

during GIMPLE pass: hsagen
source-gcc/libgomp/testsuite/libgomp.c/target-39.c: In function ‘main._omp_fn.0.hsa.0’:
source-gcc/libgomp/testsuite/libgomp.c/target-39.c:23:11: internal compiler error: Segmentation fault
23 | #pragma omp target map(from:err)
| ^~~
[...]

GDB:

Program received signal SIGSEGV, Segmentation fault.
fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
6267 return (fndecl_built_in_p (node, BUILT_IN_NORMAL)
(gdb) bt
#0 fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
#1 0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5304
#2 0x0000000000b1aca7 in gen_hsa_insns_for_gimple_stmt (stmt=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5770
#3 0x0000000000b1bd21 in gen_body_from_gimple () at [...]/source-gcc/gcc/hsa-gen.c:5999
#4 0x0000000000b1dbd2 in generate_hsa (kernel=<optimized out>) at [...]/source-gcc/gcc/hsa-gen.c:6596
#5 0x0000000000b1de66 in (anonymous namespace)::pass_gen_hsail::execute (this=0x2a2aac0) at [...]/source-gcc/gcc/hsa-gen.c:6680
#6 0x0000000000d06f90 in execute_one_pass (pass=pass@entry=0x2a2aac0) at [...]/source-gcc/gcc/passes.c:2502
[...]
(gdb) up
#1 0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at /home/thomas/tmp/source/gcc/build/track-slim-omp/source-gcc/gcc/hsa-gen.c:5304
5304 if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
(gdb) print function_decl
$1 = (tree) 0x0
(gdb) list
5299 if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
5300 {
5301 tree function_decl = gimple_call_fndecl (stmt);
5302 /* Prefetch pass can create type-mismatching prefetch builtin calls which
5303 fail the gimple_call_builtin_p test above. Handle them here. */
5304 if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
5305 return;
5306
5307 if (function_decl == NULL_TREE)
5308 {

The problem is present already since 2016-11-23 commit
56b1c60e412fcf1245b4780871553cbdebb956a3 (r242761) "Merge from HSA branch to
trunk", and the fix obvious enough.

gcc/
* hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl ==
NULL_TREE' check earlier.
gcc/testsuite/
* c-c++-common/gomp/hsa-indirect-call-1.c: New file.

(cherry picked from commit 973bce0fb50bbfd91f47238b82b99935525716ad)

PR fortran/95088 - Buffer overflows with PDTs, submodules and long symbols

With PDTs (parameterized derived types) and submodules, name mangling
results in variably long internal symbols. Instead of using a fixed-size
intermediate buffer, which is actually not really needed, just use a
pointer to strings.

2020-06-14 Harald Anlauf <anlauf@gmx.de>

gcc/fortran/
PR fortran/95088
* class.c (get_unique_type_string): Replace use of fixed size
buffer by internally passing a pointer to strings.

(cherry picked from commit 3ee9d82484bdc0ae5b1b21f4a3d8ff46d40e36fd)

c++: ICE with IMPLICIT_CONV_EXPR in array subscript [PR95508]

Since r10-7096 convert_like, when called in a template, creates an
IMPLICIT_CONV_EXPR when we're converting to/from array type.

In this test, we have e[f], and we're converting f (of type class A) to
int, so convert_like in build_new_op_1 created the IMPLICIT_CONV_EXPR
that got into cp_build_array_ref which calls maybe_constant_value. My
patch above failed to adjust this spot to call fold_non_dependent_expr
instead, which can handle codes like I_C_E in a template. Fixed by
using a new function maybe_fold_non_dependent_expr, which, if the expr
can't be evaluated to a constant, returns the original expression.

gcc/cp/ChangeLog:

PR c++/95508
* constexpr.c (maybe_fold_non_dependent_expr): New.
* cp-tree.h (maybe_fold_non_dependent_expr): Declare.
* typeck.c (cp_build_array_ref): Call maybe_fold_non_dependent_expr
instead of maybe_constant_value.

gcc/testsuite/ChangeLog:

PR c++/95508
* g++.dg/template/conv16.C: New test.

Daily bump.

OpenACC/Fortran: permit 'routine' inside PURE

gcc/fortran/ChangeLog

* parse.c (decode_oacc_directive): Permit 'acc routine' also
inside pure procedures.
* openmp.c (gfc_match_oacc_routine): Inside pure procedures
do not permit gang, worker or vector clauses.

libgomp/ChangeLog:

* testsuite/libgomp.oacc-fortran/routine-10.f90: New test.

gcc/testsuite/ChangeLog:

* gfortran.dg/goacc/pure-elemental-procedures-2.f90: New test.

Reviewed-by: Thomas Schwinge <thomas@codesourcery.com>
(cherry picked from commit 12df77ab6df4b91d4770240bcc4ab443e4bb18b9)

arm: Fix the MVE ACLE vbicq intrinsics.

Following MVE intrinsic testcases are failing in GCC testsuite.

Directory: gcc.target/arm/mve/intrinsics/
Testcases: vbicq_f16.c, vbicq_f32.c, vbicq_s16.c, vbicq_s32.c, vbicq_s8.c
,vbicq_u16.c, vbicq_u32.c and vbicq_u8.c.

This patch fixes the vbicq intrinsics by modifying the intrinsic parameters
and polymorphic variants in "arm_mve.h" header file.

Backported from mainline
2020-06-04 Srinath Parvathaneni <srinath.parvathaneni@arm.com>

gcc/
* config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic
arguments.
(__arm_vbicq_n_s16): Likewise.
(__arm_vbicq_n_u32): Likewise.
(__arm_vbicq_n_s32): Likewise.
(__arm_vbicq): Modify polymorphic variant.

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Modify.
* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.

arm: Correct the grouping of operands in MVE vector scatter store intrinsics (PR94735).

The operands in RTL patterns of MVE vector scatter store intrinsics are
wrongly grouped, because of which few vector loads and stores instructions
are wrongly getting optimized out with -O2.

A new predicate "mve_scatter_memory" is defined in this patch, this predicate
returns TRUE on matching: (mem(reg)) for MVE scatter store intrinsics.
This patch fixes the issue by adding define_expand pattern with
"mve_scatter_memory" predicate and calls the corresponding define_insn by
passing register_operand as first argument. This register_operand is extracted
from the operand with "mve_scatter_memory" predicate in define_expand pattern.

Backported from mainline
2020-06-04 Srinath Parvathaneni <srinath.parvathaneni@arm.com>

gcc/
PR target/94735
* config/arm/predicates.md (mve_scatter_memory): Define to
match (mem (reg)) for scatter store memory.
* config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>): Modify
define_insn to define_expand.
(mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
(mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
(mve_vstrhq_scatter_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
(mve_vstrwq_scatter_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
(mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for scatter
stores.
(mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
(mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
(mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
(mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.

gcc/testsuite/
PR target/94735
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base_p.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset_p.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c:
Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c:
Likewise.

arm: Fix unintentional fall throughs in arm.c

This small patch fix some unintentional fall-throughs in
`mve_vector_mem_operand'.

Backported from mainline
2020-05-28 Andrea Corallo <andrea.corallo@arm.com>

gcc/
* config/arm/arm.c (mve_vector_mem_operand): Fix unwanted
fall-throughs.

arm: Fix the wrong code-gen generated by MVE vector load/store intrinsics (PR94959).

Few MVE intrinsics like vldrbq_s32, vldrhq_s32 etc., the assembler instructions
generated by current compiler are wrong.
eg: vldrbq_s32 generates an assembly instructions `vldrb.s32 q0,[ip]`.
But as per Arm-arm second argument in above instructions must also be a low
register (<= r7). This patch fixes this issue by creating a new predicate
"mve_memory_operand" and constraint "Ux" which allows low registers as arguments
to the generated instructions depending on the mode of the argument. A new constraint
"Ul" is created to handle loading to PC-relative addressing modes for vector
store/load intrinsiscs.
All the corresponding MVE intrinsic generating wrong code-gen as vldrbq_s32
are modified in this patch.

Backported from mainline
2020-05-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>

gcc/
PR target/94959
* config/arm/arm-protos.h (arm_mode_base_reg_class): Function
declaration.
(mve_vector_mem_operand): Likewise.
* config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check
the load from memory to a core register is legitimate for give mode.
(mve_vector_mem_operand): Define function.
(arm_print_operand): Modify comment.
(arm_mode_base_reg_class): Define.
* config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for
TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE.
* config/arm/constraints.md (Ux): Likewise.
(Ul): Likewise.
* config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also
add support for missing Vector Store Register and Vector Load Register.
Add a new alternative to support load from memory to PC (or label) in
vector store/load.
(mve_vstrbq_<supf><mode>): Modify constraint Us to Ux.
(mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux.
(mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vldrhq_z_fv8hf): Likewise.
(mve_vldrhq_z_<supf><mode>): Likewise.
(mve_vldrwq_fv4sf): Likewise.
(mve_vldrwq_<supf>v4si): Likewise.
(mve_vldrwq_z_fv4sf): Likewise.
(mve_vldrwq_z_<supf>v4si): Likewise.
(mve_vld1q_f<mode>): Modify constriant Us to Ux.
(mve_vld1q_<supf><mode>): Likewise.
(mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand.
(mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to
mve_memory_operand and also modify the MVE instructions to emit.
(mve_vstrhq_p_<supf><mode>): Likewise.
(mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
mve_memory_operand.
(mve_vstrwq_fv4sf): Modify constriant Us to Ux.
(mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE
instructions to emit.
(mve_vstrwq_p_<supf>v4si): Likewise.
(mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux.
* config/arm/predicates.md (mve_memory_operand): Define.

gcc/testsuite/
PR target/94959
* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Modify.
* gcc.target/arm/mve/intrinsics/mve_vldr.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vldr_z.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstr.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstr_p.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_f16.c: Modify.
* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise.

Co-Authored-By: Andre Vieira <andre.simoesdiasvieira@arm.com>

testsuite: Add offloading_enabled check and use it for xfail (PR95622)

gcc/testsuite/ChangeLog:

PR middle-end/95622
* lib/target-supports.exp (check_effective_target_offloading_enabled):
New.
* c-c++-common/goacc/kernels-alias-ipa-pta-2.c: Use it for xfail.
* c-c++-common/goacc/kernels-alias-ipa-pta-4.c: Likewise.
* c-c++-common/goacc/kernels-alias-ipa-pta.c: Likewise.

Reviewed-by: Thomas Schwinge <thomas@codesourcery.com>
(cherry picked from commit e70fbee1a3dd9fdeb661366dbf3096d76c4e2d6e)

Daily bump.

Merge remote-tracking branch 'origin/releases/gcc-10' into devel/omp/gcc-10

Merged up to 8a3453786c3c2d6343c5258e564ad139d5ad116f (Jun 15, 2020)

Merge branch 'releases/gcc-10' into devel/omp/gcc-10

Merged up to e09d626551fef9b5719073427170d11e97038c44 (Jun 14, 2020)

amdgcn: use unsigned extend for lshiftrt

This fixes a wrong-code logic error in a previous patch.
Detected by gcc.c-torture/execute/pr53645-2.c.

gcc/
* config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.

(cherry picked from commit b8db70e1f1cea312888470e1911c7b5e32333c61)

openmp: ensure variables in offload table are streamed out (PRs 94848 + 95551)

gcc/ChangeLog:

* omp-offload.c (add_decls_addresses_to_decl_constructor,
omp_finish_file): With in_lto_p, stream out all offload-table
items even if the symtab_node does not exist.

(cherry picked from commit bf4ab2689bb586971d5b2ab6b13d078cd7ac45af)

openmp: ensure variables in offload table are streamed out (PRs 94848 + 95551)

gcc/ChangeLog:

PR lto/94848
PR middle-end/95551
* omp-offload.c (add_decls_addresses_to_decl_constructor,
omp_finish_file): Skip removed items.
* lto-cgraph.c (output_offload_tables): Likewise; set force_output
to this node for variables and functions.

libgomp/ChangeLog:

PR lto/94848
PR middle-end/95551
* testsuite/libgomp.fortran/target-var.f90: New test.

(cherry picked from commit 1c0fdaf79e3618fd7512608a2e5c62b6b306e9e8)