hardware/intel/intel-driver
修订版 | 9e924b4d1a1862efb6ab20dd92dbb233f3acf19c (tree) |
---|---|
时间 | 2016-05-09 17:52:22 |
作者 | Xiang, Haihao <haihao.xiang@inte...> |
Commiter | Xiang, Haihao |
Add 'struct i965_gpe_resource' and related utility functions
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-By: Sean V Kelley <sean.v.kelley@intel.com>
@@ -1308,3 +1308,119 @@ gen9_gpe_pipeline_end(VADriverContextP ctx, | ||
1308 | 1308 | GEN9_FORCE_MEDIA_AWAKE_MASK); |
1309 | 1309 | ADVANCE_BATCH(batch); |
1310 | 1310 | } |
1311 | + | |
1312 | +Bool | |
1313 | +i965_allocate_gpe_resource(dri_bufmgr *bufmgr, | |
1314 | + struct i965_gpe_resource *res, | |
1315 | + const char *name) | |
1316 | +{ | |
1317 | + res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096); | |
1318 | + res->map = NULL; | |
1319 | + | |
1320 | + return (res->bo != NULL); | |
1321 | +} | |
1322 | + | |
1323 | +void | |
1324 | +i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res, | |
1325 | + struct object_surface *obj_surface) | |
1326 | +{ | |
1327 | + unsigned int swizzle; | |
1328 | + | |
1329 | + res->type = I965_GPE_RESOURCE_2D; | |
1330 | + res->width = obj_surface->orig_width; | |
1331 | + res->height = obj_surface->orig_height; | |
1332 | + res->pitch = obj_surface->width; | |
1333 | + res->size = obj_surface->size; | |
1334 | + res->cb_cr_pitch = obj_surface->cb_cr_pitch; | |
1335 | + res->x_cb_offset = obj_surface->x_cb_offset; | |
1336 | + res->y_cb_offset = obj_surface->y_cb_offset; | |
1337 | + res->bo = obj_surface->bo; | |
1338 | + res->map = NULL; | |
1339 | + | |
1340 | + dri_bo_reference(res->bo); | |
1341 | + dri_bo_get_tiling(obj_surface->bo, &res->tiling, &swizzle); | |
1342 | +} | |
1343 | + | |
1344 | +void | |
1345 | +i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res, | |
1346 | + dri_bo *bo) | |
1347 | +{ | |
1348 | + unsigned int swizzle; | |
1349 | + | |
1350 | + res->type = I965_GPE_RESOURCE_BUFFER; | |
1351 | + res->width = bo->size; | |
1352 | + res->height = 1; | |
1353 | + res->pitch = res->width; | |
1354 | + res->size = res->pitch * res->width; | |
1355 | + res->bo = bo; | |
1356 | + res->map = NULL; | |
1357 | + | |
1358 | + dri_bo_reference(res->bo); | |
1359 | + dri_bo_get_tiling(res->bo, &res->tiling, &swizzle); | |
1360 | +} | |
1361 | + | |
1362 | +void | |
1363 | +i965_gpe_dri_object_to_2d_gpe_resource(struct i965_gpe_resource *res, | |
1364 | + dri_bo *bo, | |
1365 | + unsigned int width, | |
1366 | + unsigned int height, | |
1367 | + unsigned int pitch) | |
1368 | +{ | |
1369 | + unsigned int swizzle; | |
1370 | + | |
1371 | + res->type = I965_GPE_RESOURCE_2D; | |
1372 | + res->width = width; | |
1373 | + res->height = height; | |
1374 | + res->pitch = pitch; | |
1375 | + res->size = res->pitch * res->width; | |
1376 | + res->bo = bo; | |
1377 | + res->map = NULL; | |
1378 | + | |
1379 | + dri_bo_reference(res->bo); | |
1380 | + dri_bo_get_tiling(res->bo, &res->tiling, &swizzle); | |
1381 | +} | |
1382 | + | |
1383 | +void | |
1384 | +i965_zero_gpe_resource(struct i965_gpe_resource *res) | |
1385 | +{ | |
1386 | + if (res->bo) { | |
1387 | + dri_bo_map(res->bo, 1); | |
1388 | + memset(res->bo->virtual, 0, res->size); | |
1389 | + dri_bo_unmap(res->bo); | |
1390 | + } | |
1391 | +} | |
1392 | + | |
1393 | +void | |
1394 | +i965_free_gpe_resource(struct i965_gpe_resource *res) | |
1395 | +{ | |
1396 | + dri_bo_unreference(res->bo); | |
1397 | + res->bo = NULL; | |
1398 | + res->map = NULL; | |
1399 | +} | |
1400 | + | |
1401 | +void * | |
1402 | +i965_map_gpe_resource(struct i965_gpe_resource *res) | |
1403 | +{ | |
1404 | + int ret; | |
1405 | + | |
1406 | + if (res->bo) { | |
1407 | + ret = dri_bo_map(res->bo, 1); | |
1408 | + | |
1409 | + if (ret == 0) | |
1410 | + res->map = res->bo->virtual; | |
1411 | + else | |
1412 | + res->map = NULL; | |
1413 | + } else | |
1414 | + res->map = NULL; | |
1415 | + | |
1416 | + return res->map; | |
1417 | +} | |
1418 | + | |
1419 | +void | |
1420 | +i965_unmap_gpe_resource(struct i965_gpe_resource *res) | |
1421 | +{ | |
1422 | + if (res->bo && res->map) | |
1423 | + dri_bo_unmap(res->bo); | |
1424 | + | |
1425 | + res->map = NULL; | |
1426 | +} |
@@ -44,6 +44,26 @@ struct i965_buffer_surface | ||
44 | 44 | unsigned int pitch; |
45 | 45 | }; |
46 | 46 | |
47 | +enum { | |
48 | + I965_GPE_RESOURCE_BUFFER = 0, | |
49 | + I965_GPE_RESOURCE_2D | |
50 | +}; | |
51 | + | |
52 | +struct i965_gpe_resource | |
53 | +{ | |
54 | + dri_bo *bo; | |
55 | + char *map; | |
56 | + uint32_t type; | |
57 | + uint32_t width; | |
58 | + uint32_t height; | |
59 | + uint32_t pitch; | |
60 | + uint32_t size; | |
61 | + uint32_t tiling; | |
62 | + uint32_t cb_cr_pitch; | |
63 | + uint32_t x_cb_offset; | |
64 | + uint32_t y_cb_offset; | |
65 | +}; | |
66 | + | |
47 | 67 | struct i965_gpe_context |
48 | 68 | { |
49 | 69 | struct { |
@@ -228,4 +248,28 @@ void gen9_gpe_pipeline_end(VADriverContextP ctx, | ||
228 | 248 | struct i965_gpe_context *gpe_context, |
229 | 249 | struct intel_batchbuffer *batch); |
230 | 250 | |
251 | +Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr, | |
252 | + struct i965_gpe_resource *res, | |
253 | + const char *name); | |
254 | + | |
255 | +void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res, | |
256 | + struct object_surface *obj_surface); | |
257 | + | |
258 | +void i965_dri_object_to_buffer_gpe_resource(struct i965_gpe_resource *res, | |
259 | + dri_bo *bo); | |
260 | + | |
261 | +void i965_gpe_dri_object_to_2d_gpe_resource(struct i965_gpe_resource *res, | |
262 | + dri_bo *bo, | |
263 | + unsigned int width, | |
264 | + unsigned int height, | |
265 | + unsigned int pitch); | |
266 | + | |
267 | +void i965_zero_gpe_resource(struct i965_gpe_resource *res); | |
268 | + | |
269 | +void i965_free_gpe_resource(struct i965_gpe_resource *res); | |
270 | + | |
271 | +void *i965_map_gpe_resource(struct i965_gpe_resource *res); | |
272 | + | |
273 | +void i965_unmap_gpe_resource(struct i965_gpe_resource *res); | |
274 | + | |
231 | 275 | #endif /* _I965_GPE_UTILS_H_ */ |