修订版 | 503123c9f01e86eb3c6ec0557c2d85deea15ee80 (tree) |
---|---|
时间 | 2015-12-26 22:24:02 |
作者 | Yoshinori Sato <ysato@user...> |
Commiter | Yoshinori Sato |
SCI simulation fix
@@ -785,13 +785,14 @@ enum {PORT_NONE, PORT_PTY,PORT_NET}; | ||
785 | 785 | static int sci_port_type = PORT_NONE; |
786 | 786 | |
787 | 787 | |
788 | -static void set_sciir(int ch, unsigned char ssr) | |
788 | +static void set_sciir(int ch, unsigned char scr, unsigned char ssr) | |
789 | 789 | { |
790 | 790 | unsigned char mask[] = {0x38, 0x40, 0x80, 0x04}; |
791 | + unsigned char enable[] = {0x40, 0x40, 0x80, 0x04}; | |
791 | 792 | unsigned char *irptr = rx_mem_ptr(IRADR(214 + ch * 4), MPA_WRITING); |
792 | 793 | unsigned int i; |
793 | 794 | for (i = 0; i < 4; i++) |
794 | - *irptr++ = !!(ssr & mask[i]); | |
795 | + *irptr++ = ((ssr & mask[i]) && (scr & enable[i])); | |
795 | 796 | } |
796 | 797 | |
797 | 798 | static unsigned int |
@@ -976,20 +977,21 @@ sci(unsigned int cycles_diff) | ||
976 | 977 | { |
977 | 978 | st = &sci_state[ch]; |
978 | 979 | /* clear internal ssr */ |
979 | - st->ssr &= SSR(ch); | |
980 | + if (get_rw_flag(0x00088243 + ch * 8) == mem_w) | |
981 | + st->ssr &= SSR(ch); | |
980 | 982 | |
981 | 983 | /* Tx request */ |
982 | 984 | if((SCR(ch) & 0x20) && |
983 | - (get_rw_flag(0x00088243 + ch * 8) == mem_w) && (st->txstate == 0)) | |
985 | + (get_rw_flag(0x00088243 + ch * 8) == mem_w) && (st->txstate == 0) && !(SSR(ch) & 0x80)) | |
984 | 986 | { |
985 | 987 | sci_send_data(ch,TDR(ch)); |
986 | - st->ssr &= ~0x04; | |
987 | 988 | /* TSR shift time */ |
988 | 989 | st->tx_end_time = 1; |
989 | 990 | st->txstate = 1; |
990 | 991 | set_rw_flag(0x00088243 + ch * 8, mem_none); |
991 | 992 | } |
992 | - st->tx_end_time -= cycles_diff; | |
993 | + if(st->tx_end_time > 0) | |
994 | + st->tx_end_time -= cycles_diff; | |
993 | 995 | /* Tx complete check */ |
994 | 996 | if(((st->ssr & 0x84) != 0x84) && |
995 | 997 | (st->tx_end_time <= 0)) |
@@ -1004,7 +1006,8 @@ sci(unsigned int cycles_diff) | ||
1004 | 1006 | st->ssr |= 0x04; |
1005 | 1007 | } |
1006 | 1008 | } |
1007 | - st->rx_end_time -= cycles_diff; | |
1009 | + if(st->rx_end_time > 0) | |
1010 | + st->rx_end_time -= cycles_diff; | |
1008 | 1011 | /* Rx check */ |
1009 | 1012 | if (st->rx_end_time <= 0) |
1010 | 1013 | /* RSR free & Rx Enabled */ |
@@ -1028,8 +1031,8 @@ sci(unsigned int cycles_diff) | ||
1028 | 1031 | } |
1029 | 1032 | |
1030 | 1033 | /* update SSR */ |
1031 | - SSR(ch) = st->ssr & 0xfc; | |
1032 | - set_sciir(ch, st->ssr); | |
1034 | + SSR(ch) = st->ssr & 0xfc; | |
1035 | + set_sciir(ch, SCR(ch), st->ssr); | |
1033 | 1036 | } |
1034 | 1037 | } |
1035 | 1038 |