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修订版503123c9f01e86eb3c6ec0557c2d85deea15ee80 (tree)
时间2015-12-26 22:24:02
作者Yoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

SCI simulation fix

更改概述

差异

--- a/sim/rx/mem.c
+++ b/sim/rx/mem.c
@@ -785,13 +785,14 @@ enum {PORT_NONE, PORT_PTY,PORT_NET};
785785 static int sci_port_type = PORT_NONE;
786786
787787
788-static void set_sciir(int ch, unsigned char ssr)
788+static void set_sciir(int ch, unsigned char scr, unsigned char ssr)
789789 {
790790 unsigned char mask[] = {0x38, 0x40, 0x80, 0x04};
791+ unsigned char enable[] = {0x40, 0x40, 0x80, 0x04};
791792 unsigned char *irptr = rx_mem_ptr(IRADR(214 + ch * 4), MPA_WRITING);
792793 unsigned int i;
793794 for (i = 0; i < 4; i++)
794- *irptr++ = !!(ssr & mask[i]);
795+ *irptr++ = ((ssr & mask[i]) && (scr & enable[i]));
795796 }
796797
797798 static unsigned int
@@ -976,20 +977,21 @@ sci(unsigned int cycles_diff)
976977 {
977978 st = &sci_state[ch];
978979 /* clear internal ssr */
979- st->ssr &= SSR(ch);
980+ if (get_rw_flag(0x00088243 + ch * 8) == mem_w)
981+ st->ssr &= SSR(ch);
980982
981983 /* Tx request */
982984 if((SCR(ch) & 0x20) &&
983- (get_rw_flag(0x00088243 + ch * 8) == mem_w) && (st->txstate == 0))
985+ (get_rw_flag(0x00088243 + ch * 8) == mem_w) && (st->txstate == 0) && !(SSR(ch) & 0x80))
984986 {
985987 sci_send_data(ch,TDR(ch));
986- st->ssr &= ~0x04;
987988 /* TSR shift time */
988989 st->tx_end_time = 1;
989990 st->txstate = 1;
990991 set_rw_flag(0x00088243 + ch * 8, mem_none);
991992 }
992- st->tx_end_time -= cycles_diff;
993+ if(st->tx_end_time > 0)
994+ st->tx_end_time -= cycles_diff;
993995 /* Tx complete check */
994996 if(((st->ssr & 0x84) != 0x84) &&
995997 (st->tx_end_time <= 0))
@@ -1004,7 +1006,8 @@ sci(unsigned int cycles_diff)
10041006 st->ssr |= 0x04;
10051007 }
10061008 }
1007- st->rx_end_time -= cycles_diff;
1009+ if(st->rx_end_time > 0)
1010+ st->rx_end_time -= cycles_diff;
10081011 /* Rx check */
10091012 if (st->rx_end_time <= 0)
10101013 /* RSR free & Rx Enabled */
@@ -1028,8 +1031,8 @@ sci(unsigned int cycles_diff)
10281031 }
10291032
10301033 /* update SSR */
1031- SSR(ch) = st->ssr & 0xfc;
1032- set_sciir(ch, st->ssr);
1034+ SSR(ch) = st->ssr & 0xfc;
1035+ set_sciir(ch, SCR(ch), st->ssr);
10331036 }
10341037 }
10351038