提交: 10fa93797a5ee3b3632aeec0a64b115167f7b016 - uboot (git)

Commit MetaInfo

• 修订版: 10fa93797a5ee3b3632aeec0a64b115167f7b016 (tree)
• 时间: 2016-04-17 18:04:08
• 作者: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

Add MS7206SE support.

更改概述

• add: board/renesas/ms7206se/Makefile
• add: board/renesas/ms7206se/lowlevel_init.S
• add: board/renesas/ms7206se/ms7206se.c
• add: include/configs/ms7206se.h

差异

--- /dev/null
+++ b/board/renesas/ms7206se/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Yoshinori Sato <[e-mail]>
+#
+# u-boot/board/renesas/ms7619se/Makefile
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ms7206se.o
+obj-y	+= lowlevel_init.o

--- /dev/null
+++ b/board/renesas/ms7206se/lowlevel_init.S
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <[e-mail]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+#define INTMSK0 0x11800000
+	
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	mova	CPG_settings_table,r0
+1:	mov.l	@r0+,r3		// Address (or zero)
+	tst	r3,r3
+	bt	2f
+	mov.l	@r0+,r1		// data
+	bra	1b
+	 mov.w	r1,@r3
+2:
+	mov.l	$mclkcr,r0		// MCLKCR setting
+	mov	#0x40,r1
+	mov.b	r1,@r0
+
+	// Set up the Bus Controler
+	mova	BSC_settings_table,r0
+5:	mov.l	@r0+,r3		       // Address (or zero)
+	tst	r3,r3
+	bt	6f
+	mov.l	@r0+,r1		       // data
+	bra	5b
+	 mov.l	r1,@r3
+
+6:
+	mov.l	$delay_count,r0
+7:
+	dt	r0
+	bf	7b
+
+	mov.l	$SDMR,r1		// Turns on SDRAM controller
+	mov.l	$SDMR_val,r2
+	mov.l	r2,@r1
+
+	// Set up the Pin Function Controler
+	mova	PFC_settings_table,r0
+3:	mov.l	@r0+,r3		       // Address (or zero)
+	tst	r3,r3
+	bt	4f
+	mov.l	@r0+,r1		       // data
+	bra	3b
+	 mov.w	r1,@r3
+4:
+	rts/n
+
+	.align	4
+$delay_count:
+	.long	2000
+$SDMR:	.long	0xfffc5880
+$SDMR_val:
+	.long	0
+
+$mclkcr:
+	.long	MCLKCR
+
+CPG_settings_table:
+	.long	WTCSR,0xA500
+	.long	WTCNT,0x5A00
+	.long	WTCSR,0xA51E
+	.long	FRQCR, 0x120c	/* input:33.3333MHz I:B:P=6:2:1=200MHz:66MHz:33MHz */
+	.long	0
+
+BSC_settings_table:
+	# Settings from Hitachi docs for SE7206
+	.long	CMNCR,  0x00001010
+	.long	CS0BCR, 0x10000600
+	.long	CS2BCR, 0x10000600
+	.long	CS4BCR, 0x10000400
+	.long	CS5BCR, 0x10000400
+	.long	CS3BCR, 0x10004600
+	.long	CS0WCR, 0x00000380;	/* wait:4cycle				*/
+	.long	CS2WCR, 0x00000380;
+	.long	CS4WCR, 0x00000380;
+	.long	CS5WCR, 0x00000380;
+	.long	CS3WCR, 0x00004892;	/* pre->actv:1cycle, actv->read/write:2cycle, write->pre:1cycle, ref->actv:4cycle	*/
+	.long	SDCR,   0x00000811;
+	.long	RTCNT,  0xa55a0083;
+	.long	RTCOR,  0xa55a0083;
+	.long	RTCSR,  0xa55a0008;	/* reflesh count=Bφ/4	*/
+	.long	0
+
+PFC_settings_table:
+	.long	PACRH3, 0x0022
+	.long	PACRH2, 0x1111
+	.long	PACRH1, 0x1115
+	.long	PACRL4, 0x1111
+	.long	PACRL3, 0x1125
+	.long	PACRL2, 0x2255
+	.long	PACRL1, 0x5500
+	.long	PBCR3,  0x0022
+	.long	PBCR2,  0x2244
+	.long	PBCR1,  0x1111
+	.long	PCCRL1, 0x1111
+	.long	PDCRH4, 0x1111
+	.long	PDCRH3, 0x1111
+	.long	PDCRH2, 0x1111
+	.long	PDCRH1, 0x1111
+	.long	PDCRL4, 0x1111
+	.long	PDCRL3, 0x1111
+	.long	PECRH1, 0x0005
+	.long	PECRL4, 0x3223
+	.long	PECRL3, 0x3030
+	.long	PECRL2, 0x3550
+	.long	IFCR,   0x0003
+	.long	0
+
+$INTMSK0:
+	.long	INTMSK0

--- /dev/null
+++ b/board/renesas/ms7206se/ms7206se.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Yoshinori Sato <[e-mail]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Technology MS7206SE\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc  = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	return rc;
+}
+#endif

--- /dev/null
+++ b/include/configs/ms7206se.h
@@ -0,0 +1,95 @@
+/*
+ * Configuation settings for the Renesas Technology MS7206SE
+ *
+ * Copyright (C) 2013 Yoshinori Sato <[e-mail]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MS7206SE_H
+#define __MS7206SE
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH2		1
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7206	1
+#define CONFIG_MS7206SE		1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC3,115200"
+#define CONFIG_LOADADDR		0x0C100000 /* MS7206SE01_SDRAM_BASE + 1MB */
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define MS7206SE_SDRAM_BASE	0x0C000000
+#define MS7206SE_FLASH_BASE_1	0x20000000	/* Non cache */
+#define MS7206SE_FLASH_BANK_SIZE	(16 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x0C7C0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200,  3840, 57600, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF3	1
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_LOADADDR
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_LOADADDR + (63 * 1024 * 1024))
+
+#define CONFIG_SYS_SDRAM_BASE		MS7206SE_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		MS7206SE_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#undef	CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE		MS7206SE_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	142
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE (0x30000000)
+
+#endif	/* __MS7206SE_H */