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修订版181d1684cae07f11122b76263007da01d795acdf (tree)
时间2022-07-25 23:12:01
作者Marcel Ziswiler <marcel.ziswiler@tora...>
CommiterStefano Babic

Log Message

imx8mq: synchronise device tree with linux

Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

更改概述

差异

--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -27,6 +27,17 @@
2727 clock-frequency = <100000000>;
2828 };
2929
30+ reg_pcie1: regulator-pcie {
31+ compatible = "regulator-fixed";
32+ pinctrl-names = "default";
33+ pinctrl-0 = <&pinctrl_pcie1_reg>;
34+ regulator-name = "MPCIE_3V3";
35+ regulator-min-microvolt = <3300000>;
36+ regulator-max-microvolt = <3300000>;
37+ gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38+ enable-active-high;
39+ };
40+
3041 reg_usdhc2_vmmc: regulator-vsd-3v3 {
3142 pinctrl-names = "default";
3243 pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -123,6 +134,7 @@
123134
124135 &ddrc {
125136 operating-points-v2 = <&ddrc_opp_table>;
137+ status = "okay";
126138
127139 ddrc_opp_table: opp-table {
128140 compatible = "operating-points-v2";
@@ -169,6 +181,11 @@
169181 reg = <0>;
170182 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
171183 reset-assert-us = <10000>;
184+ qca,disable-smarteee;
185+ vddio-supply = <&vddh>;
186+
187+ vddh: vddh-regulator {
188+ };
172189 };
173190 };
174191 };
@@ -318,6 +335,21 @@
318335 <&clk IMX8MQ_CLK_PCIE1_PHY>,
319336 <&pcie0_refclk>;
320337 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
338+ vph-supply = <&vgen5_reg>;
339+ status = "okay";
340+};
341+
342+&pcie1 {
343+ pinctrl-names = "default";
344+ pinctrl-0 = <&pinctrl_pcie1>;
345+ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
346+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
347+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
348+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
349+ <&pcie0_refclk>;
350+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
351+ vpcie-supply = <&reg_pcie1>;
352+ vph-supply = <&vgen5_reg>;
321353 status = "okay";
322354 };
323355
@@ -325,6 +357,10 @@
325357 power-supply = <&sw1a_reg>;
326358 };
327359
360+&pgc_vpu {
361+ power-supply = <&sw1c_reg>;
362+};
363+
328364 &qspi0 {
329365 pinctrl-names = "default";
330366 pinctrl-0 = <&pinctrl_qspi>;
@@ -336,6 +372,8 @@
336372 #size-cells = <1>;
337373 compatible = "micron,n25q256a", "jedec,spi-nor";
338374 spi-max-frequency = <29000000>;
375+ spi-tx-bus-width = <1>;
376+ spi-rx-bus-width = <4>;
339377 };
340378 };
341379
@@ -402,9 +440,9 @@
402440 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
403441 assigned-clock-rates = <200000000>;
404442 pinctrl-names = "default", "state_100mhz", "state_200mhz";
405- pinctrl-0 = <&pinctrl_usdhc2>;
406- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
407- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
443+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
444+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
445+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
408446 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
409447 vmmc-supply = <&reg_usdhc2_vmmc>;
410448 status = "okay";
@@ -422,7 +460,6 @@
422460 fsl,pins = <
423461 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
424462 >;
425-
426463 };
427464
428465 pinctrl_fec1: fec1grp {
@@ -471,6 +508,19 @@
471508 >;
472509 };
473510
511+ pinctrl_pcie1: pcie1grp {
512+ fsl,pins = <
513+ MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
514+ MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
515+ >;
516+ };
517+
518+ pinctrl_pcie1_reg: pcie1reggrp {
519+ fsl,pins = <
520+ MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
521+ >;
522+ };
523+
474524 pinctrl_qspi: qspigrp {
475525 fsl,pins = <
476526 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
@@ -479,7 +529,6 @@
479529 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
480530 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
481531 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
482-
483532 >;
484533 };
485534
@@ -564,6 +613,12 @@
564613 >;
565614 };
566615
616+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
617+ fsl,pins = <
618+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
619+ >;
620+ };
621+
567622 pinctrl_usdhc2: usdhc2grp {
568623 fsl,pins = <
569624 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
--- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts
@@ -51,6 +51,7 @@
5151 regulator-min-microvolt = <3300000>;
5252 regulator-max-microvolt = <3300000>;
5353 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
54+ off-on-delay-us = <20000>;
5455 enable-active-high;
5556 };
5657 };
@@ -310,7 +311,7 @@
310311 &uart3 {
311312 pinctrl-names = "default";
312313 pinctrl-0 = <&pinctrl_uart3>;
313- fsl,uart-has-rtscts;
314+ uart-has-rtscts;
314315 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
315316 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
316317 status = "okay";
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -12,6 +12,31 @@
1212 / {
1313 model = "MNT Reform 2";
1414 compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15+ chassis-type = "laptop";
16+
17+ backlight: backlight {
18+ compatible = "pwm-backlight";
19+ pinctrl-names = "default";
20+ pinctrl-0 = <&pinctrl_backlight>;
21+ pwms = <&pwm2 0 10000 0>;
22+ power-supply = <&reg_main_usb>;
23+ enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
24+ brightness-levels = <0 32 64 128 160 200 255>;
25+ default-brightness-level = <6>;
26+ };
27+
28+ panel {
29+ compatible = "innolux,n125hce-gn1", "simple-panel";
30+ power-supply = <&reg_main_3v3>;
31+ backlight = <&backlight>;
32+ no-hpd;
33+
34+ port {
35+ panel_in: endpoint {
36+ remote-endpoint = <&edp_bridge_out>;
37+ };
38+ };
39+ };
1540
1641 pcie1_refclk: clock-pcie1-refclk {
1742 compatible = "fixed-clock";
@@ -41,6 +66,22 @@
4166 vin-supply = <&reg_main_5v>;
4267 };
4368
69+ reg_main_1v8: regulator-main-1v8 {
70+ compatible = "regulator-fixed";
71+ regulator-name = "1V8";
72+ regulator-min-microvolt = <1800000>;
73+ regulator-max-microvolt = <1800000>;
74+ vin-supply = <&reg_main_3v3>;
75+ };
76+
77+ reg_main_1v2: regulator-main-1v2 {
78+ compatible = "regulator-fixed";
79+ regulator-name = "1V2";
80+ regulator-min-microvolt = <1200000>;
81+ regulator-max-microvolt = <1200000>;
82+ vin-supply = <&reg_main_5v>;
83+ };
84+
4485 sound {
4586 compatible = "fsl,imx-audio-wm8960";
4687 audio-cpu = <&sai2>;
@@ -60,6 +101,13 @@
60101 };
61102 };
62103
104+&dphy {
105+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107+ assigned-clock-rates = <25000000>;
108+ status = "okay";
109+};
110+
63111 &fec1 {
64112 status = "okay";
65113 };
@@ -83,6 +131,67 @@
83131 };
84132 };
85133
134+&i2c4 {
135+ pinctrl-names = "default";
136+ pinctrl-0 = <&pinctrl_i2c4>;
137+ clock-frequency = <400000>;
138+ status = "okay";
139+
140+ edp_bridge: bridge@2c {
141+ compatible = "ti,sn65dsi86";
142+ pinctrl-names = "default";
143+ pinctrl-0 = <&pinctrl_edp_bridge>;
144+ reg = <0x2c>;
145+ enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
146+ vccio-supply = <&reg_main_1v8>;
147+ vpll-supply = <&reg_main_1v8>;
148+ vcca-supply = <&reg_main_1v2>;
149+ vcc-supply = <&reg_main_1v2>;
150+
151+ ports {
152+ #address-cells = <1>;
153+ #size-cells = <0>;
154+
155+ port@0 {
156+ reg = <0>;
157+
158+ edp_bridge_in: endpoint {
159+ remote-endpoint = <&mipi_dsi_out>;
160+ };
161+ };
162+
163+ port@1 {
164+ reg = <1>;
165+
166+ edp_bridge_out: endpoint {
167+ remote-endpoint = <&panel_in>;
168+ };
169+ };
170+ };
171+ };
172+};
173+
174+&lcdif {
175+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177+ /delete-property/assigned-clock-rates;
178+ status = "okay";
179+};
180+
181+&mipi_dsi {
182+ status = "okay";
183+
184+ ports {
185+ port@1 {
186+ reg = <1>;
187+
188+ mipi_dsi_out: endpoint {
189+ remote-endpoint = <&edp_bridge_in>;
190+ };
191+ };
192+ };
193+};
194+
86195 &pcie1 {
87196 pinctrl-names = "default";
88197 pinctrl-0 = <&pinctrl_pcie1>;
@@ -95,6 +204,12 @@
95204 status = "okay";
96205 };
97206
207+&pwm2 {
208+ pinctrl-names = "default";
209+ pinctrl-0 = <&pinctrl_pwm2>;
210+ status = "okay";
211+};
212+
98213 &reg_1p8v {
99214 vin-supply = <&reg_main_5v>;
100215 };
@@ -168,10 +283,29 @@
168283 };
169284
170285 &iomuxc {
286+ pinctrl_backlight: backlightgrp {
287+ fsl,pins = <
288+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
289+ >;
290+ };
291+
292+ pinctrl_edp_bridge: edpbridgegrp {
293+ fsl,pins = <
294+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1
295+ >;
296+ };
297+
171298 pinctrl_i2c3: i2c3grp {
172299 fsl,pins = <
173- MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
174- MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
300+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
301+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022
302+ >;
303+ };
304+
305+ pinctrl_i2c4: i2c4grp {
306+ fsl,pins = <
307+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
308+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022
175309 >;
176310 };
177311
@@ -181,6 +315,12 @@
181315 >;
182316 };
183317
318+ pinctrl_pwm2: pwm2grp {
319+ fsl,pins = <
320+ MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3
321+ >;
322+ };
323+
184324 pinctrl_sai2: sai2grp {
185325 fsl,pins = <
186326 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
--- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi
+++ b/arch/arm/dts/imx8mq-nitrogen-som.dtsi
@@ -69,6 +69,9 @@
6969 reg = <4>;
7070 interrupt-parent = <&gpio1>;
7171 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
72+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
73+ reset-assert-us = <10000>;
74+ reset-deassert-us = <300>;
7275 };
7376 };
7477 };
@@ -191,20 +194,20 @@
191194 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
192195 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
193196 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
194- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
197+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1
195198 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
196199 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
197200 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
198- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
199- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
200- MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
201+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1
202+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1
203+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41
201204 >;
202205 };
203206
204207 pinctrl_i2c1: i2c1grp {
205208 fsl,pins = <
206- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
207- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
209+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
210+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022
208211 >;
209212 };
210213
--- a/arch/arm/dts/imx8mq-phanbell.dts
+++ b/arch/arm/dts/imx8mq-phanbell.dts
@@ -1,11 +1,12 @@
11 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
22 /*
3- * Copyright 2020 NXP
3+ * Copyright 2017-2019 NXP
44 */
55
66 /dts-v1/;
77
88 #include "imx8mq.dtsi"
9+#include <dt-bindings/interrupt-controller/irq.h>
910
1011 / {
1112 model = "Google i.MX8MQ Phanbell";
@@ -35,6 +36,16 @@
3536 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
3637 enable-active-high;
3738 };
39+
40+ fan: gpio-fan {
41+ compatible = "gpio-fan";
42+ gpio-fan,speed-map = <0 0 8600 1>;
43+ gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
44+ #cooling-cells = <2>;
45+ pinctrl-names = "default";
46+ pinctrl-0 = <&pinctrl_gpio_fan>;
47+ status = "okay";
48+ };
3849 };
3950
4051 &A53_0 {
@@ -53,6 +64,53 @@
5364 cpu-supply = <&buck2>;
5465 };
5566
67+&cpu_thermal {
68+ trips {
69+ cpu_alert0: trip0 {
70+ temperature = <75000>;
71+ hysteresis = <2000>;
72+ type = "passive";
73+ };
74+
75+ cpu_alert1: trip1 {
76+ temperature = <80000>;
77+ hysteresis = <2000>;
78+ type = "passive";
79+ };
80+
81+ cpu_crit0: trip3 {
82+ temperature = <90000>;
83+ hysteresis = <2000>;
84+ type = "critical";
85+ };
86+
87+ fan_toggle0: trip4 {
88+ temperature = <65000>;
89+ hysteresis = <10000>;
90+ type = "active";
91+ };
92+ };
93+
94+ cooling-maps {
95+ map0 {
96+ trip = <&cpu_alert0>;
97+ cooling-device =
98+ <&A53_0 0 1>; /* Exclude highest OPP */
99+ };
100+
101+ map1 {
102+ trip = <&cpu_alert1>;
103+ cooling-device =
104+ <&A53_0 0 2>; /* Exclude two highest OPPs */
105+ };
106+
107+ map4 {
108+ trip = <&fan_toggle0>;
109+ cooling-device = <&fan 0 1>;
110+ };
111+ };
112+};
113+
56114 &i2c1 {
57115 clock-frequency = <400000>;
58116 pinctrl-names = "default";
@@ -68,7 +126,7 @@
68126 clocks = <&pmic_osc>;
69127 clock-output-names = "pmic_clk";
70128 interrupt-parent = <&gpio1>;
71- interrupts = <3 GPIO_ACTIVE_LOW>;
129+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
72130
73131 regulators {
74132 buck1: BUCK1 {
@@ -206,9 +264,6 @@
206264 pinctrl-0 = <&pinctrl_fec1>;
207265 phy-mode = "rgmii-id";
208266 phy-handle = <&ethphy0>;
209- phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
210- phy-reset-duration = <10>;
211- phy-reset-post-delay = <50>;
212267 fsl,magic-packet;
213268 status = "okay";
214269
@@ -218,6 +273,9 @@
218273 ethphy0: ethernet-phy@0 {
219274 compatible = "ethernet-phy-ieee802.3-c22";
220275 reg = <0>;
276+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
277+ reset-assert-us = <10000>;
278+ reset-deassert-us = <50000>;
221279 };
222280 };
223281 };
@@ -295,6 +353,12 @@
295353 >;
296354 };
297355
356+ pinctrl_gpio_fan: gpiofangrp {
357+ fsl,pins = <
358+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
359+ >;
360+ };
361+
298362 pinctrl_i2c1: i2c1grp {
299363 fsl,pins = <
300364 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
@@ -302,7 +366,7 @@
302366 >;
303367 };
304368
305- pinctrl_pmic: pmicirq {
369+ pinctrl_pmic: pmicirqgrp {
306370 fsl,pins = <
307371 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
308372 >;
@@ -332,7 +396,7 @@
332396 >;
333397 };
334398
335- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
399+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
336400 fsl,pins = <
337401 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
338402 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
@@ -349,7 +413,7 @@
349413 >;
350414 };
351415
352- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
416+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
353417 fsl,pins = <
354418 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
355419 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
@@ -366,7 +430,7 @@
366430 >;
367431 };
368432
369- pinctrl_usdhc2_gpio: usdhc2grpgpio {
433+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
370434 fsl,pins = <
371435 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
372436 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -385,7 +449,7 @@
385449 >;
386450 };
387451
388- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
452+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
389453 fsl,pins = <
390454 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
391455 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
@@ -397,7 +461,7 @@
397461 >;
398462 };
399463
400- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
464+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
401465 fsl,pins = <
402466 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
403467 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
--- a/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi
@@ -1,5 +1,7 @@
11 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
22
3+#include "imx8mq-u-boot.dtsi"
4+
35 &pinctrl_uart1 {
46 u-boot,dm-spl;
57 };
--- a/arch/arm/dts/imx8mq-pico-pi.dts
+++ b/arch/arm/dts/imx8mq-pico-pi.dts
@@ -9,7 +9,7 @@
99 /dts-v1/;
1010
1111 #include "imx8mq.dtsi"
12-#include "imx8mq-u-boot.dtsi"
12+#include <dt-bindings/interrupt-controller/irq.h>
1313
1414 / {
1515 model = "TechNexion PICO-PI-8M";
@@ -35,25 +35,13 @@
3535 regulator-max-microvolt = <5000000>;
3636 gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
3737 };
38-
39- reg_eth_phy: eth_phy {
40- compatible = "regulator-fixed";
41- regulator-name = "eth_phy_pwr";
42- regulator-min-microvolt = <3300000>;
43- regulator-max-microvolt = <3300000>;
44- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
45- };
4638 };
4739
4840 &fec1 {
4941 pinctrl-names = "default";
50- pinctrl-0 = <&pinctrl_fec1>;
42+ pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
5143 phy-mode = "rgmii-id";
5244 phy-handle = <&ethphy0>;
53- phy-supply = <&reg_eth_phy>;
54- phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
55- phy-reset-duration = <100>;
56- phy-reset-post-delay = <100>;
5745 fsl,magic-packet;
5846 status = "okay";
5947
@@ -83,7 +71,7 @@
8371 clock-names = "osc";
8472 clock-output-names = "pmic_clk";
8573 interrupt-parent = <&gpio1>;
86- interrupts = <3 GPIO_ACTIVE_LOW>;
74+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
8775 interrupt-names = "irq";
8876
8977 regulators {
@@ -220,6 +208,8 @@
220208 };
221209
222210 &usdhc1 {
211+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
212+ assigned-clock-rates = <400000000>;
223213 pinctrl-names = "default", "state_100mhz", "state_200mhz";
224214 pinctrl-0 = <&pinctrl_usdhc1>;
225215 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -230,6 +220,8 @@
230220 };
231221
232222 &usdhc2 {
223+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
224+ assigned-clock-rates = <200000000>;
233225 pinctrl-names = "default", "state_100mhz", "state_200mhz";
234226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
235227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -260,24 +252,29 @@
260252 };
261253
262254 &iomuxc {
255+ pinctrl_enet_3v3: enet3v3grp {
256+ fsl,pins = <
257+ MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
258+ >;
259+ };
260+
263261 pinctrl_fec1: fec1grp {
264262 fsl,pins = <
265- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
266- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
267- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
268- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
269- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
270- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
271- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
272- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
273- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
274- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
275- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
276- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
263+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
264+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
265+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
266+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
267+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
268+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
269+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
270+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
271+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
272+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
273+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
274+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
277275 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
278276 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
279- MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
280- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
277+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
281278 >;
282279 };
283280
@@ -301,7 +298,7 @@
301298 >;
302299 };
303300
304- pinctrl_pmic: pmicirq {
301+ pinctrl_pmic: pmicirqgrp {
305302 fsl,pins = <
306303 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
307304 >;
@@ -339,7 +336,7 @@
339336 >;
340337 };
341338
342- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
339+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
343340 fsl,pins = <
344341 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
345342 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
@@ -355,7 +352,7 @@
355352 >;
356353 };
357354
358- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
355+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
359356 fsl,pins = <
360357 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
361358 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
@@ -371,7 +368,7 @@
371368 >;
372369 };
373370
374- pinctrl_usdhc2_gpio: usdhc2grpgpio {
371+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
375372 fsl,pins = <
376373 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
377374 >;
@@ -389,7 +386,7 @@
389386 >;
390387 };
391388
392- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
389+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
393390 fsl,pins = <
394391 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
395392 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
@@ -401,7 +398,7 @@
401398 >;
402399 };
403400
404- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
401+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
405402 fsl,pins = <
406403 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
407404 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -63,6 +63,13 @@
6363 clock-output-names = "osc_27m";
6464 };
6565
66+ hdmi_phy_27m: clock-hdmi-phy-27m {
67+ compatible = "fixed-clock";
68+ #clock-cells = <0>;
69+ clock-frequency = <27000000>;
70+ clock-output-names = "hdmi_phy_27m";
71+ };
72+
6673 clk_ext1: clock-ext1 {
6774 compatible = "fixed-clock";
6875 #clock-cells = <0>;
@@ -102,6 +109,12 @@
102109 clock-latency = <61036>; /* two CLK32 periods */
103110 clocks = <&clk IMX8MQ_CLK_ARM>;
104111 enable-method = "psci";
112+ i-cache-size = <0x8000>;
113+ i-cache-line-size = <64>;
114+ i-cache-sets = <256>;
115+ d-cache-size = <0x8000>;
116+ d-cache-line-size = <64>;
117+ d-cache-sets = <128>;
105118 next-level-cache = <&A53_L2>;
106119 operating-points-v2 = <&a53_opp_table>;
107120 #cooling-cells = <2>;
@@ -116,6 +129,12 @@
116129 clock-latency = <61036>; /* two CLK32 periods */
117130 clocks = <&clk IMX8MQ_CLK_ARM>;
118131 enable-method = "psci";
132+ i-cache-size = <0x8000>;
133+ i-cache-line-size = <64>;
134+ i-cache-sets = <256>;
135+ d-cache-size = <0x8000>;
136+ d-cache-line-size = <64>;
137+ d-cache-sets = <128>;
119138 next-level-cache = <&A53_L2>;
120139 operating-points-v2 = <&a53_opp_table>;
121140 #cooling-cells = <2>;
@@ -128,6 +147,12 @@
128147 clock-latency = <61036>; /* two CLK32 periods */
129148 clocks = <&clk IMX8MQ_CLK_ARM>;
130149 enable-method = "psci";
150+ i-cache-size = <0x8000>;
151+ i-cache-line-size = <64>;
152+ i-cache-sets = <256>;
153+ d-cache-size = <0x8000>;
154+ d-cache-line-size = <64>;
155+ d-cache-sets = <128>;
131156 next-level-cache = <&A53_L2>;
132157 operating-points-v2 = <&a53_opp_table>;
133158 #cooling-cells = <2>;
@@ -140,6 +165,12 @@
140165 clock-latency = <61036>; /* two CLK32 periods */
141166 clocks = <&clk IMX8MQ_CLK_ARM>;
142167 enable-method = "psci";
168+ i-cache-size = <0x8000>;
169+ i-cache-line-size = <64>;
170+ i-cache-sets = <256>;
171+ d-cache-size = <0x8000>;
172+ d-cache-line-size = <64>;
173+ d-cache-sets = <128>;
143174 next-level-cache = <&A53_L2>;
144175 operating-points-v2 = <&a53_opp_table>;
145176 #cooling-cells = <2>;
@@ -147,6 +178,10 @@
147178
148179 A53_L2: l2-cache0 {
149180 compatible = "cache";
181+ cache-level = <2>;
182+ cache-size = <0x100000>;
183+ cache-line-size = <64>;
184+ cache-sets = <1024>;
150185 };
151186 };
152187
@@ -429,49 +464,49 @@
429464 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
430465 little-endian;
431466 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
432- fsl,tmu-calibration = <0x00000000 0x00000023
433- 0x00000001 0x00000029
434- 0x00000002 0x0000002f
435- 0x00000003 0x00000035
436- 0x00000004 0x0000003d
437- 0x00000005 0x00000043
438- 0x00000006 0x0000004b
439- 0x00000007 0x00000051
440- 0x00000008 0x00000057
441- 0x00000009 0x0000005f
442- 0x0000000a 0x00000067
443- 0x0000000b 0x0000006f
444-
445- 0x00010000 0x0000001b
446- 0x00010001 0x00000023
447- 0x00010002 0x0000002b
448- 0x00010003 0x00000033
449- 0x00010004 0x0000003b
450- 0x00010005 0x00000043
451- 0x00010006 0x0000004b
452- 0x00010007 0x00000055
453- 0x00010008 0x0000005d
454- 0x00010009 0x00000067
455- 0x0001000a 0x00000070
456-
457- 0x00020000 0x00000017
458- 0x00020001 0x00000023
459- 0x00020002 0x0000002d
460- 0x00020003 0x00000037
461- 0x00020004 0x00000041
462- 0x00020005 0x0000004b
463- 0x00020006 0x00000057
464- 0x00020007 0x00000063
465- 0x00020008 0x0000006f
466-
467- 0x00030000 0x00000015
468- 0x00030001 0x00000021
469- 0x00030002 0x0000002d
470- 0x00030003 0x00000039
471- 0x00030004 0x00000045
472- 0x00030005 0x00000053
473- 0x00030006 0x0000005f
474- 0x00030007 0x00000071>;
467+ fsl,tmu-calibration = <0x00000000 0x00000023>,
468+ <0x00000001 0x00000029>,
469+ <0x00000002 0x0000002f>,
470+ <0x00000003 0x00000035>,
471+ <0x00000004 0x0000003d>,
472+ <0x00000005 0x00000043>,
473+ <0x00000006 0x0000004b>,
474+ <0x00000007 0x00000051>,
475+ <0x00000008 0x00000057>,
476+ <0x00000009 0x0000005f>,
477+ <0x0000000a 0x00000067>,
478+ <0x0000000b 0x0000006f>,
479+
480+ <0x00010000 0x0000001b>,
481+ <0x00010001 0x00000023>,
482+ <0x00010002 0x0000002b>,
483+ <0x00010003 0x00000033>,
484+ <0x00010004 0x0000003b>,
485+ <0x00010005 0x00000043>,
486+ <0x00010006 0x0000004b>,
487+ <0x00010007 0x00000055>,
488+ <0x00010008 0x0000005d>,
489+ <0x00010009 0x00000067>,
490+ <0x0001000a 0x00000070>,
491+
492+ <0x00020000 0x00000017>,
493+ <0x00020001 0x00000023>,
494+ <0x00020002 0x0000002d>,
495+ <0x00020003 0x00000037>,
496+ <0x00020004 0x00000041>,
497+ <0x00020005 0x0000004b>,
498+ <0x00020006 0x00000057>,
499+ <0x00020007 0x00000063>,
500+ <0x00020008 0x0000006f>,
501+
502+ <0x00030000 0x00000015>,
503+ <0x00030001 0x00000021>,
504+ <0x00030002 0x0000002d>,
505+ <0x00030003 0x00000039>,
506+ <0x00030004 0x00000045>,
507+ <0x00030005 0x00000053>,
508+ <0x00030006 0x0000005f>,
509+ <0x00030007 0x00000071>;
475510 #thermal-sensor-cells = <1>;
476511 };
477512
@@ -526,7 +561,7 @@
526561 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
527562 status = "disabled";
528563
529- port@0 {
564+ port {
530565 lcdif_mipi_dsi: endpoint {
531566 remote-endpoint = <&mipi_dsi_lcdif_in>;
532567 };
@@ -709,7 +744,21 @@
709744 pgc_vpu: power-domain@6 {
710745 #power-domain-cells = <0>;
711746 reg = <IMX8M_POWER_DOMAIN_VPU>;
712- clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
747+ clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
748+ <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
749+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
750+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
751+ <&clk IMX8MQ_CLK_VPU_G2>,
752+ <&clk IMX8MQ_CLK_VPU_BUS>,
753+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
754+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
755+ <&clk IMX8MQ_VPU_PLL_OUT>,
756+ <&clk IMX8MQ_SYS1_PLL_800M>,
757+ <&clk IMX8MQ_VPU_PLL>;
758+ assigned-clock-rates = <600000000>,
759+ <600000000>,
760+ <800000000>,
761+ <0>;
713762 };
714763
715764 pgc_disp: power-domain@7 {
@@ -749,7 +798,7 @@
749798 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
750799 <&clk IMX8MQ_CLK_PWM1_ROOT>;
751800 clock-names = "ipg", "per";
752- #pwm-cells = <2>;
801+ #pwm-cells = <3>;
753802 status = "disabled";
754803 };
755804
@@ -760,7 +809,7 @@
760809 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
761810 <&clk IMX8MQ_CLK_PWM2_ROOT>;
762811 clock-names = "ipg", "per";
763- #pwm-cells = <2>;
812+ #pwm-cells = <3>;
764813 status = "disabled";
765814 };
766815
@@ -771,7 +820,7 @@
771820 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
772821 <&clk IMX8MQ_CLK_PWM3_ROOT>;
773822 clock-names = "ipg", "per";
774- #pwm-cells = <2>;
823+ #pwm-cells = <3>;
775824 status = "disabled";
776825 };
777826
@@ -782,7 +831,7 @@
782831 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
783832 <&clk IMX8MQ_CLK_PWM4_ROOT>;
784833 clock-names = "ipg", "per";
785- #pwm-cells = <2>;
834+ #pwm-cells = <3>;
786835 status = "disabled";
787836 };
788837
@@ -1123,8 +1172,8 @@
11231172 #address-cells = <1>;
11241173 #size-cells = <0>;
11251174
1126- port@0 {
1127- reg = <0>;
1175+ port@1 {
1176+ reg = <1>;
11281177
11291178 csi1_mipi_ep: endpoint {
11301179 remote-endpoint = <&csi1_ep>;
@@ -1175,8 +1224,8 @@
11751224 #address-cells = <1>;
11761225 #size-cells = <0>;
11771226
1178- port@0 {
1179- reg = <0>;
1227+ port@1 {
1228+ reg = <1>;
11801229
11811230 csi2_mipi_ep: endpoint {
11821231 remote-endpoint = <&csi2_ep>;
@@ -1290,7 +1339,6 @@
12901339 fsl,num-rx-queues = <3>;
12911340 nvmem-cells = <&fec_mac_address>;
12921341 nvmem-cell-names = "mac-address";
1293- nvmem_macaddr_swap;
12941342 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
12951343 status = "disabled";
12961344 };
@@ -1430,30 +1478,31 @@
14301478 status = "disabled";
14311479 };
14321480
1433- vpu: video-codec@38300000 {
1434- compatible = "nxp,imx8mq-vpu";
1435- reg = <0x38300000 0x10000>,
1436- <0x38310000 0x10000>,
1437- <0x38320000 0x10000>;
1438- reg-names = "g1", "g2", "ctrl";
1439- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1440- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1441- interrupt-names = "g1", "g2";
1481+ vpu_g1: video-codec@38300000 {
1482+ compatible = "nxp,imx8mq-vpu-g1";
1483+ reg = <0x38300000 0x10000>;
1484+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1485+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
1486+ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1487+ };
1488+
1489+ vpu_g2: video-codec@38310000 {
1490+ compatible = "nxp,imx8mq-vpu-g2";
1491+ reg = <0x38310000 0x10000>;
1492+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1493+ clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1494+ power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1495+ };
1496+
1497+ vpu_blk_ctrl: blk-ctrl@38320000 {
1498+ compatible = "fsl,imx8mq-vpu-blk-ctrl";
1499+ reg = <0x38320000 0x100>;
1500+ power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1501+ power-domain-names = "bus", "g1", "g2";
14421502 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1443- <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1444- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1445- clock-names = "g1", "g2", "bus";
1446- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1447- <&clk IMX8MQ_CLK_VPU_G2>,
1448- <&clk IMX8MQ_CLK_VPU_BUS>,
1449- <&clk IMX8MQ_VPU_PLL_BYPASS>;
1450- assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1451- <&clk IMX8MQ_VPU_PLL_OUT>,
1452- <&clk IMX8MQ_SYS1_PLL_800M>,
1453- <&clk IMX8MQ_VPU_PLL>;
1454- assigned-clock-rates = <600000000>, <600000000>,
1455- <800000000>, <0>;
1456- power-domains = <&pgc_vpu>;
1503+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1504+ clock-names = "g1", "g2";
1505+ #power-domain-cells = <1>;
14571506 };
14581507
14591508 pcie0: pcie@33800000 {
@@ -1552,6 +1601,7 @@
15521601 <&clk IMX8MQ_DRAM_PLL_OUT>,
15531602 <&clk IMX8MQ_CLK_DRAM_ALT>,
15541603 <&clk IMX8MQ_CLK_DRAM_APB>;
1604+ status = "disabled";
15551605 };
15561606
15571607 ddr-pmu@3d800000 {
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -405,25 +405,6 @@
405405
406406 #define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
407407
408-#define IMX8MQ_SYS1_PLL_40M_CG 267
409-#define IMX8MQ_SYS1_PLL_80M_CG 268
410-#define IMX8MQ_SYS1_PLL_100M_CG 269
411-#define IMX8MQ_SYS1_PLL_133M_CG 270
412-#define IMX8MQ_SYS1_PLL_160M_CG 271
413-#define IMX8MQ_SYS1_PLL_200M_CG 272
414-#define IMX8MQ_SYS1_PLL_266M_CG 273
415-#define IMX8MQ_SYS1_PLL_400M_CG 274
416-#define IMX8MQ_SYS1_PLL_800M_CG 275
417-#define IMX8MQ_SYS2_PLL_50M_CG 276
418-#define IMX8MQ_SYS2_PLL_100M_CG 277
419-#define IMX8MQ_SYS2_PLL_125M_CG 278
420-#define IMX8MQ_SYS2_PLL_166M_CG 279
421-#define IMX8MQ_SYS2_PLL_200M_CG 280
422-#define IMX8MQ_SYS2_PLL_250M_CG 281
423-#define IMX8MQ_SYS2_PLL_333M_CG 282
424-#define IMX8MQ_SYS2_PLL_500M_CG 283
425-#define IMX8MQ_SYS2_PLL_1000M_CG 284
426-
427408 #define IMX8MQ_CLK_GPU_CORE 285
428409 #define IMX8MQ_CLK_GPU_SHADER 286
429410 #define IMX8MQ_CLK_M4_CORE 287
--- a/include/dt-bindings/power/imx8mq-power.h
+++ b/include/dt-bindings/power/imx8mq-power.h
@@ -18,4 +18,7 @@
1818 #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
1919 #define IMX8M_POWER_DOMAIN_PCIE2 10
2020
21+#define IMX8MQ_VPUBLK_PD_G1 0
22+#define IMX8MQ_VPUBLK_PD_G2 1
23+
2124 #endif