| 修订版 | 6b95d5793b0faebc5f28ecf0cf39ffcbb3e431cf (tree) |
|---|---|
| 时间 | 2020-07-26 18:22:19 |
| 作者 | Yoshinori Sato <ysato@user...> |
| Commiter | Yoshinori Sato |
Add QEMU virtial target
arch/rx/dts/rx-virt.dts (diff)| @@ -0,0 +1,94 @@ | ||
| 1 | +/dts-v1/; | |
| 2 | +/ { | |
| 3 | + model = "QEMU rx-virt"; | |
| 4 | + compatible = "qemu,rx-virt"; | |
| 5 | + #address-cells = <1>; | |
| 6 | + #size-cells = <1>; | |
| 7 | + | |
| 8 | + interrupt-parent = <&rxicu>; | |
| 9 | + | |
| 10 | + chosen { | |
| 11 | + stdout-path = "serial0:38400"; | |
| 12 | + }; | |
| 13 | + aliases { | |
| 14 | + serial0 = &sci0; | |
| 15 | + serial1 = &sci1; | |
| 16 | + }; | |
| 17 | + | |
| 18 | + xclk: oscillator { | |
| 19 | + #clock-cells = <0>; | |
| 20 | + compatible = "fixed-clock"; | |
| 21 | + clock-frequency = <12000000>; | |
| 22 | + clock-output-names = "xtal"; | |
| 23 | + }; | |
| 24 | + pllclk: pllclk { | |
| 25 | + #clock-cells = <0>; | |
| 26 | + compatible = "fixed-factor-clock"; | |
| 27 | + clock-mult = <8>; | |
| 28 | + clocks = <&xclk>; | |
| 29 | + clock-output-names = "pll"; | |
| 30 | + }; | |
| 31 | + | |
| 32 | + pck: pck { | |
| 33 | + #clock-cells = <0>; | |
| 34 | + compatible = "renesas,rx62n-cpg"; | |
| 35 | + clocks = <&pllclk>; | |
| 36 | + reg = <0x00080020 4>; | |
| 37 | + clock-names = "fck"; | |
| 38 | + }; | |
| 39 | + bck: bck { | |
| 40 | + compatible = "renesas,rx62n-cpg"; | |
| 41 | + clocks = <&pllclk>; | |
| 42 | + #clock-cells = <0>; | |
| 43 | + reg = <0x00080020 4>; | |
| 44 | + }; | |
| 45 | + ick: ick { | |
| 46 | + compatible = "renesas,rx62n-cpg"; | |
| 47 | + clocks = <&pllclk>; | |
| 48 | + #clock-cells = <0>; | |
| 49 | + reg = <0x00080020 4>; | |
| 50 | + }; | |
| 51 | + | |
| 52 | + cpus { | |
| 53 | + #address-cells = <1>; | |
| 54 | + #size-cells = <0>; | |
| 55 | + cpu@0 { | |
| 56 | + compatible = "renesas,rx"; | |
| 57 | + clocks = <&ick>; | |
| 58 | + mem-cycle = <2>; | |
| 59 | + }; | |
| 60 | + }; | |
| 61 | + memory@01000000 { | |
| 62 | + device_type = "memory"; | |
| 63 | + reg = <0x01000000 0x01000000>; | |
| 64 | + }; | |
| 65 | + | |
| 66 | + rxicu: interrupt-controller@87000 { | |
| 67 | + compatible = "renesas,rx-icu"; | |
| 68 | + #interrupt-cells = <2>; | |
| 69 | + interrupt-controller; | |
| 70 | + reg = <0x00087000 0x600>; | |
| 71 | + }; | |
| 72 | + | |
| 73 | + mtu: timer@00088600 { | |
| 74 | + compatible = "renesas,rx-mtu2"; | |
| 75 | + reg = <0x00088600 0x600>; | |
| 76 | + clocks = <&pck>; | |
| 77 | + }; | |
| 78 | + | |
| 79 | + sci0: serial@00088240 { | |
| 80 | + compatible = "renesas,sci"; | |
| 81 | + reg = <0x00088240 8>; | |
| 82 | + interrupts = <214 0>, <215 0>, <216 0>, <217 0>; | |
| 83 | + clock-names = "fck", "pck"; | |
| 84 | + clocks = <&pck>; | |
| 85 | + }; | |
| 86 | + | |
| 87 | + sci1: serial@00088248 { | |
| 88 | + compatible = "renesas,sci"; | |
| 89 | + reg = <0x00088248 8>; | |
| 90 | + interrupts = <218 0>, <219 0>, <220 0>, <221 0>; | |
| 91 | + clock-names = "fck", "pck"; | |
| 92 | + clocks = <&pck>; | |
| 93 | + }; | |
| 94 | +}; |
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