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修订版71f07731488e9ade674ee396208317ab2db3cce1 (tree)
时间2022-07-26 15:23:54
作者Ashok Reddy Soma <ashok.reddy.soma@xili...>
CommiterMichal Simek

Log Message

mmc: zynq_sdhci: Fix timing macros for MMC High speed

Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

更改概述

差异

--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -101,8 +101,8 @@ static const u8 mode2timing[] = {
101101 [MMC_LEGACY] = MMC_TIMING_LEGACY,
102102 [MMC_HS] = MMC_TIMING_MMC_HS,
103103 [SD_HS] = MMC_TIMING_SD_HS,
104- [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
105- [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
104+ [MMC_HS_52] = MMC_TIMING_MMC_HS,
105+ [MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
106106 [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
107107 [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
108108 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,