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修订版a4a9d9e874bffa509c31d0752b8155e653f9093f (tree)
时间2022-07-26 02:02:04
作者Sumit Garg <sumit.garg@lina...>
CommiterTom Rini

Log Message

clocks: qcom: Add clock driver for QCS404 SoC

Currently this clock driver initializes clocks for UART and eMMC. Along
with this import "qcom,gcc-qcs404.h" header from Linux mainline to
support DT bindings.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

更改概述

差异

--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -0,0 +1,79 @@
1+// SPDX-License-Identifier: BSD-3-Clause
2+/*
3+ * Clock drivers for Qualcomm QCS404
4+ *
5+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6+ */
7+
8+#include <common.h>
9+#include <clk-uclass.h>
10+#include <dm.h>
11+#include <errno.h>
12+#include <asm/io.h>
13+#include <linux/bitops.h>
14+#include "clock-snapdragon.h"
15+
16+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
17+
18+/* GPLL0 clock control registers */
19+#define GPLL0_STATUS_ACTIVE BIT(31)
20+
21+static struct vote_clk gcc_blsp1_ahb_clk = {
22+ .cbcr_reg = BLSP1_AHB_CBCR,
23+ .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
24+ .vote_bit = BIT(10) | BIT(5) | BIT(4),
25+};
26+
27+static const struct bcr_regs uart2_regs = {
28+ .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
29+ .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
30+ .M = BLSP1_UART2_APPS_M,
31+ .N = BLSP1_UART2_APPS_N,
32+ .D = BLSP1_UART2_APPS_D,
33+};
34+
35+static const struct bcr_regs sdc_regs = {
36+ .cfg_rcgr = SDCC_CFG_RCGR(1),
37+ .cmd_rcgr = SDCC_CMD_RCGR(1),
38+ .M = SDCC_M(1),
39+ .N = SDCC_N(1),
40+ .D = SDCC_D(1),
41+};
42+
43+static struct pll_vote_clk gpll0_vote_clk = {
44+ .status = GPLL0_STATUS,
45+ .status_bit = GPLL0_STATUS_ACTIVE,
46+ .ena_vote = APCS_GPLL_ENA_VOTE,
47+ .vote_bit = BIT(0),
48+};
49+
50+ulong msm_set_rate(struct clk *clk, ulong rate)
51+{
52+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
53+
54+ switch (clk->id) {
55+ case GCC_BLSP1_UART2_APPS_CLK:
56+ /* UART: 115200 */
57+ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
58+ CFG_CLK_SRC_CXO);
59+ clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
60+ break;
61+ case GCC_BLSP1_AHB_CLK:
62+ clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
63+ break;
64+ case GCC_SDCC1_APPS_CLK:
65+ /* SDCC1: 200MHz */
66+ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
67+ CFG_CLK_SRC_GPLL0);
68+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
69+ clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
70+ break;
71+ case GCC_SDCC1_AHB_CLK:
72+ clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
73+ break;
74+ default:
75+ return 0;
76+ }
77+
78+ return 0;
79+}
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
136136 { .compatible = "qcom,gcc-msm8996" },
137137 { .compatible = "qcom,gcc-apq8096" },
138138 { .compatible = "qcom,gcc-sdm845" },
139+ { .compatible = "qcom,gcc-qcs404" },
139140 { }
140141 };
141142
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -0,0 +1,40 @@
1+/* SPDX-License-Identifier: GPL-2.0+ */
2+/*
3+ * Qualcomm QCS404 sysmap
4+ *
5+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6+ */
7+#ifndef _MACH_SYSMAP_QCS404_H
8+#define _MACH_SYSMAP_QCS404_H
9+
10+#define GICD_BASE (0x0b000000)
11+#define GICC_BASE (0x0b002000)
12+
13+/* Clocks: (from CLK_CTL_BASE) */
14+#define GPLL0_STATUS (0x21000)
15+#define APCS_GPLL_ENA_VOTE (0x45000)
16+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
17+
18+/* BLSP1 AHB clock (root clock for BLSP) */
19+#define BLSP1_AHB_CBCR 0x1008
20+
21+/* Uart clock control registers */
22+#define BLSP1_UART2_BCR (0x3028)
23+#define BLSP1_UART2_APPS_CBCR (0x302C)
24+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
25+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
26+#define BLSP1_UART2_APPS_M (0x303C)
27+#define BLSP1_UART2_APPS_N (0x3040)
28+#define BLSP1_UART2_APPS_D (0x3044)
29+
30+/* SD controller clock control registers */
31+#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
32+#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
33+#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
34+#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
35+#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
36+#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
37+#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
38+#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
39+
40+#endif
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,180 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4+ */
5+
6+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
7+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
8+
9+#define GCC_APSS_AHB_CLK_SRC 0
10+#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
11+#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
12+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
13+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
14+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
15+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
16+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
17+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
18+#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
19+#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
20+#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
21+#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
22+#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
23+#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
24+#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
25+#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
26+#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
27+#define GCC_BYTE0_CLK_SRC 18
28+#define GCC_EMAC_CLK_SRC 19
29+#define GCC_EMAC_PTP_CLK_SRC 20
30+#define GCC_ESC0_CLK_SRC 21
31+#define GCC_APSS_AHB_CLK 22
32+#define GCC_APSS_AXI_CLK 23
33+#define GCC_BIMC_APSS_AXI_CLK 24
34+#define GCC_BIMC_GFX_CLK 25
35+#define GCC_BIMC_MDSS_CLK 26
36+#define GCC_BLSP1_AHB_CLK 27
37+#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
38+#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
39+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
40+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
41+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
42+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
43+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
44+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
45+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
46+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
47+#define GCC_BLSP1_UART0_APPS_CLK 38
48+#define GCC_BLSP1_UART1_APPS_CLK 39
49+#define GCC_BLSP1_UART2_APPS_CLK 40
50+#define GCC_BLSP1_UART3_APPS_CLK 41
51+#define GCC_BLSP2_AHB_CLK 42
52+#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
53+#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
54+#define GCC_BLSP2_UART0_APPS_CLK 45
55+#define GCC_BOOT_ROM_AHB_CLK 46
56+#define GCC_DCC_CLK 47
57+#define GCC_GENI_IR_H_CLK 48
58+#define GCC_ETH_AXI_CLK 49
59+#define GCC_ETH_PTP_CLK 50
60+#define GCC_ETH_RGMII_CLK 51
61+#define GCC_ETH_SLAVE_AHB_CLK 52
62+#define GCC_GENI_IR_S_CLK 53
63+#define GCC_GP1_CLK 54
64+#define GCC_GP2_CLK 55
65+#define GCC_GP3_CLK 56
66+#define GCC_MDSS_AHB_CLK 57
67+#define GCC_MDSS_AXI_CLK 58
68+#define GCC_MDSS_BYTE0_CLK 59
69+#define GCC_MDSS_ESC0_CLK 60
70+#define GCC_MDSS_HDMI_APP_CLK 61
71+#define GCC_MDSS_HDMI_PCLK_CLK 62
72+#define GCC_MDSS_MDP_CLK 63
73+#define GCC_MDSS_PCLK0_CLK 64
74+#define GCC_MDSS_VSYNC_CLK 65
75+#define GCC_OXILI_AHB_CLK 66
76+#define GCC_OXILI_GFX3D_CLK 67
77+#define GCC_PCIE_0_AUX_CLK 68
78+#define GCC_PCIE_0_CFG_AHB_CLK 69
79+#define GCC_PCIE_0_MSTR_AXI_CLK 70
80+#define GCC_PCIE_0_PIPE_CLK 71
81+#define GCC_PCIE_0_SLV_AXI_CLK 72
82+#define GCC_PCNOC_USB2_CLK 73
83+#define GCC_PCNOC_USB3_CLK 74
84+#define GCC_PDM2_CLK 75
85+#define GCC_PDM_AHB_CLK 76
86+#define GCC_VSYNC_CLK_SRC 77
87+#define GCC_PRNG_AHB_CLK 78
88+#define GCC_PWM0_XO512_CLK 79
89+#define GCC_PWM1_XO512_CLK 80
90+#define GCC_PWM2_XO512_CLK 81
91+#define GCC_SDCC1_AHB_CLK 82
92+#define GCC_SDCC1_APPS_CLK 83
93+#define GCC_SDCC1_ICE_CORE_CLK 84
94+#define GCC_SDCC2_AHB_CLK 85
95+#define GCC_SDCC2_APPS_CLK 86
96+#define GCC_SYS_NOC_USB3_CLK 87
97+#define GCC_USB20_MOCK_UTMI_CLK 88
98+#define GCC_USB2A_PHY_SLEEP_CLK 89
99+#define GCC_USB30_MASTER_CLK 90
100+#define GCC_USB30_MOCK_UTMI_CLK 91
101+#define GCC_USB30_SLEEP_CLK 92
102+#define GCC_USB3_PHY_AUX_CLK 93
103+#define GCC_USB3_PHY_PIPE_CLK 94
104+#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
105+#define GCC_USB_HS_SYSTEM_CLK 96
106+#define GCC_GFX3D_CLK_SRC 97
107+#define GCC_GP1_CLK_SRC 98
108+#define GCC_GP2_CLK_SRC 99
109+#define GCC_GP3_CLK_SRC 100
110+#define GCC_GPLL0_OUT_MAIN 101
111+#define GCC_GPLL1_OUT_MAIN 102
112+#define GCC_GPLL3_OUT_MAIN 103
113+#define GCC_GPLL4_OUT_MAIN 104
114+#define GCC_HDMI_APP_CLK_SRC 105
115+#define GCC_HDMI_PCLK_CLK_SRC 106
116+#define GCC_MDP_CLK_SRC 107
117+#define GCC_PCIE_0_AUX_CLK_SRC 108
118+#define GCC_PCIE_0_PIPE_CLK_SRC 109
119+#define GCC_PCLK0_CLK_SRC 110
120+#define GCC_PDM2_CLK_SRC 111
121+#define GCC_SDCC1_APPS_CLK_SRC 112
122+#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
123+#define GCC_SDCC2_APPS_CLK_SRC 114
124+#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
125+#define GCC_USB30_MASTER_CLK_SRC 116
126+#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
127+#define GCC_USB3_PHY_AUX_CLK_SRC 118
128+#define GCC_USB_HS_SYSTEM_CLK_SRC 119
129+#define GCC_GPLL0_AO_CLK_SRC 120
130+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
131+#define GCC_GPLL0_AO_OUT_MAIN 123
132+#define GCC_GPLL0_SLEEP_CLK_SRC 124
133+#define GCC_GPLL6 125
134+#define GCC_GPLL6_OUT_AUX 126
135+#define GCC_MDSS_MDP_VOTE_CLK 127
136+#define GCC_MDSS_ROTATOR_VOTE_CLK 128
137+#define GCC_BIMC_GPU_CLK 129
138+#define GCC_GTCU_AHB_CLK 130
139+#define GCC_GFX_TCU_CLK 131
140+#define GCC_GFX_TBU_CLK 132
141+#define GCC_SMMU_CFG_CLK 133
142+#define GCC_APSS_TCU_CLK 134
143+#define GCC_CRYPTO_AHB_CLK 135
144+#define GCC_CRYPTO_AXI_CLK 136
145+#define GCC_CRYPTO_CLK 137
146+#define GCC_MDP_TBU_CLK 138
147+#define GCC_QDSS_DAP_CLK 139
148+#define GCC_DCC_XO_CLK 140
149+#define GCC_WCSS_Q6_AHB_CLK 141
150+#define GCC_WCSS_Q6_AXIM_CLK 142
151+#define GCC_CDSP_CFG_AHB_CLK 143
152+#define GCC_BIMC_CDSP_CLK 144
153+#define GCC_CDSP_TBU_CLK 145
154+#define GCC_CDSP_BIMC_CLK_SRC 146
155+
156+#define GCC_GENI_IR_BCR 0
157+#define GCC_USB_HS_BCR 1
158+#define GCC_USB2_HS_PHY_ONLY_BCR 2
159+#define GCC_QUSB2_PHY_BCR 3
160+#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
161+#define GCC_USB2A_PHY_BCR 5
162+#define GCC_USB3_PHY_BCR 6
163+#define GCC_USB_30_BCR 7
164+#define GCC_USB3PHY_PHY_BCR 8
165+#define GCC_PCIE_0_BCR 9
166+#define GCC_PCIE_0_PHY_BCR 10
167+#define GCC_PCIE_0_LINK_DOWN_BCR 11
168+#define GCC_PCIEPHY_0_PHY_BCR 12
169+#define GCC_EMAC_BCR 13
170+#define GCC_CDSP_RESTART 14
171+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
172+#define GCC_PCIE_0_AHB_ARES 16
173+#define GCC_PCIE_0_AXI_SLAVE_ARES 17
174+#define GCC_PCIE_0_AXI_MASTER_ARES 18
175+#define GCC_PCIE_0_CORE_STICKY_ARES 19
176+#define GCC_PCIE_0_SLEEP_ARES 20
177+#define GCC_PCIE_0_PIPE_ARES 21
178+#define GCC_WDSP_RESTART 22
179+
180+#endif