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修订版e0caa84ca68505193f6044fad3f9939af8d4d1ee (tree)
时间2022-07-25 23:12:01
作者Marcel Ziswiler <marcel.ziswiler@tora...>
CommiterStefano Babic

Log Message

imx8mp: synchronise device tree with linux

Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

更改概述

差异

--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -74,11 +74,21 @@
7474 status = "okay";
7575 };
7676
77+&flexcan2 {
78+ pinctrl-names = "default";
79+ pinctrl-0 = <&pinctrl_flexcan2>;
80+ xceiver-supply = <&reg_can2_stby>;
81+ status = "disabled";/* can2 pin conflict with pdm */
82+};
83+
7784 &eqos {
7885 pinctrl-names = "default";
7986 pinctrl-0 = <&pinctrl_eqos>;
8087 phy-mode = "rgmii-id";
8188 phy-handle = <&ethphy0>;
89+ snps,force_thresh_dma_mode;
90+ snps,mtl-tx-config = <&mtl_tx_setup>;
91+ snps,mtl-rx-config = <&mtl_rx_setup>;
8292 status = "okay";
8393
8494 mdio {
@@ -90,15 +100,77 @@
90100 compatible = "ethernet-phy-ieee802.3-c22";
91101 reg = <1>;
92102 eee-broken-1000t;
103+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
104+ reset-assert-us = <10000>;
105+ reset-deassert-us = <80000>;
106+ realtek,clkout-disable;
93107 };
94108 };
95-};
96109
97-&flexcan2 {
98- pinctrl-names = "default";
99- pinctrl-0 = <&pinctrl_flexcan2>;
100- xceiver-supply = <&reg_can2_stby>;
101- status = "disabled";/* can2 pin conflict with pdm */
110+ mtl_tx_setup: tx-queues-config {
111+ snps,tx-queues-to-use = <5>;
112+ snps,tx-sched-sp;
113+
114+ queue0 {
115+ snps,dcb-algorithm;
116+ snps,priority = <0x1>;
117+ };
118+
119+ queue1 {
120+ snps,dcb-algorithm;
121+ snps,priority = <0x2>;
122+ };
123+
124+ queue2 {
125+ snps,dcb-algorithm;
126+ snps,priority = <0x4>;
127+ };
128+
129+ queue3 {
130+ snps,dcb-algorithm;
131+ snps,priority = <0x8>;
132+ };
133+
134+ queue4 {
135+ snps,dcb-algorithm;
136+ snps,priority = <0xf0>;
137+ };
138+ };
139+
140+ mtl_rx_setup: rx-queues-config {
141+ snps,rx-queues-to-use = <5>;
142+ snps,rx-sched-sp;
143+
144+ queue0 {
145+ snps,dcb-algorithm;
146+ snps,priority = <0x1>;
147+ snps,map-to-dma-channel = <0>;
148+ };
149+
150+ queue1 {
151+ snps,dcb-algorithm;
152+ snps,priority = <0x2>;
153+ snps,map-to-dma-channel = <1>;
154+ };
155+
156+ queue2 {
157+ snps,dcb-algorithm;
158+ snps,priority = <0x4>;
159+ snps,map-to-dma-channel = <2>;
160+ };
161+
162+ queue3 {
163+ snps,dcb-algorithm;
164+ snps,priority = <0x8>;
165+ snps,map-to-dma-channel = <3>;
166+ };
167+
168+ queue4 {
169+ snps,dcb-algorithm;
170+ snps,priority = <0xf0>;
171+ snps,map-to-dma-channel = <4>;
172+ };
173+ };
102174 };
103175
104176 &fec {
@@ -118,6 +190,95 @@
118190 reg = <1>;
119191 eee-broken-1000t;
120192 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
193+ reset-assert-us = <10000>;
194+ reset-deassert-us = <80000>;
195+ realtek,clkout-disable;
196+ };
197+ };
198+};
199+
200+&i2c1 {
201+ clock-frequency = <400000>;
202+ pinctrl-names = "default";
203+ pinctrl-0 = <&pinctrl_i2c1>;
204+ status = "okay";
205+
206+ pmic@25 {
207+ compatible = "nxp,pca9450c";
208+ reg = <0x25>;
209+ pinctrl-names = "default";
210+ pinctrl-0 = <&pinctrl_pmic>;
211+ interrupt-parent = <&gpio1>;
212+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
213+
214+ regulators {
215+ BUCK1 {
216+ regulator-name = "BUCK1";
217+ regulator-min-microvolt = <720000>;
218+ regulator-max-microvolt = <1000000>;
219+ regulator-boot-on;
220+ regulator-always-on;
221+ regulator-ramp-delay = <3125>;
222+ };
223+
224+ BUCK2 {
225+ regulator-name = "BUCK2";
226+ regulator-min-microvolt = <720000>;
227+ regulator-max-microvolt = <1025000>;
228+ regulator-boot-on;
229+ regulator-always-on;
230+ regulator-ramp-delay = <3125>;
231+ nxp,dvs-run-voltage = <950000>;
232+ nxp,dvs-standby-voltage = <850000>;
233+ };
234+
235+ BUCK4 {
236+ regulator-name = "BUCK4";
237+ regulator-min-microvolt = <3000000>;
238+ regulator-max-microvolt = <3600000>;
239+ regulator-boot-on;
240+ regulator-always-on;
241+ };
242+
243+ BUCK5 {
244+ regulator-name = "BUCK5";
245+ regulator-min-microvolt = <1650000>;
246+ regulator-max-microvolt = <1950000>;
247+ regulator-boot-on;
248+ regulator-always-on;
249+ };
250+
251+ BUCK6 {
252+ regulator-name = "BUCK6";
253+ regulator-min-microvolt = <1045000>;
254+ regulator-max-microvolt = <1155000>;
255+ regulator-boot-on;
256+ regulator-always-on;
257+ };
258+
259+ LDO1 {
260+ regulator-name = "LDO1";
261+ regulator-min-microvolt = <1650000>;
262+ regulator-max-microvolt = <1950000>;
263+ regulator-boot-on;
264+ regulator-always-on;
265+ };
266+
267+ LDO3 {
268+ regulator-name = "LDO3";
269+ regulator-min-microvolt = <1710000>;
270+ regulator-max-microvolt = <1890000>;
271+ regulator-boot-on;
272+ regulator-always-on;
273+ };
274+
275+ LDO5 {
276+ regulator-name = "LDO5";
277+ regulator-min-microvolt = <1800000>;
278+ regulator-max-microvolt = <3300000>;
279+ regulator-boot-on;
280+ regulator-always-on;
281+ };
121282 };
122283 };
123284 };
@@ -133,9 +294,46 @@
133294 reg = <0x20>;
134295 gpio-controller;
135296 #gpio-cells = <2>;
297+ interrupt-controller;
298+ #interrupt-cells = <2>;
299+ pinctrl-names = "default";
300+ pinctrl-0 = <&pinctrl_pca6416_int>;
301+ interrupt-parent = <&gpio1>;
302+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
303+ gpio-line-names = "EXT_PWREN1",
304+ "EXT_PWREN2",
305+ "CAN1/I2C5_SEL",
306+ "PDM/CAN2_SEL",
307+ "FAN_EN",
308+ "PWR_MEAS_IO1",
309+ "PWR_MEAS_IO2",
310+ "EXP_P0_7",
311+ "EXP_P1_0",
312+ "EXP_P1_1",
313+ "EXP_P1_2",
314+ "EXP_P1_3",
315+ "EXP_P1_4",
316+ "EXP_P1_5",
317+ "EXP_P1_6",
318+ "EXP_P1_7";
136319 };
137320 };
138321
322+/* I2C on expansion connector J22. */
323+&i2c5 {
324+ clock-frequency = <100000>; /* Lower clock speed for external bus. */
325+ pinctrl-names = "default";
326+ pinctrl-0 = <&pinctrl_i2c5>;
327+ status = "disabled"; /* can1 pins conflict with i2c5 */
328+
329+ /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
330+ * LOW: CAN1 (default, pull-down)
331+ * HIGH: I2C5
332+ * You need to set it to high to enable I2C5 (for example, add gpio-hog
333+ * in pca6416 node).
334+ */
335+};
336+
139337 &snvs_pwrkey {
140338 status = "okay";
141339 };
@@ -147,6 +345,21 @@
147345 status = "okay";
148346 };
149347
348+&usb3_phy1 {
349+ status = "okay";
350+};
351+
352+&usb3_1 {
353+ status = "okay";
354+};
355+
356+&usb_dwc3_1 {
357+ pinctrl-names = "default";
358+ pinctrl-0 = <&pinctrl_usb1_vbus>;
359+ dr_mode = "host";
360+ status = "okay";
361+};
362+
150363 &usdhc2 {
151364 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
152365 assigned-clock-rates = <400000000>;
@@ -182,21 +395,21 @@
182395 &iomuxc {
183396 pinctrl_eqos: eqosgrp {
184397 fsl,pins = <
185- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
186- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
187- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
188- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
189- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
190- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
398+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
399+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
400+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
401+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
402+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
403+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
191404 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
192- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
193- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
194- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
195- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
196- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
197- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
405+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
406+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
407+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
408+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
409+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
410+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
198411 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
199- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
412+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
200413 >;
201414 };
202415
@@ -252,6 +465,13 @@
252465 >;
253466 };
254467
468+ pinctrl_i2c1: i2c1grp {
469+ fsl,pins = <
470+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
471+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
472+ >;
473+ };
474+
255475 pinctrl_i2c3: i2c3grp {
256476 fsl,pins = <
257477 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
@@ -259,6 +479,25 @@
259479 >;
260480 };
261481
482+ pinctrl_i2c5: i2c5grp {
483+ fsl,pins = <
484+ MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
485+ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
486+ >;
487+ };
488+
489+ pinctrl_pmic: pmicgrp {
490+ fsl,pins = <
491+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
492+ >;
493+ };
494+
495+ pinctrl_pca6416_int: pca6416_int_grp {
496+ fsl,pins = <
497+ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
498+ >;
499+ };
500+
262501 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
263502 fsl,pins = <
264503 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
@@ -272,6 +511,12 @@
272511 >;
273512 };
274513
514+ pinctrl_usb1_vbus: usb1grp {
515+ fsl,pins = <
516+ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
517+ >;
518+ };
519+
275520 pinctrl_usdhc2: usdhc2grp {
276521 fsl,pins = <
277522 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
--- a/arch/arm/dts/imx8mp-phycore-som.dtsi
+++ b/arch/arm/dts/imx8mp-phycore-som.dtsi
@@ -60,11 +60,26 @@
6060 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
6161 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
6262 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
63+ ti,min-output-impedance;
6364 enet-phy-lane-no-swap;
6465 };
6566 };
6667 };
6768
69+&flexspi {
70+ pinctrl-names = "default";
71+ pinctrl-0 = <&pinctrl_flexspi0>;
72+ status = "okay";
73+
74+ som_flash: flash@0 {
75+ compatible = "jedec,spi-nor";
76+ reg = <0>;
77+ spi-max-frequency = <80000000>;
78+ spi-tx-bus-width = <1>;
79+ spi-rx-bus-width = <4>;
80+ };
81+};
82+
6883 &i2c1 {
6984 clock-frequency = <400000>;
7085 pinctrl-names = "default", "gpio";
@@ -99,6 +114,8 @@
99114 regulator-boot-on;
100115 regulator-always-on;
101116 regulator-ramp-delay = <3125>;
117+ nxp,dvs-run-voltage = <950000>;
118+ nxp,dvs-standby-voltage = <850000>;
102119 };
103120
104121 buck4: BUCK4 {
@@ -153,14 +170,14 @@
153170 regulator-compatible = "LDO4";
154171 regulator-min-microvolt = <800000>;
155172 regulator-max-microvolt = <3300000>;
156- regulator-boot-on;
157- regulator-always-on;
158173 };
159174
160175 ldo5: LDO5 {
161176 regulator-compatible = "LDO5";
162177 regulator-min-microvolt = <1800000>;
163178 regulator-max-microvolt = <3300000>;
179+ regulator-boot-on;
180+ regulator-always-on;
164181 };
165182 };
166183 };
@@ -180,6 +197,8 @@
180197
181198 /* eMMC */
182199 &usdhc3 {
200+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
201+ assigned-clock-rates = <400000000>;
183202 pinctrl-names = "default", "state_100mhz", "state_200mhz";
184203 pinctrl-0 = <&pinctrl_usdhc3>;
185204 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
@@ -207,16 +226,27 @@
207226 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
208227 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
209228 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
210- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
211- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
212- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
213- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
214- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
215- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
229+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
230+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
231+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
232+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
233+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
234+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
216235 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
217236 >;
218237 };
219238
239+ pinctrl_flexspi0: flexspi0grp {
240+ fsl,pins = <
241+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
242+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
243+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
244+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
245+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
246+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
247+ >;
248+ };
249+
220250 pinctrl_i2c1: i2c1grp {
221251 fsl,pins = <
222252 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
@@ -273,21 +303,21 @@
273303 fsl,pins = <
274304 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
275305 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
276- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
277- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
278- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
279- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
280- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
281- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
282- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
283- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
306+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
307+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
308+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
309+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
310+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
311+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
312+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
313+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
284314 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
285315 >;
286316 };
287317
288318 pinctrl_wdog: wdoggrp {
289319 fsl,pins = <
290- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
320+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
291321 >;
292322 };
293323 };
--- a/arch/arm/dts/imx8mp-venice-gw74xx.dts
+++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts
@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
22 /*
3- * Copyright 2022 Gateworks Corporation
3+ * Copyright 2021 Gateworks Corporation
44 */
55
66 /dts-v1/;
@@ -485,40 +485,30 @@
485485 reg = <0>;
486486 label = "lan1";
487487 local-mac-address = [00 00 00 00 00 00];
488- phy-handle = <&sw_phy0>;
489- phy-mode = "internal";
490488 };
491489
492490 lan2: port@1 {
493491 reg = <1>;
494492 label = "lan2";
495493 local-mac-address = [00 00 00 00 00 00];
496- phy-handle = <&sw_phy1>;
497- phy-mode = "internal";
498494 };
499495
500496 lan3: port@2 {
501497 reg = <2>;
502498 label = "lan3";
503499 local-mac-address = [00 00 00 00 00 00];
504- phy-handle = <&sw_phy2>;
505- phy-mode = "internal";
506500 };
507501
508502 lan4: port@3 {
509503 reg = <3>;
510504 label = "lan4";
511505 local-mac-address = [00 00 00 00 00 00];
512- phy-handle = <&sw_phy3>;
513- phy-mode = "internal";
514506 };
515507
516508 lan5: port@4 {
517509 reg = <4>;
518510 label = "lan5";
519511 local-mac-address = [00 00 00 00 00 00];
520- phy-handle = <&sw_phy4>;
521- phy-mode = "internal";
522512 };
523513
524514 port@6 {
@@ -533,38 +523,6 @@
533523 };
534524 };
535525 };
536-
537- mdios {
538- #address-cells = <1>;
539- #size-cells = <0>;
540-
541- mdio@0 {
542- reg = <0>;
543- compatible = "microchip,ksz-mdio";
544- #address-cells = <1>;
545- #size-cells = <0>;
546-
547- sw_phy0: ethernet-phy@0 {
548- reg = <0x0>;
549- };
550-
551- sw_phy1: ethernet-phy@1 {
552- reg = <0x1>;
553- };
554-
555- sw_phy2: ethernet-phy@2 {
556- reg = <0x2>;
557- };
558-
559- sw_phy3: ethernet-phy@3 {
560- reg = <0x3>;
561- };
562-
563- sw_phy4: ethernet-phy@4 {
564- reg = <0x4>;
565- };
566- };
567- };
568526 };
569527 };
570528
@@ -842,6 +800,21 @@
842800 >;
843801 };
844802
803+ pinctrl_uart3: uart3grp {
804+ fsl,pins = <
805+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
806+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
807+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
808+ MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
809+ >;
810+ };
811+
812+ pinctrl_uart3_gpio: uart3gpiogrp {
813+ fsl,pins = <
814+ MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119
815+ >;
816+ };
817+
845818 pinctrl_uart4: uart4grp {
846819 fsl,pins = <
847820 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -38,6 +38,7 @@
3838 serial1 = &uart2;
3939 serial2 = &uart3;
4040 serial3 = &uart4;
41+ spi0 = &flexspi;
4142 };
4243
4344 cpus {
@@ -51,7 +52,16 @@
5152 clock-latency = <61036>;
5253 clocks = <&clk IMX8MP_CLK_ARM>;
5354 enable-method = "psci";
55+ i-cache-size = <0x8000>;
56+ i-cache-line-size = <64>;
57+ i-cache-sets = <256>;
58+ d-cache-size = <0x8000>;
59+ d-cache-line-size = <64>;
60+ d-cache-sets = <128>;
5461 next-level-cache = <&A53_L2>;
62+ nvmem-cells = <&cpu_speed_grade>;
63+ nvmem-cell-names = "speed_grade";
64+ operating-points-v2 = <&a53_opp_table>;
5565 #cooling-cells = <2>;
5666 };
5767
@@ -62,7 +72,14 @@
6272 clock-latency = <61036>;
6373 clocks = <&clk IMX8MP_CLK_ARM>;
6474 enable-method = "psci";
75+ i-cache-size = <0x8000>;
76+ i-cache-line-size = <64>;
77+ i-cache-sets = <256>;
78+ d-cache-size = <0x8000>;
79+ d-cache-line-size = <64>;
80+ d-cache-sets = <128>;
6581 next-level-cache = <&A53_L2>;
82+ operating-points-v2 = <&a53_opp_table>;
6683 #cooling-cells = <2>;
6784 };
6885
@@ -73,7 +90,14 @@
7390 clock-latency = <61036>;
7491 clocks = <&clk IMX8MP_CLK_ARM>;
7592 enable-method = "psci";
93+ i-cache-size = <0x8000>;
94+ i-cache-line-size = <64>;
95+ i-cache-sets = <256>;
96+ d-cache-size = <0x8000>;
97+ d-cache-line-size = <64>;
98+ d-cache-sets = <128>;
7699 next-level-cache = <&A53_L2>;
100+ operating-points-v2 = <&a53_opp_table>;
77101 #cooling-cells = <2>;
78102 };
79103
@@ -84,12 +108,52 @@
84108 clock-latency = <61036>;
85109 clocks = <&clk IMX8MP_CLK_ARM>;
86110 enable-method = "psci";
111+ i-cache-size = <0x8000>;
112+ i-cache-line-size = <64>;
113+ i-cache-sets = <256>;
114+ d-cache-size = <0x8000>;
115+ d-cache-line-size = <64>;
116+ d-cache-sets = <128>;
87117 next-level-cache = <&A53_L2>;
118+ operating-points-v2 = <&a53_opp_table>;
88119 #cooling-cells = <2>;
89120 };
90121
91122 A53_L2: l2-cache0 {
92123 compatible = "cache";
124+ cache-level = <2>;
125+ cache-size = <0x80000>;
126+ cache-line-size = <64>;
127+ cache-sets = <512>;
128+ };
129+ };
130+
131+ a53_opp_table: opp-table {
132+ compatible = "operating-points-v2";
133+ opp-shared;
134+
135+ opp-1200000000 {
136+ opp-hz = /bits/ 64 <1200000000>;
137+ opp-microvolt = <850000>;
138+ opp-supported-hw = <0x8a0>, <0x7>;
139+ clock-latency-ns = <150000>;
140+ opp-suspend;
141+ };
142+
143+ opp-1600000000 {
144+ opp-hz = /bits/ 64 <1600000000>;
145+ opp-microvolt = <950000>;
146+ opp-supported-hw = <0xa0>, <0x7>;
147+ clock-latency-ns = <150000>;
148+ opp-suspend;
149+ };
150+
151+ opp-1800000000 {
152+ opp-hz = /bits/ 64 <1800000000>;
153+ opp-microvolt = <1000000>;
154+ opp-supported-hw = <0x20>, <0x3>;
155+ clock-latency-ns = <150000>;
156+ opp-suspend;
93157 };
94158 };
95159
@@ -135,11 +199,21 @@
135199 clock-output-names = "clk_ext4";
136200 };
137201
202+ reserved-memory {
203+ #address-cells = <2>;
204+ #size-cells = <2>;
205+ ranges;
206+
207+ dsp_reserved: dsp@92400000 {
208+ reg = <0 0x92400000 0 0x2000000>;
209+ no-map;
210+ };
211+ };
212+
138213 pmu {
139214 compatible = "arm,cortex-a53-pmu";
140215 interrupts = <GIC_PPI 7
141216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
142- interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
143217 };
144218
145219 psci {
@@ -359,6 +433,10 @@
359433 eth_mac1: mac-address@90 {
360434 reg = <0x90 6>;
361435 };
436+
437+ eth_mac2: mac-address@96 {
438+ reg = <0x96 6>;
439+ };
362440 };
363441
364442 anatop: anatop@30360000 {
@@ -408,7 +486,6 @@
408486 <&clk IMX8MP_CLK_GIC>,
409487 <&clk IMX8MP_CLK_AUDIO_AHB>,
410488 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
411- <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
412489 <&clk IMX8MP_AUDIO_PLL1>,
413490 <&clk IMX8MP_AUDIO_PLL2>;
414491 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
@@ -424,7 +501,6 @@
424501 <500000000>,
425502 <400000000>,
426503 <800000000>,
427- <400000000>,
428504 <393216000>,
429505 <361267200>;
430506 };
@@ -447,6 +523,11 @@
447523 #address-cells = <1>;
448524 #size-cells = <0>;
449525
526+ pgc_mipi_phy1: power-domain@0 {
527+ #power-domain-cells = <0>;
528+ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
529+ };
530+
450531 pgc_pcie_phy: power-domain@1 {
451532 #power-domain-cells = <0>;
452533 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -462,6 +543,45 @@
462543 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
463544 };
464545
546+ pgc_gpu2d: power-domain@6 {
547+ #power-domain-cells = <0>;
548+ reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
549+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
550+ power-domains = <&pgc_gpumix>;
551+ };
552+
553+ pgc_gpumix: power-domain@7 {
554+ #power-domain-cells = <0>;
555+ reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
556+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
557+ <&clk IMX8MP_CLK_GPU_AHB>;
558+ assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
559+ <&clk IMX8MP_CLK_GPU_AHB>;
560+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
561+ <&clk IMX8MP_SYS_PLL1_800M>;
562+ assigned-clock-rates = <800000000>, <400000000>;
563+ };
564+
565+ pgc_gpu3d: power-domain@9 {
566+ #power-domain-cells = <0>;
567+ reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
568+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
569+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
570+ power-domains = <&pgc_gpumix>;
571+ };
572+
573+ pgc_mediamix: power-domain@10 {
574+ #power-domain-cells = <0>;
575+ reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
576+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
577+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
578+ };
579+
580+ pgc_mipi_phy2: power-domain@16 {
581+ #power-domain-cells = <0>;
582+ reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
583+ };
584+
465585 pgc_hsiomix: power-domains@17 {
466586 #power-domain-cells = <0>;
467587 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -471,6 +591,12 @@
471591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
472592 assigned-clock-rates = <500000000>;
473593 };
594+
595+ pgc_ispdwp: power-domain@18 {
596+ #power-domain-cells = <0>;
597+ reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
598+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
599+ };
474600 };
475601 };
476602 };
@@ -489,7 +615,7 @@
489615 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
490616 <&clk IMX8MP_CLK_PWM1_ROOT>;
491617 clock-names = "ipg", "per";
492- #pwm-cells = <2>;
618+ #pwm-cells = <3>;
493619 status = "disabled";
494620 };
495621
@@ -500,7 +626,7 @@
500626 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
501627 <&clk IMX8MP_CLK_PWM2_ROOT>;
502628 clock-names = "ipg", "per";
503- #pwm-cells = <2>;
629+ #pwm-cells = <3>;
504630 status = "disabled";
505631 };
506632
@@ -511,7 +637,7 @@
511637 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
512638 <&clk IMX8MP_CLK_PWM3_ROOT>;
513639 clock-names = "ipg", "per";
514- #pwm-cells = <2>;
640+ #pwm-cells = <3>;
515641 status = "disabled";
516642 };
517643
@@ -522,7 +648,7 @@
522648 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
523649 <&clk IMX8MP_CLK_PWM4_ROOT>;
524650 clock-names = "ipg", "per";
525- #pwm-cells = <2>;
651+ #pwm-cells = <3>;
526652 status = "disabled";
527653 };
528654
@@ -615,11 +741,13 @@
615741 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
616742 <&clk IMX8MP_CLK_UART2_ROOT>;
617743 clock-names = "ipg", "per";
744+ dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
745+ dma-names = "rx", "tx";
618746 status = "disabled";
619747 };
620748
621749 flexcan1: can@308c0000 {
622- compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
750+ compatible = "fsl,imx8mp-flexcan";
623751 reg = <0x308c0000 0x10000>;
624752 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
625753 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
@@ -634,7 +762,7 @@
634762 };
635763
636764 flexcan2: can@308d0000 {
637- compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
765+ compatible = "fsl,imx8mp-flexcan";
638766 reg = <0x308d0000 0x10000>;
639767 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640768 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
@@ -738,6 +866,14 @@
738866 #mbox-cells = <2>;
739867 };
740868
869+ mu2: mailbox@30e60000 {
870+ compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
871+ reg = <0x30e60000 0x10000>;
872+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
873+ #mbox-cells = <2>;
874+ status = "disabled";
875+ };
876+
741877 i2c5: i2c@30ad0000 {
742878 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
743879 #address-cells = <1>;
@@ -759,7 +895,7 @@
759895 };
760896
761897 usdhc1: mmc@30b40000 {
762- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
898+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
763899 reg = <0x30b40000 0x10000>;
764900 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
765901 clocks = <&clk IMX8MP_CLK_DUMMY>,
@@ -773,7 +909,7 @@
773909 };
774910
775911 usdhc2: mmc@30b50000 {
776- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
912+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
777913 reg = <0x30b50000 0x10000>;
778914 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
779915 clocks = <&clk IMX8MP_CLK_DUMMY>,
@@ -787,7 +923,7 @@
787923 };
788924
789925 usdhc3: mmc@30b60000 {
790- compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
926+ compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
791927 reg = <0x30b60000 0x10000>;
792928 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
793929 clocks = <&clk IMX8MP_CLK_DUMMY>,
@@ -854,16 +990,15 @@
854990 nvmem-cells = <&eth_mac1>;
855991 nvmem-cell-names = "mac-address";
856992 fsl,stop-mode = <&gpr 0x10 3>;
857- nvmem_macaddr_swap;
858993 status = "disabled";
859994 };
860995
861996 eqos: ethernet@30bf0000 {
862997 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
863998 reg = <0x30bf0000 0x10000>;
864- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
865- <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
866- interrupt-names = "eth_wake_irq", "macirq";
999+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1000+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1001+ interrupt-names = "macirq", "eth_wake_irq";
8671002 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
8681003 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
8691004 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
@@ -876,6 +1011,8 @@
8761011 <&clk IMX8MP_SYS_PLL2_100M>,
8771012 <&clk IMX8MP_SYS_PLL2_125M>;
8781013 assigned-clock-rates = <0>, <100000000>, <125000000>;
1014+ nvmem-cells = <&eth_mac2>;
1015+ nvmem-cell-names = "mac-address";
8791016 intf_mode = <&gpr 0x4>;
8801017 status = "disabled";
8811018 };
@@ -888,6 +1025,44 @@
8881025 #size-cells = <1>;
8891026 ranges;
8901027
1028+ media_blk_ctrl: blk-ctrl@32ec0000 {
1029+ compatible = "fsl,imx8mp-media-blk-ctrl",
1030+ "syscon";
1031+ reg = <0x32ec0000 0x10000>;
1032+ power-domains = <&pgc_mediamix>,
1033+ <&pgc_mipi_phy1>,
1034+ <&pgc_mipi_phy1>,
1035+ <&pgc_mediamix>,
1036+ <&pgc_mediamix>,
1037+ <&pgc_mipi_phy2>,
1038+ <&pgc_mediamix>,
1039+ <&pgc_ispdwp>,
1040+ <&pgc_ispdwp>,
1041+ <&pgc_mipi_phy2>;
1042+ power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1043+ "lcdif1", "isi", "mipi-csi2",
1044+ "lcdif2", "isp", "dwe",
1045+ "mipi-dsi2";
1046+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1047+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1048+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1049+ <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1050+ <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1051+ <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1052+ <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1053+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1054+ clock-names = "apb", "axi", "cam1", "cam2",
1055+ "disp1", "disp2", "isp", "phy";
1056+
1057+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1058+ <&clk IMX8MP_CLK_MEDIA_APB>;
1059+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1060+ <&clk IMX8MP_SYS_PLL1_800M>;
1061+ assigned-clock-rates = <500000000>, <200000000>;
1062+
1063+ #power-domain-cells = <1>;
1064+ };
1065+
8911066 hsio_blk_ctrl: blk-ctrl@32f10000 {
8921067 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
8931068 reg = <0x32f10000 0x24>;
@@ -903,6 +1078,37 @@
9031078 };
9041079 };
9051080
1081+ gpu3d: gpu@38000000 {
1082+ compatible = "vivante,gc";
1083+ reg = <0x38000000 0x8000>;
1084+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1085+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1086+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1087+ <&clk IMX8MP_CLK_GPU_ROOT>,
1088+ <&clk IMX8MP_CLK_GPU_AHB>;
1089+ clock-names = "core", "shader", "bus", "reg";
1090+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1091+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1092+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1093+ <&clk IMX8MP_SYS_PLL1_800M>;
1094+ assigned-clock-rates = <800000000>, <800000000>;
1095+ power-domains = <&pgc_gpu3d>;
1096+ };
1097+
1098+ gpu2d: gpu@38008000 {
1099+ compatible = "vivante,gc";
1100+ reg = <0x38008000 0x8000>;
1101+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1102+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1103+ <&clk IMX8MP_CLK_GPU_ROOT>,
1104+ <&clk IMX8MP_CLK_GPU_AHB>;
1105+ clock-names = "core", "bus", "reg";
1106+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1107+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1108+ assigned-clock-rates = <800000000>;
1109+ power-domains = <&pgc_gpu2d>;
1110+ };
1111+
9061112 gic: interrupt-controller@38800000 {
9071113 compatible = "arm,gic-v3";
9081114 reg = <0x38800000 0x10000>,
@@ -913,6 +1119,12 @@
9131119 interrupt-parent = <&gic>;
9141120 };
9151121
1122+ edacmc: memory-controller@3d400000 {
1123+ compatible = "snps,ddrc-3.80a";
1124+ reg = <0x3d400000 0x400000>;
1125+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1126+ };
1127+
9161128 ddr-pmu@3d800000 {
9171129 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
9181130 reg = <0x3d800000 0x400000>;
@@ -953,9 +1165,6 @@
9531165 <&clk IMX8MP_CLK_USB_CORE_REF>,
9541166 <&clk IMX8MP_CLK_USB_ROOT>;
9551167 clock-names = "bus_early", "ref", "suspend";
956- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
957- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
958- assigned-clock-rates = <500000000>;
9591168 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
9601169 phys = <&usb3_phy0>, <&usb3_phy0>;
9611170 phy-names = "usb2-phy", "usb3-phy";
@@ -998,14 +1207,22 @@
9981207 <&clk IMX8MP_CLK_USB_CORE_REF>,
9991208 <&clk IMX8MP_CLK_USB_ROOT>;
10001209 clock-names = "bus_early", "ref", "suspend";
1001- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
1002- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
1003- assigned-clock-rates = <500000000>;
10041210 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
10051211 phys = <&usb3_phy1>, <&usb3_phy1>;
10061212 phy-names = "usb2-phy", "usb3-phy";
10071213 snps,dis-u2-freeclk-exists-quirk;
10081214 };
10091215 };
1216+
1217+ dsp: dsp@3b6e8000 {
1218+ compatible = "fsl,imx8mp-dsp";
1219+ reg = <0x3b6e8000 0x88000>;
1220+ mbox-names = "txdb0", "txdb1",
1221+ "rxdb0", "rxdb1";
1222+ mboxes = <&mu2 2 0>, <&mu2 2 1>,
1223+ <&mu2 3 0>, <&mu2 3 1>;
1224+ memory-region = <&dsp_reserved>;
1225+ status = "disabled";
1226+ };
10101227 };
10111228 };